Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23370366

1

T1

1680

T2

1340

T3

987

full_word

7812213

1

T1

731

T2

257

T3

169

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31182259	1			T1	2411		T2	1597		T3	1156
auto[TlIntgErrCmd]	105	1			T269	2		T270	3		T271	4
auto[TlIntgErrData]	101	1			T269	3		T270	3		T271	9
auto[TlIntgErrBoth]	114	1			T269	5		T270	4		T271	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9349021

1

T1

2138

T2

1528

T3

980

auto[1]

21833558

1

T1

273

T2

69

T3

176

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5877551	1			T1	1518		T2	1298		T3	892
auto[TlIntgErrNone]	partial	auto[1]	17492523	1			T1	162		T2	42		T3	95
auto[TlIntgErrNone]	full_word	auto[0]	3471318	1			T1	620		T2	230		T3	88
auto[TlIntgErrNone]	full_word	auto[1]	4340867	1			T1	111		T2	27		T3	81
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T269	1		T270	3		T271	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T269	1		T271	2		T359	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T357	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T359	3		T360	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T269	1		T270	2		T271	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T269	2		T270	1		T271	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T360	2		T364	1		T274	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T271	1		T363	1		T365	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T269	3		T270	2		T271	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T269	1		T270	2		T271	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T269	1		T364	1		T275	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T360	1		T361	1		T274	1