Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24410794

1

T1

2359

T2

14

T3

977

full_word

7940379

1

T1

1556

T2

5

T3

218

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32350903	1			T1	3915		T2	19		T3	1195
auto[TlIntgErrCmd]	94	1			T305	5		T306	6		T307	5
auto[TlIntgErrData]	93	1			T305	3		T306	8		T307	2
auto[TlIntgErrBoth]	83	1			T305	2		T306	6		T307	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9672513

1

T1

3119

T2

4

T3

943

auto[1]

22678660

1

T1

796

T2

15

T3

252

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6212153	1			T1	1871		T2	3		T3	840
auto[TlIntgErrNone]	partial	auto[1]	18198398	1			T1	488		T2	11		T3	137
auto[TlIntgErrNone]	full_word	auto[0]	3460255	1			T1	1248		T2	1		T3	103
auto[TlIntgErrNone]	full_word	auto[1]	4480097	1			T1	308		T2	4		T3	115
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T305	2		T306	1		T307	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T305	3		T306	3		T307	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T306	1		T432	1		T433	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T306	1		T434	2		T433	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T305	1		T306	3		T434	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T305	2		T306	5		T307	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T307	1		T435	1		T436	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1			T306	5		T434	1		T437	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T305	2		T307	2		T434	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T306	1		T438	1		T439	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T307	1		T432	1		T315	2