Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5339869

1

T1

13

T2

1072

T3

541

full_word

2572088

1

T1

6

T2

292

T3

374

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7911667	1			T1	19		T2	1364		T3	915
auto[TlIntgErrCmd]	104	1			T279	1		T280	9		T281	2
auto[TlIntgErrData]	97	1			T279	6		T280	5		T281	4
auto[TlIntgErrBoth]	89	1			T279	3		T280	6		T281	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5845240

1

T1

4

T2

1048

T3

563

auto[1]

2066717

1

T1

15

T2

316

T3

352

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3877329	1			T1	2		T2	891		T3	350
auto[TlIntgErrNone]	partial	auto[1]	1462273	1			T1	11		T2	181		T3	191
auto[TlIntgErrNone]	full_word	auto[0]	1967769	1			T1	2		T2	157		T3	213
auto[TlIntgErrNone]	full_word	auto[1]	604296	1			T1	4		T2	135		T3	161
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T280	3		T281	1		T292	4
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T279	1		T280	6		T281	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T388	1		T290	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T292	1		T390	1		T396	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T279	3		T280	5		T281	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T279	3		T281	1		T292	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T289	2		T394	1		T290	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T281	1		T397	1		T290	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T279	3		T280	4		T281	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T280	2		T281	2		T292	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T292	2		T289	1		T398	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T397	1		T290	1		-	-