Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	452398705	7387525	0	0
check_regwen_rd_A	452398705	4575	0	0
check_timeout_rd_A	452398705	3969	0	0
check_trigger_regwen_rd_A	452398705	4450	0	0
consistency_check_period_rd_A	452398705	4848	0	0
creator_sw_cfg_read_lock_rd_A	452398705	4251	0	0
direct_access_address_rd_A	452398705	2383	0	0
direct_access_wdata_0_rd_A	452398705	1678	0	0
direct_access_wdata_1_rd_A	452398705	2102	0	0
integrity_check_period_rd_A	452398705	4262	0	0
intr_enable_rd_A	452398705	5418	0	0
owner_sw_cfg_read_lock_rd_A	452398705	3794	0	0
rot_creator_auth_codesign_read_lock_rd_A	452398705	4099	0	0
rot_creator_auth_state_read_lock_rd_A	452398705	3841	0	0
vendor_test_read_lock_rd_A	452398705	3574	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	7387525	0	0
T4	756283	162296	0	0
T5	56328	0	0	0
T6	603424	33157	0	0
T7	0	63729	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T12	0	17450	0	0
T13	64282	0	0	0
T14	134137	0	0	0
T16	0	72213	0	0
T23	0	58894	0	0
T31	0	129979	0	0
T102	12342	0	0	0
T148	0	22274	0	0
T158	0	194009	0	0
T164	0	45856	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	4575	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	34	0	0
T31	0	60	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	89	0	0
T139	0	80	0	0
T158	0	204	0	0
T164	0	53	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	36	0	0
T292	0	79	0	0
T327	0	54	0	0
T337	0	37	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	3969	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	28	0	0
T31	0	71	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	104	0	0
T139	0	121	0	0
T158	0	196	0	0
T164	0	87	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	60	0	0
T292	0	116	0	0
T327	0	51	0	0
T337	0	18	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	4450	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	32	0	0
T31	0	80	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	77	0	0
T139	0	66	0	0
T158	0	207	0	0
T164	0	50	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	56	0	0
T292	0	67	0	0
T327	0	46	0	0
T337	0	46	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	4848	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	44	0	0
T31	0	117	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	87	0	0
T139	0	154	0	0
T158	0	270	0	0
T164	0	45	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	72	0	0
T292	0	140	0	0
T327	0	54	0	0
T337	0	31	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	4251	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	34	0	0
T31	0	84	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	70	0	0
T139	0	85	0	0
T158	0	297	0	0
T164	0	43	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	54	0	0
T292	0	95	0	0
T327	0	52	0	0
T337	0	21	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	2383	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	37	0	0
T31	0	80	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	92	0	0
T139	0	88	0	0
T158	0	195	0	0
T164	0	65	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	56	0	0
T292	0	88	0	0
T327	0	91	0	0
T337	0	17	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	1678	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	36	0	0
T31	0	79	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	60	0	0
T139	0	92	0	0
T158	0	146	0	0
T164	0	23	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	73	0	0
T292	0	52	0	0
T327	0	22	0	0
T337	0	2	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	2102	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	23	0	0
T31	0	109	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	41	0	0
T139	0	178	0	0
T158	0	190	0	0
T164	0	38	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	43	0	0
T292	0	113	0	0
T327	0	38	0	0
T337	0	22	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	4262	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	41	0	0
T31	0	48	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	73	0	0
T139	0	57	0	0
T158	0	158	0	0
T164	0	99	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	37	0	0
T292	0	64	0	0
T327	0	40	0	0
T337	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	5418	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	57	0	0
T31	0	79	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T116	0	16	0	0
T119	15260	0	0	0
T138	0	97	0	0
T158	0	228	0	0
T164	0	73	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T292	0	76	0	0
T327	0	48	0	0
T337	0	38	0	0
T338	0	4	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	3794	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	38	0	0
T31	0	85	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	100	0	0
T139	0	92	0	0
T158	0	179	0	0
T164	0	63	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	53	0	0
T292	0	83	0	0
T327	0	63	0	0
T337	0	19	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	4099	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	45	0	0
T31	0	61	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	67	0	0
T139	0	117	0	0
T158	0	222	0	0
T164	0	73	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	64	0	0
T292	0	107	0	0
T327	0	57	0	0
T337	0	18	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	3841	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	32	0	0
T31	0	76	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	94	0	0
T139	0	130	0	0
T158	0	248	0	0
T164	0	75	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	75	0	0
T292	0	80	0	0
T327	0	75	0	0
T337	0	14	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452398705	3574	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T23	284205	35	0	0
T31	0	66	0	0
T70	16235	0	0	0
T74	9688	0	0	0
T93	39898	0	0	0
T94	23532	0	0	0
T119	15260	0	0	0
T138	0	108	0	0
T139	0	86	0	0
T158	0	194	0	0
T164	0	55	0	0
T173	65312	0	0	0
T185	26833	0	0	0
T281	0	76	0	0
T292	0	105	0	0
T327	0	55	0	0
T337	0	28	0	0