Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	475093535	7679306	0	0
check_regwen_rd_A	475093535	2910	0	0
check_timeout_rd_A	475093535	2305	0	0
check_trigger_regwen_rd_A	475093535	2677	0	0
consistency_check_period_rd_A	475093535	2924	0	0
creator_sw_cfg_read_lock_rd_A	475093535	2428	0	0
direct_access_address_rd_A	475093535	1883	0	0
direct_access_wdata_0_rd_A	475093535	1035	0	0
direct_access_wdata_1_rd_A	475093535	1376	0	0
integrity_check_period_rd_A	475093535	2794	0	0
intr_enable_rd_A	475093535	3343	0	0
owner_sw_cfg_read_lock_rd_A	475093535	2329	0	0
rot_creator_auth_codesign_read_lock_rd_A	475093535	2506	0	0
rot_creator_auth_state_read_lock_rd_A	475093535	2273	0	0
vendor_test_read_lock_rd_A	475093535	2234	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	7679306	0	0
T14	103260	22822	0	0
T15	0	18529	0	0
T16	0	36044	0	0
T20	0	51337	0	0
T21	0	27722	0	0
T24	0	40858	0	0
T25	0	61683	0	0
T26	0	32150	0	0
T63	13520	0	0	0
T83	120362	0	0	0
T283	148025	0	0	0
T292	0	49007	0	0
T318	0	40426	0	0
T319	12660	0	0	0
T320	31279	0	0	0
T321	69087	0	0	0
T322	20018	0	0	0
T323	48573	0	0	0
T324	48094	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2910	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	50	0	0
T293	0	17	0	0
T294	0	51	0	0
T329	0	87	0	0
T390	0	28	0	0
T391	0	61	0	0
T392	0	76	0	0
T393	0	163	0	0
T394	0	73	0	0
T395	0	42	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2305	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	31	0	0
T293	0	14	0	0
T294	0	34	0	0
T329	0	90	0	0
T390	0	15	0	0
T391	0	52	0	0
T392	0	106	0	0
T393	0	117	0	0
T394	0	78	0	0
T395	0	30	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2677	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	24	0	0
T293	0	16	0	0
T294	0	40	0	0
T329	0	109	0	0
T390	0	22	0	0
T391	0	52	0	0
T392	0	83	0	0
T393	0	165	0	0
T394	0	69	0	0
T395	0	30	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2924	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	55	0	0
T293	0	32	0	0
T294	0	23	0	0
T329	0	147	0	0
T390	0	35	0	0
T391	0	49	0	0
T392	0	134	0	0
T393	0	118	0	0
T394	0	70	0	0
T395	0	54	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2428	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	20	0	0
T293	0	1	0	0
T294	0	29	0	0
T329	0	104	0	0
T390	0	10	0	0
T391	0	22	0	0
T392	0	121	0	0
T393	0	196	0	0
T394	0	95	0	0
T395	0	54	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	1883	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	46	0	0
T293	0	32	0	0
T294	0	53	0	0
T329	0	138	0	0
T390	0	38	0	0
T391	0	80	0	0
T392	0	79	0	0
T393	0	132	0	0
T394	0	91	0	0
T395	0	42	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	1035	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	3	0	0
T293	0	6	0	0
T294	0	11	0	0
T329	0	82	0	0
T390	0	7	0	0
T391	0	21	0	0
T392	0	81	0	0
T393	0	91	0	0
T394	0	28	0	0
T395	0	27	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	1376	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	33	0	0
T293	0	3	0	0
T294	0	17	0	0
T329	0	81	0	0
T390	0	20	0	0
T391	0	50	0	0
T392	0	117	0	0
T393	0	105	0	0
T394	0	46	0	0
T395	0	29	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2794	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	42	0	0
T293	0	20	0	0
T294	0	16	0	0
T329	0	67	0	0
T390	0	29	0	0
T391	0	36	0	0
T392	0	114	0	0
T393	0	131	0	0
T394	0	51	0	0
T395	0	21	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	3343	0	0
T111	0	47	0	0
T187	9472	0	0	0
T292	0	62	0	0
T293	0	17	0	0
T294	0	34	0	0
T308	614258	43	0	0
T402	0	15	0	0
T403	0	21	0	0
T404	0	15	0	0
T405	0	35	0	0
T406	0	18	0	0
T407	108272	0	0	0
T408	27576	0	0	0
T409	8931	0	0	0
T410	47489	0	0	0
T411	21233	0	0	0
T412	25350	0	0	0
T413	15724	0	0	0
T414	14609	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2329	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	36	0	0
T293	0	18	0	0
T294	0	32	0	0
T329	0	77	0	0
T390	0	15	0	0
T391	0	58	0	0
T392	0	73	0	0
T393	0	167	0	0
T394	0	57	0	0
T395	0	78	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2506	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	57	0	0
T293	0	11	0	0
T294	0	32	0	0
T329	0	124	0	0
T390	0	23	0	0
T391	0	59	0	0
T392	0	101	0	0
T393	0	170	0	0
T394	0	74	0	0
T395	0	48	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2273	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	39	0	0
T293	0	21	0	0
T294	0	41	0	0
T329	0	87	0	0
T390	0	3	0	0
T391	0	44	0	0
T392	0	88	0	0
T393	0	143	0	0
T394	0	61	0	0
T395	0	46	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475093535	2234	0	0
T139	781377	0	0	0
T167	24921	0	0	0
T171	7902	0	0	0
T292	235527	63	0	0
T293	0	7	0	0
T294	0	25	0	0
T329	0	88	0	0
T390	0	27	0	0
T391	0	70	0	0
T392	0	84	0	0
T393	0	131	0	0
T394	0	78	0	0
T395	0	34	0	0
T396	439923	0	0	0
T397	7683	0	0	0
T398	8974	0	0	0
T399	24168	0	0	0
T400	31430	0	0	0
T401	327695	0	0	0