Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101097360	429604	0	0
check_regwen_rd_A	101097360	1710	0	0
check_timeout_rd_A	101097360	558	0	0
check_trigger_regwen_rd_A	101097360	1705	0	0
consistency_check_period_rd_A	101097360	1801	0	0
creator_sw_cfg_read_lock_rd_A	101097360	559	0	0
direct_access_address_rd_A	101097360	468	0	0
direct_access_wdata_0_rd_A	101097360	64	0	0
direct_access_wdata_1_rd_A	101097360	67	0	0
integrity_check_period_rd_A	101097360	1841	0	0
intr_enable_rd_A	101097360	2500	0	0
owner_sw_cfg_read_lock_rd_A	101097360	638	0	0
rot_creator_auth_codesign_read_lock_rd_A	101097360	632	0	0
rot_creator_auth_state_read_lock_rd_A	101097360	628	0	0
vendor_test_read_lock_rd_A	101097360	600	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	429604	0	0
T14	160407	3243	0	0
T15	0	4954	0	0
T16	0	1781	0	0
T81	4679	0	0	0
T82	29133	0	0	0
T83	17640	0	0	0
T98	120701	0	0	0
T99	164462	0	0	0
T134	0	5616	0	0
T135	0	6250	0	0
T136	0	12981	0	0
T137	0	2057	0	0
T147	17767	0	0	0
T214	54356	0	0	0
T215	260560	0	0	0
T263	51078	0	0	0
T278	0	975	0	0
T293	0	1913	0	0
T297	0	4497	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	1710	0	0
T15	278775	18	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	15	0	0
T137	0	16	0	0
T220	0	27	0	0
T278	0	21	0	0
T293	0	16	0	0
T340	0	5	0	0
T341	0	22	0	0
T342	0	31	0	0
T343	0	44	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	558	0	0
T15	278775	32	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	13	0	0
T137	0	27	0	0
T220	0	46	0	0
T278	0	15	0	0
T293	0	24	0	0
T340	0	4	0	0
T341	0	27	0	0
T342	0	51	0	0
T343	0	47	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	1705	0	0
T15	278775	17	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	24	0	0
T137	0	19	0	0
T220	0	31	0	0
T278	0	2	0	0
T293	0	14	0	0
T340	0	5	0	0
T341	0	13	0	0
T342	0	50	0	0
T343	0	38	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	1801	0	0
T15	278775	50	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	33	0	0
T137	0	19	0	0
T220	0	39	0	0
T278	0	9	0	0
T293	0	10	0	0
T340	0	17	0	0
T341	0	33	0	0
T342	0	44	0	0
T343	0	37	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	559	0	0
T15	278775	36	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	23	0	0
T137	0	18	0	0
T220	0	53	0	0
T278	0	8	0	0
T293	0	25	0	0
T340	0	13	0	0
T341	0	6	0	0
T342	0	30	0	0
T343	0	57	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	468	0	0
T15	278775	35	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	22	0	0
T137	0	12	0	0
T220	0	60	0	0
T278	0	6	0	0
T293	0	17	0	0
T340	0	8	0	0
T341	0	18	0	0
T342	0	82	0	0
T343	0	47	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	64	0	0
T137	131966	7	0	0
T208	147324	0	0	0
T209	16817	0	0	0
T220	0	10	0	0
T340	0	7	0	0
T342	0	16	0	0
T343	0	10	0	0
T351	0	1	0	0
T352	0	4	0	0
T353	0	9	0	0
T354	4107	0	0	0
T355	26409	0	0	0
T356	72640	0	0	0
T357	33843	0	0	0
T358	64414	0	0	0
T359	52689	0	0	0
T360	81406	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	67	0	0
T15	278775	3	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	5	0	0
T220	0	2	0	0
T293	0	7	0	0
T341	0	9	0	0
T342	0	22	0	0
T343	0	4	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0
T353	0	3	0	0
T361	0	7	0	0
T362	0	1	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	1841	0	0
T15	278775	17	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	17	0	0
T137	0	18	0	0
T220	0	59	0	0
T278	0	10	0	0
T293	0	36	0	0
T340	0	10	0	0
T341	0	25	0	0
T342	0	38	0	0
T343	0	45	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	2500	0	0
T15	0	50	0	0
T98	120701	1	0	0
T99	164462	0	0	0
T109	0	9	0	0
T118	51967	0	0	0
T135	0	47	0	0
T137	0	100	0	0
T205	0	9	0	0
T207	27356	0	0	0
T214	54356	0	0	0
T215	260560	0	0	0
T220	0	74	0	0
T263	51078	0	0	0
T278	0	8	0	0
T293	0	26	0	0
T340	0	10	0	0
T363	26153	0	0	0
T364	3973	0	0	0
T365	21017	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	638	0	0
T15	278775	39	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	21	0	0
T137	0	20	0	0
T220	0	44	0	0
T278	0	15	0	0
T293	0	25	0	0
T340	0	7	0	0
T341	0	18	0	0
T342	0	60	0	0
T343	0	50	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	632	0	0
T15	278775	19	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	34	0	0
T137	0	16	0	0
T220	0	63	0	0
T278	0	5	0	0
T293	0	26	0	0
T340	0	29	0	0
T341	0	13	0	0
T342	0	54	0	0
T343	0	56	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	628	0	0
T15	278775	8	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	39	0	0
T137	0	23	0	0
T220	0	52	0	0
T278	0	14	0	0
T293	0	28	0	0
T340	0	7	0	0
T341	0	15	0	0
T342	0	57	0	0
T343	0	35	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101097360	600	0	0
T15	278775	26	0	0
T22	10583	0	0	0
T66	12615	0	0	0
T135	0	28	0	0
T137	0	31	0	0
T220	0	58	0	0
T278	0	7	0	0
T293	0	24	0	0
T340	0	9	0	0
T341	0	17	0	0
T342	0	60	0	0
T343	0	33	0	0
T344	16307	0	0	0
T345	19925	0	0	0
T346	37143	0	0	0
T347	20534	0	0	0
T348	287064	0	0	0
T349	96731	0	0	0
T350	31980	0	0	0