Unified Coverage Report :: Module :: prim_secded_hamming_22_16_dec

Module : prim_secded_hamming_22_16_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_22_16_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_dec	100.00	100.00	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.45	97.27	100.00		100.00	100.00	100.00	gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_secded_hamming_22_16_dec

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	16	24	24	100.00

15                          // Syndrome calculation
16         1/1              syndrome_o[0] = ^(data_i & 22'h01AD5B);
           Tests:       T1 T2 T3 
17         1/1              syndrome_o[1] = ^(data_i & 22'h02366D);
           Tests:       T1 T2 T3 
18         1/1              syndrome_o[2] = ^(data_i & 22'h04C78E);
           Tests:       T1 T2 T3 
19         1/1              syndrome_o[3] = ^(data_i & 22'h0807F0);
           Tests:       T1 T2 T3 
20         1/1              syndrome_o[4] = ^(data_i & 22'h10F800);
           Tests:       T1 T2 T3 
21         1/1              syndrome_o[5] = ^(data_i & 22'h3FFFFF);
           Tests:       T1 T2 T3 
22                      
23                          // Corrected output calculation
24         1/1              data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
           Tests:       T1 T2 T3 
25         1/1              data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
           Tests:       T1 T2 T3 
26         1/1              data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
           Tests:       T1 T2 T3 
27         1/1              data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
           Tests:       T1 T2 T3 
28         1/1              data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
           Tests:       T1 T2 T3 
29         1/1              data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
           Tests:       T1 T2 T3 
30         1/1              data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
           Tests:       T1 T2 T3 
31         1/1              data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
           Tests:       T1 T2 T3 
32         1/1              data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
           Tests:       T1 T2 T3 
33         1/1              data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
           Tests:       T1 T2 T3 
34         1/1              data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
           Tests:       T1 T2 T3 
35         1/1              data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
           Tests:       T1 T2 T3 
36         1/1              data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
           Tests:       T1 T2 T3 
37         1/1              data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
           Tests:       T1 T2 T3 
38         1/1              data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
           Tests:       T1 T2 T3 
39         1/1              data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
           Tests:       T1 T2 T3 
40                      
41                          // err_o calc. bit0: single error, bit1: double error
42         1/1              err_o[0] = syndrome_o[5];
           Tests:       T1 T2 T3 
43         1/1              err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_secded_hamming_22_16_dec

	Total	Covered	Percent
Conditions	99	99	100.00
Logical	99	99	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION ((syndrome_o == 6'h23) ^ data_i[0])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T84,T198,T80
1	1	Covered	T26,T64,T263

 LINE       24
 SUB-EXPRESSION (syndrome_o == 6'h23)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T84,T198

 LINE       25
 EXPRESSION ((syndrome_o == 6'h25) ^ data_i[1])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T159,T35
1	1	Covered	T7,T102,T51

 LINE       25
 SUB-EXPRESSION (syndrome_o == 6'h25)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T74,T102

 LINE       26
 EXPRESSION ((syndrome_o == 6'h26) ^ data_i[2])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T56,T366
1	1	Covered	T7,T74,T28

 LINE       26
 SUB-EXPRESSION (syndrome_o == 6'h26)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T74,T28

 LINE       27
 EXPRESSION ((syndrome_o == 6'h27) ^ data_i[3])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90,T127,T110
1	1	Covered	T74,T8,T27

 LINE       27
 SUB-EXPRESSION (syndrome_o == 6'h27)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T74,T8,T27

 LINE       28
 EXPRESSION ((syndrome_o == 6'h29) ^ data_i[4])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T50,T56
1	1	Covered	T6,T7,T74

 LINE       28
 SUB-EXPRESSION (syndrome_o == 6'h29)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T74

 LINE       29
 EXPRESSION ((syndrome_o == 6'h2a) ^ data_i[5])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T89,T35,T263
1	1	Covered	T2,T4,T7

 LINE       29
 SUB-EXPRESSION (syndrome_o == 6'h2a)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       30
 EXPRESSION ((syndrome_o == 6'h2b) ^ data_i[6])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T159,T366
1	1	Covered	T2,T27,T28

 LINE       30
 SUB-EXPRESSION (syndrome_o == 6'h2b)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T74,T27

 LINE       31
 EXPRESSION ((syndrome_o == 6'h2c) ^ data_i[7])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T50,T36
1	1	Covered	T18,T198,T51

 LINE       31
 SUB-EXPRESSION (syndrome_o == 6'h2c)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T198

 LINE       32
 EXPRESSION ((syndrome_o == 6'h2d) ^ data_i[8])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T119,T132
1	1	Covered	T85,T27,T91

 LINE       32
 SUB-EXPRESSION (syndrome_o == 6'h2d)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T85,T27,T91

 LINE       33
 EXPRESSION ((syndrome_o == 6'h2e) ^ data_i[9])
             ----------1----------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T9,T28
1	1	Covered	T48,T9,T27

 LINE       33
 SUB-EXPRESSION (syndrome_o == 6'h2e)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T48,T9

 LINE       34
 EXPRESSION ((syndrome_o == 6'h2f) ^ data_i[10])
             ----------1----------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T102,T83,T367
1	1	Covered	T5,T18,T27

 LINE       34
 SUB-EXPRESSION (syndrome_o == 6'h2f)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T18,T102

 LINE       35
 EXPRESSION ((syndrome_o == 6'h31) ^ data_i[11])
             ----------1----------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T119
1	1	Covered	T88,T198,T35

 LINE       35
 SUB-EXPRESSION (syndrome_o == 6'h31)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T18,T88

 LINE       36
 EXPRESSION ((syndrome_o == 6'h32) ^ data_i[12])
             ----------1----------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T110,T366
1	1	Covered	T85,T9,T27

 LINE       36
 SUB-EXPRESSION (syndrome_o == 6'h32)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T85,T9

 LINE       37
 EXPRESSION ((syndrome_o == 6'h33) ^ data_i[13])
             ----------1----------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T95,T112
1	1	Covered	T28,T215,T50

 LINE       37
 SUB-EXPRESSION (syndrome_o == 6'h33)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T28,T95

 LINE       38
 EXPRESSION ((syndrome_o == 6'h34) ^ data_i[14])
             ----------1----------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T9
1	1	Covered	T17,T26,T27

 LINE       38
 SUB-EXPRESSION (syndrome_o == 6'h34)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T17

 LINE       39
 EXPRESSION ((syndrome_o == 6'h35) ^ data_i[15])
             ----------1----------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T88,T98
1	1	Covered	T102,T50,T368

 LINE       39
 SUB-EXPRESSION (syndrome_o == 6'h35)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T102,T88

 LINE       43
 EXPRESSION (((|syndrome_o[4:0])) & ((~syndrome_o[5])))
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5