Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.46	91.21	93.10		80.00	90.70	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	94.20	93.10	98.55	80.00	91.07	94.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.12	96.70	93.94		83.33	95.45	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.27	97.83	93.94	98.55	83.33	94.74	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84	96.70	93.94		86.96	95.45	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.87	97.83	93.94	98.55	86.96	94.74	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	83	91.21
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	66	58	87.88
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149                         assign otp_err = otp_err_e'(otp_err_i);
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153        1/1                if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
           Tests:       T1 T2 T3 
154        1/1                  otp_err = NoError;
           Tests:       T2 T5 T6 
155                           end else begin
156        1/1                  otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                   ==>  MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        excluded                   error_d = MacroEccCorrError;
Exclude Annotation: VC_COV_UNR
222                                 end
                        MISSING_ELSE
223                               end else begin
224        0/1     ==>              state_d = ErrorSt;
225        0/1     ==>              error_d = otp_err;
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T4 T5 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T4 T5 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T4 T5 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T4 T5 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T4 T5 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T4 T5 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T4 T5 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T4 T5 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T4 T5 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T7 T17 T18 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T7 T17 T18 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T7 T17 T18 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T7 T17 T18 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T4 T5 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T4 T5 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T4 T5 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T4 T5 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T4 T5 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T4 T5 
273        excluded                   error_d = MacroEccCorrError;
Exclude Annotation: VC_COV_UNR
274                                 end
                        MISSING_ELSE
275                               end else begin
276        0/1     ==>              state_d = ErrorSt;
277        0/1     ==>              error_d = otp_err;
278                                 // This causes the TL-UL adapter to return a bus error.
279        0/1     ==>              tlul_rerror_o = 2'b11;
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T3 T5 
289        1/1                    error_d = FsmStateError;
           Tests:       T19 T20 T21 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T3 T5 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T3 T13 T8 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T3 T13 T8 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T3 T5 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T3 T13 T8 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T3 T13 T8 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        0/1     ==>        state_d = ErrorSt;
316        0/1     ==>        if (state_q != ErrorSt) begin
317        0/1     ==>          error_d = CheckFailError;
318                           end
                   ==>  MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T3 T5 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T3 T5 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T3 T5 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T3 T5 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339        1/1              assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
           Tests:       T1 T2 T3 
340                     
341                       end else begin : gen_nonzero_offset
342                         assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	27	93.10
Logical	29	27	93.10
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T4,T5
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T13
1	1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T4,T5
ReadWaitSt	252	Covered	T2,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T2,T4,T5
InitSt->ErrorSt	315	Covered	T105,T106
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T107,T108,T109
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T7,T17,T18
ReadSt->ReadWaitSt	252	Covered	T2,T4,T5
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T4,T5
ResetSt->ErrorSt	315	Covered	T61,T62,T63
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	3	75.00	(Not included in score)
Transitions	7	5	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T7,T17,T18
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T9,T64
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T7,T17,T18
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T7,T17,T18
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		43	39	90.70
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	20	18	90.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T17,T59,T65
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T17,T18
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T13,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T13,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

153              if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
                 -1-  
154                otp_err = NoError;
                   ==>
155              end else begin
156                otp_err = otp_err_e'(otp_err_i);
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	24	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	24	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	98207139	97364126	0	0
DigestKnown_A	98207139	97364126	0	0
DigestOffsetMustBeRepresentable_A	1134	1134	0	0
EccErrorState_A	98207139	0	0	0
ErrorKnown_A	98207139	97364126	0	0
FsmStateKnown_A	98207139	97364126	0	0
InitDoneKnown_A	98207139	97364126	0	0
InitReadLocksPartition_A	98207139	16826097	0	0
InitWriteLocksPartition_A	98207139	16826097	0	0
OffsetMustBeBlockAligned_A	1134	1134	0	0
OtpAddrKnown_A	98207139	97364126	0	0
OtpCmdKnown_A	98207139	97364126	0	0
OtpErrorState_A	98207139	0	0	0
OtpReqKnown_A	98207139	97364126	0	0
OtpSizeKnown_A	98207139	97364126	0	0
OtpWdataKnown_A	98207139	97364126	0	0
ReadLockPropagation_A	98207139	17779899	0	0
SizeMustBeBlockAligned_A	1134	1134	0	0
TlulGntKnown_A	98207139	97364126	0	0
TlulRdataKnown_A	98207139	97364126	0	0
TlulReadOnReadLock_A	98207139	6078	0	0
TlulRerrorKnown_A	98207139	97364126	0	0
TlulRvalidKnown_A	98207139	97364126	0	0
WriteLockPropagation_A	98207139	3158673	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	98207139	32313617	0	0
u_state_regs_A	98207139	97364126	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	16826097	0	0
T1	5052	45	0	0
T2	12258	4471	0	0
T3	15564	7354	0	0
T4	12945	641	0	0
T5	14286	4202	0	0
T6	44910	3822	0	0
T7	53433	8389	0	0
T11	4718	56	0	0
T12	38234	435	0	0
T13	12599	7109	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	16826097	0	0
T1	5052	45	0	0
T2	12258	4471	0	0
T3	15564	7354	0	0
T4	12945	641	0	0
T5	14286	4202	0	0
T6	44910	3822	0	0
T7	53433	8389	0	0
T11	4718	56	0	0
T12	38234	435	0	0
T13	12599	7109	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	17779899	0	0
T7	53433	10421	0	0
T8	0	16581	0	0
T9	0	76813	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	67529	963	0	0
T18	0	3304	0	0
T26	42930	6846	0	0
T27	0	4465	0	0
T38	0	535	0	0
T48	0	1645	0	0
T59	0	435	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T75	28810	0	0	0
T85	15758	0	0	0
T86	6255	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	6078	0	0
T3	15564	3	0	0
T4	12945	0	0	0
T5	14286	0	0	0
T6	44910	0	0	0
T7	53433	3	0	0
T8	0	7	0	0
T9	0	24	0	0
T11	4718	0	0	0
T12	38234	0	0	0
T13	12599	10	0	0
T17	0	2	0	0
T18	0	1	0	0
T27	0	4	0	0
T48	0	1	0	0
T65	0	8	0	0
T73	30085	0	0	0
T74	31023	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	3158673	0	0
T8	27870	0	0	0
T9	95099	0	0	0
T18	38533	2279	0	0
T27	45676	0	0	0
T38	18908	932	0	0
T48	60443	0	0	0
T59	0	2945	0	0
T65	0	6877	0	0
T87	16300	0	0	0
T88	0	32303	0	0
T89	0	1921	0	0
T91	0	4413	0	0
T93	0	2340	0	0
T94	0	813	0	0
T95	0	5193	0	0
T101	10187	0	0	0
T102	28978	0	0	0
T103	15859	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	32313617	0	0
T2	12258	3242	0	0
T3	15564	2941	0	0
T4	12945	0	0	0
T5	14286	0	0	0
T6	44910	0	0	0
T7	53433	0	0	0
T11	4718	0	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	0	17463	0	0
T18	0	22104	0	0
T26	0	29405	0	0
T38	0	12613	0	0
T48	0	44877	0	0
T59	0	17482	0	0
T65	0	56076	0	0
T73	30085	0	0	0
T84	0	25356	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	88	96.70
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	65	95.59
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T2 T22 T23 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T5 T24 T25 
225        1/1                      error_d = otp_err;
           Tests:       T5 T24 T25 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T5 T7 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T5 T7 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T5 T7 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T5 T7 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T5 T7 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T5 T7 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T5 T7 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T5 T7 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T5 T7 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T7 T26 T18 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T7 T26 T18 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T7 T26 T18 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T7 T26 T18 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T5 T7 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T5 T7 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T5 T7 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T5 T7 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T5 T7 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T5 T7 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T7 T27 T28 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T29 T30 T31 
277        1/1                      error_d = otp_err;
           Tests:       T29 T30 T31 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T29 T30 T31 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T3 T5 
289        1/1                    error_d = FsmStateError;
           Tests:       T19 T20 T21 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T3 T5 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T3 T6 T7 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T3 T6 T7 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T3 T5 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T3 T6 T7 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T3 T6 T7 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        0/1     ==>        state_d = ErrorSt;
316        0/1     ==>        if (state_q != ErrorSt) begin
317        0/1     ==>          error_d = CheckFailError;
318                           end
                   ==>  MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T3 T5 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T3 T5 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T3 T5 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T3 T6 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T5 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	31	93.94
Logical	33	31	93.94
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T22,T23

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T7,T27,T28

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T2,T5,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T5,T7
ReadWaitSt	252	Covered	T2,T5,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T2,T5,T7
InitSt->ErrorSt	315	Covered	T107,T108,T109
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T5,T24,T25
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T7,T26,T18
ReadSt->ReadWaitSt	252	Covered	T2,T5,T7
ReadWaitSt->ErrorSt	276	Covered	T29,T30,T31
ReadWaitSt->IdleSt	270	Covered	T2,T5,T7
ResetSt->ErrorSt	315	Covered	T61,T62,T63
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	8	72.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T7,T26,T18
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Covered	T2,T7,T27
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T56,T110
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T7,T26,T18
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T56,T58
MacroEccCorrError->NoError	235	Covered	T7,T27,T28
NoError->AccessError	256	Covered	T7,T26,T18
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T3,T6,T7
NoError->MacroEccCorrError	221	Covered	T2,T7,T27

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	42	95.45
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T7

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T7

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T23
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T5,T24,T25
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T5,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T65,T78,T80
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T26,T18
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T7,T27,T28
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T5,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T29,T30,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	98207139	97364126	0	0
DigestKnown_A	98207139	97364126	0	0
DigestOffsetMustBeRepresentable_A	1134	1134	0	0
EccErrorState_A	98207139	0	0	0
ErrorKnown_A	98207139	97364126	0	0
FsmStateKnown_A	98207139	97364126	0	0
InitDoneKnown_A	98207139	97364126	0	0
InitReadLocksPartition_A	98207139	17004174	0	0
InitWriteLocksPartition_A	98207139	17004174	0	0
OffsetMustBeBlockAligned_A	1134	1134	0	0
OtpAddrKnown_A	98207139	97364126	0	0
OtpCmdKnown_A	98207139	97364126	0	0
OtpErrorState_A	98207139	78	0	0
OtpReqKnown_A	98207139	97364126	0	0
OtpSizeKnown_A	98207139	97364126	0	0
OtpWdataKnown_A	98207139	97364126	0	0
ReadLockPropagation_A	98207139	17993616	0	0
SizeMustBeBlockAligned_A	1134	1134	0	0
TlulGntKnown_A	98207139	97364126	0	0
TlulRdataKnown_A	98207139	97364126	0	0
TlulReadOnReadLock_A	98207139	6150	0	0
TlulRerrorKnown_A	98207139	97364126	0	0
TlulRvalidKnown_A	98207139	97364126	0	0
WriteLockPropagation_A	98207139	3353606	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	98207139	32455064	0	0
u_state_regs_A	98207139	97364126	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	17004174	0	0
T1	5052	62	0	0
T2	12258	4522	0	0
T3	15564	7405	0	0
T4	12945	709	0	0
T5	14286	4243	0	0
T6	44910	3907	0	0
T7	53433	8576	0	0
T11	4718	73	0	0
T12	38234	452	0	0
T13	12599	7143	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	17004174	0	0
T1	5052	62	0	0
T2	12258	4522	0	0
T3	15564	7405	0	0
T4	12945	709	0	0
T5	14286	4243	0	0
T6	44910	3907	0	0
T7	53433	8576	0	0
T11	4718	73	0	0
T12	38234	452	0	0
T13	12599	7143	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	78	0	0
T5	14286	1	0	0
T6	44910	0	0	0
T7	53433	0	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	67529	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	42930	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T75	28810	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	17993616	0	0
T7	53433	2479	0	0
T9	0	76803	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	67529	790	0	0
T18	0	3131	0	0
T26	42930	11964	0	0
T27	0	3526	0	0
T48	0	2395	0	0
T59	0	615	0	0
T65	0	4769	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T75	28810	0	0	0
T84	0	3655	0	0
T85	15758	0	0	0
T86	6255	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	6150	0	0
T3	15564	8	0	0
T4	12945	0	0	0
T5	14286	0	0	0
T6	44910	1	0	0
T7	53433	2	0	0
T8	0	15	0	0
T9	0	18	0	0
T11	4718	0	0	0
T12	38234	0	0	0
T13	12599	2	0	0
T18	0	4	0	0
T26	0	4	0	0
T48	0	2	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T87	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	3353606	0	0
T7	53433	5041	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	67529	0	0	0
T26	42930	0	0	0
T65	0	1253	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T75	28810	0	0	0
T85	15758	0	0	0
T86	6255	0	0	0
T88	0	29825	0	0
T89	0	5446	0	0
T90	0	48165	0	0
T91	0	2729	0	0
T92	0	10431	0	0
T93	0	2509	0	0
T94	0	5933	0	0
T95	0	10135	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	32455064	0	0
T3	15564	2924	0	0
T4	12945	0	0	0
T5	14286	3273	0	0
T6	44910	0	0	0
T7	53433	28218	0	0
T11	4718	0	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T18	0	22019	0	0
T26	0	29320	0	0
T38	0	12545	0	0
T48	0	27952	0	0
T59	0	11644	0	0
T65	0	60539	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T84	0	25237	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	88	96.70
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	65	95.59
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T32 T33 T34 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T35 T36 T37 
225        1/1                      error_d = otp_err;
           Tests:       T35 T36 T37 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T5 T7 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T5 T7 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T5 T7 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T5 T7 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T5 T7 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T5 T7 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T5 T7 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T5 T7 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T5 T7 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T26 T38 T18 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T26 T38 T18 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T26 T38 T18 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T26 T38 T18 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T5 T7 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T5 T7 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T5 T7 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T5 T7 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T5 T7 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T5 T7 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T7 T27 T39 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T40 T41 T42 
277        1/1                      error_d = otp_err;
           Tests:       T40 T41 T42 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T40 T41 T42 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T3 T5 
289        1/1                    error_d = FsmStateError;
           Tests:       T19 T20 T21 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T3 T5 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T3 T6 T7 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T3 T6 T7 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T3 T5 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T3 T6 T7 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T3 T6 T7 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        0/1     ==>        state_d = ErrorSt;
316        0/1     ==>        if (state_q != ErrorSt) begin
317        0/1     ==>          error_d = CheckFailError;
318                           end
                   ==>  MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T3 T5 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T3 T5 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T3 T5 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T3 T5 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T5 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	31	93.94
Logical	33	31	93.94
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T33,T34

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T12
1	Covered	T7,T27,T39

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T2,T5,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T26

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T26

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T5,T7
ReadWaitSt	252	Covered	T2,T5,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T2,T5,T7
InitSt->ErrorSt	315	Covered	T107,T108,T109
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T5,T35,T24
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T26,T38,T18
ReadSt->ReadWaitSt	252	Covered	T2,T5,T7
ReadWaitSt->ErrorSt	276	Covered	T40,T41,T42
ReadWaitSt->IdleSt	270	Covered	T2,T5,T7
ResetSt->ErrorSt	315	Covered	T61,T62,T63
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	10	8	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T26,T38,T18
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T7,T27,T32
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T64,T99
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T26,T38,T18
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Excluded		VC_COV_UNR
MacroEccCorrError->FsmStateError	325	Covered	T32,T56,T111
MacroEccCorrError->NoError	235	Covered	T7,T27,T39
NoError->AccessError	256	Covered	T26,T38,T18
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T7,T27,T32

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	42	95.45
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T7

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T7

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T26
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T35,T36,T37
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T5,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T59,T65,T78
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T26,T38,T18
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T7,T27,T39
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T5,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T40,T41,T42
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	98207139	97364126	0	0
DigestKnown_A	98207139	97364126	0	0
DigestOffsetMustBeRepresentable_A	1134	1134	0	0
EccErrorState_A	98207139	0	0	0
ErrorKnown_A	98207139	97364126	0	0
FsmStateKnown_A	98207139	97364126	0	0
InitDoneKnown_A	98207139	97364126	0	0
InitReadLocksPartition_A	98207139	17181121	0	0
InitWriteLocksPartition_A	98207139	17181121	0	0
OffsetMustBeBlockAligned_A	1134	1134	0	0
OtpAddrKnown_A	98207139	97364126	0	0
OtpCmdKnown_A	98207139	97364126	0	0
OtpErrorState_A	98207139	49	0	0
OtpReqKnown_A	98207139	97364126	0	0
OtpSizeKnown_A	98207139	97364126	0	0
OtpWdataKnown_A	98207139	97364126	0	0
ReadLockPropagation_A	98207139	18511881	0	0
SizeMustBeBlockAligned_A	1134	1134	0	0
TlulGntKnown_A	98207139	97364126	0	0
TlulRdataKnown_A	98207139	97364126	0	0
TlulReadOnReadLock_A	98207139	6418	0	0
TlulRerrorKnown_A	98207139	97364126	0	0
TlulRvalidKnown_A	98207139	97364126	0	0
WriteLockPropagation_A	98207139	1586705	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	98207139	21326242	0	0
u_state_regs_A	98207139	97364126	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	17181121	0	0
T1	5052	79	0	0
T2	12258	4573	0	0
T3	15564	7456	0	0
T4	12945	777	0	0
T5	14286	4277	0	0
T6	44910	3992	0	0
T7	53433	8763	0	0
T11	4718	90	0	0
T12	38234	469	0	0
T13	12599	7177	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	17181121	0	0
T1	5052	79	0	0
T2	12258	4573	0	0
T3	15564	7456	0	0
T4	12945	777	0	0
T5	14286	4277	0	0
T6	44910	3992	0	0
T7	53433	8763	0	0
T11	4718	90	0	0
T12	38234	469	0	0
T13	12599	7177	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	49	0	0
T14	160407	0	0	0
T22	0	1	0	0
T35	13127	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T76	23268	0	0	0
T77	31204	0	0	0
T78	62139	0	0	0
T79	24933	0	0	0
T80	65248	0	0	0
T81	4679	0	0	0
T82	29133	0	0	0
T83	17640	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	18511881	0	0
T7	53433	4469	0	0
T8	0	16579	0	0
T9	0	76793	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	67529	936	0	0
T18	0	3005	0	0
T26	42930	4779	0	0
T27	0	3021	0	0
T38	0	533	0	0
T48	0	2897	0	0
T59	0	613	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T75	28810	0	0	0
T85	15758	0	0	0
T86	6255	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1134	1134	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	6418	0	0
T3	15564	6	0	0
T4	12945	0	0	0
T5	14286	0	0	0
T6	44910	1	0	0
T7	53433	2	0	0
T8	0	18	0	0
T9	0	17	0	0
T11	4718	0	0	0
T12	38234	0	0	0
T13	12599	3	0	0
T18	0	1	0	0
T26	0	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T73	30085	0	0	0
T74	31023	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	1586705	0	0
T8	27870	0	0	0
T18	38533	0	0	0
T26	42930	6733	0	0
T38	18908	932	0	0
T48	60443	1069	0	0
T65	0	4282	0	0
T75	28810	0	0	0
T84	0	1996	0	0
T85	15758	0	0	0
T86	6255	0	0	0
T87	16300	0	0	0
T89	0	3525	0	0
T90	0	9882	0	0
T93	0	2340	0	0
T94	0	346	0	0
T95	0	14901	0	0
T101	10187	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	21326242	0	0
T3	15564	2907	0	0
T4	12945	0	0	0
T5	14286	0	0	0
T6	44910	0	0	0
T7	53433	0	0	0
T11	4718	0	0	0
T12	38234	0	0	0
T13	12599	0	0	0
T17	0	17293	0	0
T26	0	29235	0	0
T38	0	12477	0	0
T48	0	44503	0	0
T65	0	60267	0	0
T73	30085	0	0	0
T74	31023	0	0	0
T84	0	25118	0	0
T88	0	194095	0	0
T89	0	45885	0	0
T90	0	81460	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98207139	97364126	0	0
T1	5052	4984	0	0
T2	12258	11957	0	0
T3	15564	15293	0	0
T4	12945	12680	0	0
T5	14286	14015	0	0
T6	44910	44443	0	0
T7	53433	52641	0	0
T11	4718	4645	0	0
T12	38234	38172	0	0
T13	12599	12405	0	0