Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	68.38			68.38
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	69.85			69.85
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	74.26			74.26
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	74.26			74.26
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	76.47			76.47
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	97.14			97.14
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.38			68.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.38			68.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14			97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T7,T17,T26	Yes	T3,T7,T17	INPUT
data_o[63:0]	Yes	Yes	T7,T17,T26	Yes	T3,T7,T17	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	186	68.38
Total Bits 0->1	136	93	68.38
Total Bits 1->0	136	93	68.38

Ports	2	0	0.00
Port Bits	272	186	68.38
Port Bits 0->1	136	93	68.38
Port Bits 1->0	136	93	68.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	No	No		No		INPUT
data_i[9:2]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[10]	No	No		No		INPUT
data_i[11]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[12]	No	No		No		INPUT
data_i[18:13]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[27:25]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[36]	No	No		No		INPUT
data_i[37]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[40:38]	No	No		No		INPUT
data_i[42:41]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[47:45]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[49:48]	No	No		No		INPUT
data_i[50]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[51]	No	No		No		INPUT
data_i[54:52]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[55]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[57]	No	No		No		INPUT
data_i[67:58]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[9:2]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[11]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[18:13]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[27:25]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[37]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[40:38]	No	No		No		OUTPUT
data_o[42:41]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[47:45]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[49:48]	No	No		No		OUTPUT
data_o[50]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[54:52]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[63:58]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	190	69.85
Total Bits 0->1	136	95	69.85
Total Bits 1->0	136	95	69.85

Ports	2	0	0.00
Port Bits	272	190	69.85
Port Bits 0->1	136	95	69.85
Port Bits 1->0	136	95	69.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[3]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T6,*T7,*T17	Yes	T6,T7,T17	INPUT
data_i[5]	No	No		No		INPUT
data_i[13:6]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
data_i[14]	No	No		No		INPUT
data_i[20:15]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[23:21]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T7,*T17,*T26	Yes	T7,T17,T26	INPUT
data_i[25]	No	No		No		INPUT
data_i[26]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[27]	No	No		No		INPUT
data_i[28]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[29]	No	No		No		INPUT
data_i[31:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[32]	No	No		No		INPUT
data_i[35:33]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[36]	No	No		No		INPUT
data_i[37]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[39:38]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[44:42]	No	No		No		INPUT
data_i[47:45]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[50]	No	No		No		INPUT
data_i[60:51]	Yes	Yes	T7,T17,T26	Yes	T7,T17,T26	INPUT
data_i[62:61]	No	No		No		INPUT
data_i[67:63]	Yes	Yes	*T7,*T17,*T26	Yes	T7,T17,T26	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[2:0]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T6,*T7,*T17	Yes	T6,T7,T17	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[13:6]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[20:15]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[23:21]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T7,*T17,*T26	Yes	T7,T17,T26	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[26]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[28]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[31:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[35:33]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[37]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[39:38]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[44:42]	No	No		No		OUTPUT
data_o[47:45]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[60:51]	Yes	Yes	T7,T17,T26	Yes	T7,T17,T26	OUTPUT
data_o[62:61]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T7,T17,T26	Yes	T7,T17,T26	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[7:3]	No	No		No		INPUT
data_i[22:8]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[23]	No	No		No		INPUT
data_i[25:24]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[31]	No	No		No		INPUT
data_i[33:32]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[38]	No	No		No		INPUT
data_i[41:39]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[42]	No	No		No		INPUT
data_i[45:43]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[49]	No	No		No		INPUT
data_i[52:50]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[53]	No	No		No		INPUT
data_i[56:54]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[59:57]	No	No		No		INPUT
data_i[61:60]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[2:0]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[7:3]	No	No		No		OUTPUT
data_o[22:8]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[25:24]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[33:32]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[41:39]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[45:43]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[52:50]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[56:54]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[59:57]	No	No		No		OUTPUT
data_o[61:60]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[3]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[6]	No	No		No		INPUT
data_i[14:7]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[17:15]	No	No		No		INPUT
data_i[23:18]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[26]	No	No		No		INPUT
data_i[31:27]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
data_i[32]	No	No		No		INPUT
data_i[39:33]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[40]	No	No		No		INPUT
data_i[42:41]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[52]	No	No		No		INPUT
data_i[53]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[54]	No	No		No		INPUT
data_i[59:55]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
data_i[60]	No	No		No		INPUT
data_i[61]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[14:7]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[17:15]	No	No		No		OUTPUT
data_o[23:18]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[31:27]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[39:33]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[42:41]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[59:55]	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[61]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[5:3]	No	No		No		INPUT
data_i[10:6]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[15]	No	No		No		INPUT
data_i[16]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[19:17]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[24]	No	No		No		INPUT
data_i[31:25]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[32]	No	No		No		INPUT
data_i[35:33]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[37:36]	No	No		No		INPUT
data_i[42:38]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[51:49]	No	No		No		INPUT
data_i[59:52]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[2:0]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[5:3]	No	No		No		OUTPUT
data_o[10:6]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[16]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[19:17]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[31:25]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[35:33]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[37:36]	No	No		No		OUTPUT
data_o[42:38]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[51:49]	No	No		No		OUTPUT
data_o[59:52]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[6:5]	No	No		No		INPUT
data_i[8:7]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[17]	No	No		No		INPUT
data_i[21:18]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[25]	No	No		No		INPUT
data_i[28:26]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[29]	No	No		No		INPUT
data_i[33:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[34]	No	No		No		INPUT
data_i[35]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[36]	No	No		No		INPUT
data_i[39:37]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[42]	No	No		No		INPUT
data_i[47:43]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[48]	No	No		No		INPUT
data_i[52:49]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[53]	No	No		No		INPUT
data_i[61:54]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[0]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[6:5]	No	No		No		OUTPUT
data_o[8:7]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[21:18]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[28:26]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[33:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[35]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[39:37]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[47:43]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[52:49]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[61:54]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	202	74.26
Total Bits 0->1	136	101	74.26
Total Bits 1->0	136	101	74.26

Ports	2	0	0.00
Port Bits	272	202	74.26
Port Bits 0->1	136	101	74.26
Port Bits 1->0	136	101	74.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[5:1]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[14:8]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[19]	No	No		No		INPUT
data_i[27:20]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[31]	No	No		No		INPUT
data_i[33:32]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[38:36]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[39]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[42]	No	No		No		INPUT
data_i[54:43]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[56:55]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T6,*T7,*T26	Yes	T6,T7,T26	INPUT
data_i[59:58]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T6,*T7,*T26	Yes	T6,T7,T26	INPUT
data_i[61]	No	No		No		INPUT
data_i[65:62]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[66]	No	No		No		INPUT
data_i[71:67]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[5:1]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[14:8]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[27:20]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[33:32]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[38:36]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[54:43]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[56:55]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T6,*T7,*T26	Yes	T6,T7,T26	OUTPUT
data_o[59:58]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T6,*T7,*T26	Yes	T6,T7,T26	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	202	74.26
Total Bits 0->1	136	101	74.26
Total Bits 1->0	136	101	74.26

Ports	2	0	0.00
Port Bits	272	202	74.26
Port Bits 0->1	136	101	74.26
Port Bits 1->0	136	101	74.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[10]	No	No		No		INPUT
data_i[13:11]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[15:14]	No	No		No		INPUT
data_i[25:16]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[35:31]	Yes	Yes	*T7,T17,T26	Yes	T7,T17,T26	INPUT
data_i[36]	No	No		No		INPUT
data_i[41:37]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[44:42]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[49]	No	No		No		INPUT
data_i[53:50]	Yes	Yes	T17,T18,T27	Yes	T17,T18,T102	INPUT
data_i[55:54]	No	No		No		INPUT
data_i[61:56]	Yes	Yes	T17,T18,T27	Yes	T17,T18,T102	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[68:64]	Yes	Yes	*T17,T18,T27	Yes	T17,T18,T102	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[5:0]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[13:11]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[15:14]	No	No		No		OUTPUT
data_o[25:16]	Yes	Yes	*T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[35:31]	Yes	Yes	*T7,T17,T26	Yes	T7,T17,T26	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[41:37]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[44:42]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[53:50]	Yes	Yes	T17,T18,T27	Yes	T17,T18,T102	OUTPUT
data_o[55:54]	No	No		No		OUTPUT
data_o[61:56]	Yes	Yes	T17,T18,T27	Yes	T17,T18,T102	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[4:0]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[6:5]	No	No		No		INPUT
data_i[10:7]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T6,*T7,*T73	Yes	T3,T6,T7	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[19:18]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[23]	No	No		No		INPUT
data_i[26:24]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[27]	No	No		No		INPUT
data_i[30:28]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	INPUT
data_i[31]	No	No		No		INPUT
data_i[36:32]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[37]	No	No		No		INPUT
data_i[41:38]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[42]	No	No		No		INPUT
data_i[43]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[44]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[46]	No	No		No		INPUT
data_i[53:47]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[54]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[57:56]	No	No		No		INPUT
data_i[71:58]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[4:0]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[6:5]	No	No		No		OUTPUT
data_o[10:7]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T6,*T7,*T73	Yes	T3,T6,T7	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[19:18]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[26:24]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[30:28]	Yes	Yes	T6,T7,T73	Yes	T3,T6,T7	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[36:32]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[41:38]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[43]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[53:47]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[57:56]	No	No		No		OUTPUT
data_o[63:58]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[1]	No	No		No		INPUT
data_i[5:2]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[9:8]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[10]	No	No		No		INPUT
data_i[15:11]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[19:18]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[23]	No	No		No		INPUT
data_i[27:24]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	INPUT
data_i[28]	No	No		No		INPUT
data_i[32:29]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[33]	No	No		No		INPUT
data_i[34]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[36:35]	No	No		No		INPUT
data_i[40:37]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[41]	No	No		No		INPUT
data_i[47:42]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[49:48]	No	No		No		INPUT
data_i[52:50]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	INPUT
data_i[54:53]	No	No		No		INPUT
data_i[71:55]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[0]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[5:2]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[9:8]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[15:11]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[19:18]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[27:24]	Yes	Yes	T6,T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[32:29]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[34]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[36:35]	No	No		No		OUTPUT
data_o[40:37]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[47:42]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[49:48]	No	No		No		OUTPUT
data_o[52:50]	Yes	Yes	T6,T7,T26	Yes	T6,T7,T26	OUTPUT
data_o[54:53]	No	No		No		OUTPUT
data_o[63:55]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	208	76.47
Total Bits 0->1	136	104	76.47
Total Bits 1->0	136	104	76.47

Ports	2	0	0.00
Port Bits	272	208	76.47
Port Bits 0->1	136	104	76.47
Port Bits 1->0	136	104	76.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[1]	No	No		No		INPUT
data_i[7:2]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[16:13]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[17]	No	No		No		INPUT
data_i[21:18]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[22]	No	No		No		INPUT
data_i[25:23]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[36:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	INPUT
data_i[40]	No	No		No		INPUT
data_i[46:41]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[47]	No	No		No		INPUT
data_i[50:48]	Yes	Yes	*T195,*T6,*T7	Yes	T195,T6,T7	INPUT
data_i[51]	No	No		No		INPUT
data_i[54:52]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_i[55]	No	No		No		INPUT
data_i[61:56]	Yes	Yes	*T195,*T6,*T7	Yes	T195,T6,T7	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	INPUT
data_o[0]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[7:2]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[16:13]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[21:18]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[25:23]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[36:30]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T6,*T7,*T73	Yes	T6,T7,T73	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[46:41]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[50:48]	Yes	Yes	*T195,*T6,*T7	Yes	T195,T6,T7	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[54:52]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[61:56]	Yes	Yes	*T195,*T6,*T7	Yes	T195,T6,T7	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T6,T7,T73	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T48,T59,T84	Yes	T3,T48,T59	INPUT
data_o[63:0]	Yes	Yes	T48,T59,T84	Yes	T3,T48,T59	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T26,T38	Yes	T3,T7,T26	INPUT
data_o[63:0]	Yes	Yes	T7,T26,T38	Yes	T3,T7,T26	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T17,T26,T48	Yes	T3,T17,T26	INPUT
data_o[63:0]	Yes	Yes	T17,T26,T48	Yes	T3,T17,T26	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	280	272	97.14
Total Bits 0->1	140	136	97.14
Total Bits 1->0	140	136	97.14

Ports	4	2	50.00
Port Bits	280	272	97.14
Port Bits 0->1	140	136	97.14
Port Bits 1->0	140	136	97.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T26,T38	Yes	T3,T7,T26	INPUT
data_o[63:0]	Yes	Yes	T7,T26,T38	Yes	T3,T7,T26	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	No	No		No		OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T60,T97,T82	Yes	T60,T97,T82	INPUT
data_o[63:0]	Yes	Yes	T60,T97,T82	Yes	T60,T97,T82	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T102,T103,T84	Yes	T102,T103,T84	INPUT
data_o[63:0]	Yes	Yes	T102,T103,T84	Yes	T102,T103,T84	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T85,T269,T204	Yes	T85,T270,T271	INPUT
data_o[63:0]	Yes	Yes	T85,T269,T204	Yes	T85,T270,T271	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T272,T171,T273	Yes	T49,T272,T270	INPUT
data_o[63:0]	Yes	Yes	T272,T171,T273	Yes	T49,T272,T270	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T95,T99,T56	Yes	T95,T99,T56	INPUT
data_o[63:0]	Yes	Yes	T95,T99,T56	Yes	T95,T99,T56	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T90,T147,T58	Yes	T13,T90,T147	INPUT
data_o[63:0]	Yes	Yes	T90,T147,T58	Yes	T13,T90,T147	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T274,T273,T275	Yes	T274,T273,T276	INPUT
data_o[63:0]	Yes	Yes	T274,T273,T275	Yes	T274,T273,T276	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T32,T263,T277	Yes	T7,T32,T263	INPUT
data_o[63:0]	Yes	Yes	T32,T263,T277	Yes	T7,T32,T263	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T85,T91,T92	Yes	T85,T91,T92	INPUT
data_o[63:0]	Yes	Yes	T85,T91,T92	Yes	T85,T91,T92	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T73,T17,T26	Yes	T4,T73,T17	INPUT
data_o[63:0]	Yes	Yes	T73,T17,T26	Yes	T4,T73,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T17,T102	Yes	T4,T73,T17	INPUT
data_o[63:0]	Yes	Yes	T4,T17,T102	Yes	T4,T73,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T73,T17	Yes	T7,T73,T17	INPUT
data_o[63:0]	Yes	Yes	T7,T73,T17	Yes	T7,T73,T17	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T103,T84,T91	Yes	T103,T84,T91	INPUT
data_o[63:0]	Yes	Yes	T103,T84,T91	Yes	T103,T84,T91	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T27,T59	Yes	T4,T6,T101	INPUT
data_o[63:0]	Yes	Yes	T4,T27,T59	Yes	T4,T6,T101	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T102,T65,T32	Yes	T4,T102,T65	INPUT
data_o[63:0]	Yes	Yes	T102,T65,T32	Yes	T4,T102,T65	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T17,T75,T102	Yes	T17,T75,T102	INPUT
data_o[63:0]	Yes	Yes	T17,T75,T102	Yes	T17,T75,T102	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T75,T59,T84	Yes	T75,T59,T84	INPUT
data_o[63:0]	Yes	Yes	T75,T59,T84	Yes	T75,T59,T84	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T26,T38	Yes	T4,T7,T73	INPUT
data_o[63:0]	Yes	Yes	T7,T26,T38	Yes	T4,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T17,T18,T48	Yes	T6,T7,T73	INPUT
data_o[63:0]	Yes	Yes	T17,T18,T48	Yes	T6,T7,T73	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR