Module Definition
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Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 66.18 66.18
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 66.91 66.91
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 66.91 66.91
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 68.38 68.38
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 70.59 70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 73.53 73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 73.53 73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 74.26 74.26
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 85.29 85.29
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 85.29 85.29
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.18 66.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.18 66.18


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.91 66.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.91 66.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.91 66.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.91 66.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.38 68.38


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.38 68.38


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.59 70.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.53 73.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.26 74.26


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.26 74.26


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T12,T103 Yes T1,T12,T103 INPUT
data_o[63:0] Yes Yes T1,T12,T103 Yes T1,T12,T103 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T172 Yes T109,T110,T172 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T109,*T110,*T172 Yes T109,T110,T172 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 180 66.18
Total Bits 0->1 136 90 66.18
Total Bits 1->0 136 90 66.18

Ports 2 0 0.00
Port Bits 272 180 66.18
Port Bits 0->1 136 90 66.18
Port Bits 1->0 136 90 66.18

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[1] No No No INPUT
data_i[4:2] Yes Yes T4,T6,T11 Yes T4,T5,T6 INPUT
data_i[5] No No No INPUT
data_i[8:6] Yes Yes T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[9] No No No INPUT
data_i[10] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 INPUT
data_i[11] No No No INPUT
data_i[19:12] Yes Yes T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[21:20] No No No INPUT
data_i[26:22] Yes Yes T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[28:27] No No No INPUT
data_i[29] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[34:30] No No No INPUT
data_i[35] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 INPUT
data_i[36] No No No INPUT
data_i[37] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 INPUT
data_i[38] No No No INPUT
data_i[44:39] Yes Yes T4,T6,T11 Yes T4,T5,T6 INPUT
data_i[46:45] No No No INPUT
data_i[53:47] Yes Yes T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[57:54] No No No INPUT
data_i[58] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 INPUT
data_i[59] No No No INPUT
data_i[61:60] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T4,T6,T11 Yes T4,T5,T6 INPUT
data_o[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[1] No No No OUTPUT
data_o[4:2] Yes Yes T4,T6,T11 Yes T4,T5,T6 OUTPUT
data_o[5] No No No OUTPUT
data_o[8:6] Yes Yes T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[9] No No No OUTPUT
data_o[10] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 OUTPUT
data_o[11] No No No OUTPUT
data_o[19:12] Yes Yes T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[21:20] No No No OUTPUT
data_o[26:22] Yes Yes T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[28:27] No No No OUTPUT
data_o[29] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[34:30] No No No OUTPUT
data_o[35] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 OUTPUT
data_o[36] No No No OUTPUT
data_o[37] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 OUTPUT
data_o[38] No No No OUTPUT
data_o[44:39] Yes Yes T4,T6,T11 Yes T4,T5,T6 OUTPUT
data_o[46:45] No No No OUTPUT
data_o[53:47] Yes Yes T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[57:54] No No No OUTPUT
data_o[58] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 OUTPUT
data_o[59] No No No OUTPUT
data_o[61:60] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T4,T6,T11 Yes T4,T5,T6 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 182 66.91
Total Bits 0->1 136 91 66.91
Total Bits 1->0 136 91 66.91

Ports 2 0 0.00
Port Bits 272 182 66.91
Port Bits 0->1 136 91 66.91
Port Bits 1->0 136 91 66.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[6:1] Yes Yes T4,T6,T11 Yes T4,T5,T6 INPUT
data_i[7] No No No INPUT
data_i[12:8] Yes Yes T4,T6,T11 Yes T4,T5,T6 INPUT
data_i[14:13] No No No INPUT
data_i[15] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 INPUT
data_i[16] No No No INPUT
data_i[18:17] Yes Yes T6,T11,T99 Yes T5,T6,T11 INPUT
data_i[19] No No No INPUT
data_i[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[21] No No No INPUT
data_i[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[25:23] No No No INPUT
data_i[31:26] Yes Yes T6,T11,T99 Yes T5,T6,T11 INPUT
data_i[32] No No No INPUT
data_i[39:33] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[41:40] No No No INPUT
data_i[43:42] Yes Yes T6,T11,T99 Yes T5,T6,T11 INPUT
data_i[44] No No No INPUT
data_i[50:45] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[55:53] No No No INPUT
data_i[57:56] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[60:58] No No No INPUT
data_i[62:61] Yes Yes T6,T11,T99 Yes T5,T6,T11 INPUT
data_i[63] No No No INPUT
data_i[67:64] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[68] No No No INPUT
data_i[71:69] Yes Yes T5,T6,T11 Yes T5,T6,T11 INPUT
data_o[0] No No No OUTPUT
data_o[6:1] Yes Yes T4,T6,T11 Yes T4,T5,T6 OUTPUT
data_o[7] No No No OUTPUT
data_o[12:8] Yes Yes T4,T6,T11 Yes T4,T5,T6 OUTPUT
data_o[14:13] No No No OUTPUT
data_o[15] Yes Yes *T4,*T6,*T11 Yes T4,T5,T6 OUTPUT
data_o[16] No No No OUTPUT
data_o[18:17] Yes Yes T6,T11,T99 Yes T5,T6,T11 OUTPUT
data_o[19] No No No OUTPUT
data_o[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[21] No No No OUTPUT
data_o[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[25:23] No No No OUTPUT
data_o[31:26] Yes Yes T6,T11,T99 Yes T5,T6,T11 OUTPUT
data_o[32] No No No OUTPUT
data_o[39:33] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[41:40] No No No OUTPUT
data_o[43:42] Yes Yes T6,T11,T99 Yes T5,T6,T11 OUTPUT
data_o[44] No No No OUTPUT
data_o[50:45] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[55:53] No No No OUTPUT
data_o[57:56] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[60:58] No No No OUTPUT
data_o[62:61] Yes Yes T6,T11,T99 Yes T5,T6,T11 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 182 66.91
Total Bits 0->1 136 91 66.91
Total Bits 1->0 136 91 66.91

Ports 2 0 0.00
Port Bits 272 182 66.91
Port Bits 0->1 136 91 66.91
Port Bits 1->0 136 91 66.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T6,*T11,*T99 Yes T5,T6,T11 INPUT
data_i[4:2] No No No INPUT
data_i[10:5] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[12:11] No No No INPUT
data_i[16:13] Yes Yes T6,T11,T99 Yes T5,T6,T11 INPUT
data_i[18:17] No No No INPUT
data_i[20:19] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[21] No No No INPUT
data_i[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[23] No No No INPUT
data_i[25:24] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[26] No No No INPUT
data_i[31:27] Yes Yes T6,T11,T134 Yes T5,T6,T11 INPUT
data_i[32] No No No INPUT
data_i[33] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[37:34] No No No INPUT
data_i[49:38] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[51:50] No No No INPUT
data_i[52] Yes Yes *T6,*T11,*T134 Yes T5,T6,T11 INPUT
data_i[53] No No No INPUT
data_i[55:54] Yes Yes T6,T11,T134 Yes T5,T6,T11 INPUT
data_i[56] No No No INPUT
data_i[60:57] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[62:61] No No No INPUT
data_i[65:63] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[66] No No No INPUT
data_i[71:67] Yes Yes T4,T5,T11 Yes T4,T5,T11 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T6,*T11,*T99 Yes T5,T6,T11 OUTPUT
data_o[4:2] No No No OUTPUT
data_o[10:5] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[12:11] No No No OUTPUT
data_o[16:13] Yes Yes T6,T11,T99 Yes T5,T6,T11 OUTPUT
data_o[18:17] No No No OUTPUT
data_o[20:19] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[21] No No No OUTPUT
data_o[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[23] No No No OUTPUT
data_o[25:24] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[26] No No No OUTPUT
data_o[31:27] Yes Yes T6,T11,T134 Yes T5,T6,T11 OUTPUT
data_o[32] No No No OUTPUT
data_o[33] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[37:34] No No No OUTPUT
data_o[49:38] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[51:50] No No No OUTPUT
data_o[52] Yes Yes *T6,*T11,*T134 Yes T5,T6,T11 OUTPUT
data_o[53] No No No OUTPUT
data_o[55:54] Yes Yes T6,T11,T134 Yes T5,T6,T11 OUTPUT
data_o[56] No No No OUTPUT
data_o[60:57] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[62:61] No No No OUTPUT
data_o[63] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 186 68.38
Total Bits 0->1 136 93 68.38
Total Bits 1->0 136 93 68.38

Ports 2 0 0.00
Port Bits 272 186 68.38
Port Bits 0->1 136 93 68.38
Port Bits 1->0 136 93 68.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[3:1] Yes Yes T4,T5,T11 Yes T4,T5,T11 INPUT
data_i[5:4] No No No INPUT
data_i[6] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[8:7] No No No INPUT
data_i[10:9] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[11] No No No INPUT
data_i[12] Yes Yes *T4,*T5,*T11 Yes T4,T5,T11 INPUT
data_i[13] No No No INPUT
data_i[15:14] Yes Yes T4,T5,T11 Yes T4,T5,T11 INPUT
data_i[16] No No No INPUT
data_i[21:17] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[22] No No No INPUT
data_i[25:23] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[26] No No No INPUT
data_i[28:27] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[29] No No No INPUT
data_i[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[32:31] No No No INPUT
data_i[39:33] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[42] No No No INPUT
data_i[43] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[44] No No No INPUT
data_i[46:45] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[47] No No No INPUT
data_i[50:48] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[53] No No No INPUT
data_i[55:54] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[56] No No No INPUT
data_i[62:57] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[64:63] No No No INPUT
data_i[71:65] Yes Yes T4,T6,T99 Yes T4,T6,T99 INPUT
data_o[0] No No No OUTPUT
data_o[3:1] Yes Yes T4,T5,T11 Yes T4,T5,T11 OUTPUT
data_o[5:4] No No No OUTPUT
data_o[6] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[8:7] No No No OUTPUT
data_o[10:9] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[11] No No No OUTPUT
data_o[12] Yes Yes *T4,*T5,*T11 Yes T4,T5,T11 OUTPUT
data_o[13] No No No OUTPUT
data_o[15:14] Yes Yes T4,T5,T11 Yes T4,T5,T11 OUTPUT
data_o[16] No No No OUTPUT
data_o[21:17] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[22] No No No OUTPUT
data_o[25:23] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[26] No No No OUTPUT
data_o[28:27] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[29] No No No OUTPUT
data_o[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[39:33] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[42] No No No OUTPUT
data_o[43] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[44] No No No OUTPUT
data_o[46:45] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[47] No No No OUTPUT
data_o[50:48] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[53] No No No OUTPUT
data_o[55:54] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[56] No No No OUTPUT
data_o[62:57] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 192 70.59
Total Bits 0->1 136 96 70.59
Total Bits 1->0 136 96 70.59

Ports 2 0 0.00
Port Bits 272 192 70.59
Port Bits 0->1 136 96 70.59
Port Bits 1->0 136 96 70.59

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[1] Yes Yes *T5,*T11,*T99 Yes T5,T11,T99 INPUT
data_i[2] No No No INPUT
data_i[5:3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[6] No No No INPUT
data_i[7] Yes Yes *T5,*T11,*T99 Yes T5,T11,T99 INPUT
data_i[8] No No No INPUT
data_i[12:9] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[13] No No No INPUT
data_i[15:14] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[16] No No No INPUT
data_i[19:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[20] No No No INPUT
data_i[24:21] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[25] No No No INPUT
data_i[26] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[27] No No No INPUT
data_i[31:28] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[32] No No No INPUT
data_i[33] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[34] No No No INPUT
data_i[35] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[36] No No No INPUT
data_i[38:37] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[39] No No No INPUT
data_i[45:40] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[47:46] No No No INPUT
data_i[52:48] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[53] No No No INPUT
data_i[56:54] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[57] No No No INPUT
data_i[59:58] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_i[62:60] No No No INPUT
data_i[71:63] Yes Yes T5,T11,T99 Yes T5,T11,T99 INPUT
data_o[0] No No No OUTPUT
data_o[1] Yes Yes *T5,*T11,*T99 Yes T5,T11,T99 OUTPUT
data_o[2] No No No OUTPUT
data_o[5:3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[6] No No No OUTPUT
data_o[7] Yes Yes *T5,*T11,*T99 Yes T5,T11,T99 OUTPUT
data_o[8] No No No OUTPUT
data_o[12:9] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[13] No No No OUTPUT
data_o[15:14] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[16] No No No OUTPUT
data_o[19:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[20] No No No OUTPUT
data_o[24:21] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[25] No No No OUTPUT
data_o[26] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[27] No No No OUTPUT
data_o[31:28] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[32] No No No OUTPUT
data_o[33] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[34] No No No OUTPUT
data_o[35] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[36] No No No OUTPUT
data_o[38:37] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[39] No No No OUTPUT
data_o[45:40] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[47:46] No No No OUTPUT
data_o[52:48] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[53] No No No OUTPUT
data_o[56:54] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[57] No No No OUTPUT
data_o[59:58] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
data_o[62:60] No No No OUTPUT
data_o[63] Yes Yes T5,T11,T99 Yes T5,T11,T99 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 200 73.53
Total Bits 0->1 136 100 73.53
Total Bits 1->0 136 100 73.53

Ports 2 0 0.00
Port Bits 272 200 73.53
Port Bits 0->1 136 100 73.53
Port Bits 1->0 136 100 73.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[7:6] No No No INPUT
data_i[12:8] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[13] No No No INPUT
data_i[16:14] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[17] No No No INPUT
data_i[24:18] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[26:25] No No No INPUT
data_i[27] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[31] No No No INPUT
data_i[33:32] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[34] No No No INPUT
data_i[38:35] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[39] No No No INPUT
data_i[43:40] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[44] No No No INPUT
data_i[46:45] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[47] No No No INPUT
data_i[48] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[49] No No No INPUT
data_i[50] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[52:51] No No No INPUT
data_i[55:53] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[56] No No No INPUT
data_i[59:57] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[60] No No No INPUT
data_i[62:61] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_o[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[7:6] No No No OUTPUT
data_o[12:8] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[13] No No No OUTPUT
data_o[16:14] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[17] No No No OUTPUT
data_o[24:18] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[26:25] No No No OUTPUT
data_o[27] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[31] No No No OUTPUT
data_o[33:32] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[34] No No No OUTPUT
data_o[38:35] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[39] No No No OUTPUT
data_o[43:40] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[44] No No No OUTPUT
data_o[46:45] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[47] No No No OUTPUT
data_o[48] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[49] No No No OUTPUT
data_o[50] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[52:51] No No No OUTPUT
data_o[55:53] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[56] No No No OUTPUT
data_o[59:57] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[60] No No No OUTPUT
data_o[62:61] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 200 73.53
Total Bits 0->1 136 100 73.53
Total Bits 1->0 136 100 73.53

Ports 2 0 0.00
Port Bits 272 200 73.53
Port Bits 0->1 136 100 73.53
Port Bits 1->0 136 100 73.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[1] No No No INPUT
data_i[3:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[4] No No No INPUT
data_i[5] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[6] No No No INPUT
data_i[7] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[8] No No No INPUT
data_i[9] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[10] No No No INPUT
data_i[15:11] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[16] No No No INPUT
data_i[22:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[24:23] No No No INPUT
data_i[25] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[26] No No No INPUT
data_i[33:27] Yes Yes T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[35:34] No No No INPUT
data_i[43:36] Yes Yes T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[44] No No No INPUT
data_i[45] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[46] No No No INPUT
data_i[48:47] Yes Yes T4,T5,T11 Yes T4,T5,T11 INPUT
data_i[49] No No No INPUT
data_i[53:50] Yes Yes T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[55:54] No No No INPUT
data_i[59:56] Yes Yes T4,T5,T11 Yes T4,T5,T11 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T4,T5,T11 Yes T4,T5,T11 INPUT
data_o[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[1] No No No OUTPUT
data_o[3:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[4] No No No OUTPUT
data_o[5] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[6] No No No OUTPUT
data_o[7] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[8] No No No OUTPUT
data_o[9] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[10] No No No OUTPUT
data_o[15:11] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[16] No No No OUTPUT
data_o[22:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[25] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[26] No No No OUTPUT
data_o[33:27] Yes Yes T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[43:36] Yes Yes T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[44] No No No OUTPUT
data_o[45] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[46] No No No OUTPUT
data_o[48:47] Yes Yes T4,T5,T11 Yes T4,T5,T11 OUTPUT
data_o[49] No No No OUTPUT
data_o[53:50] Yes Yes T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[55:54] No No No OUTPUT
data_o[59:56] Yes Yes T4,T5,T11 Yes T4,T5,T11 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T4,T5,T11 Yes T4,T5,T11 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 202 74.26
Total Bits 0->1 136 101 74.26
Total Bits 1->0 136 101 74.26

Ports 2 0 0.00
Port Bits 272 202 74.26
Port Bits 0->1 136 101 74.26
Port Bits 1->0 136 101 74.26

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T5,T11,T133 Yes T5,T11,T133 INPUT
data_i[2] No No No INPUT
data_i[5:3] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[7:6] No No No INPUT
data_i[8] Yes Yes *T5,*T11,*T133 Yes T5,T11,T133 INPUT
data_i[9] No No No INPUT
data_i[12:10] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[13] No No No INPUT
data_i[14] Yes Yes *T5,*T11,*T133 Yes T5,T11,T133 INPUT
data_i[15] No No No INPUT
data_i[24:16] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[25] No No No INPUT
data_i[30:26] Yes Yes T5,T11,T133 Yes T5,T11,T133 INPUT
data_i[31] No No No INPUT
data_i[32] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[33] No No No INPUT
data_i[34] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[35] No No No INPUT
data_i[36] Yes Yes *T5,*T11,*T133 Yes T5,T11,T133 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[39] No No No INPUT
data_i[42:40] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[43] No No No INPUT
data_i[45:44] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[46] No No No INPUT
data_i[48:47] Yes Yes T5,T11,T133 Yes T5,T11,T133 INPUT
data_i[49] No No No INPUT
data_i[52:50] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[53] No No No INPUT
data_i[61:54] Yes Yes T5,T11,T133 Yes T5,T11,T133 INPUT
data_i[62] No No No INPUT
data_i[64:63] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[65] No No No INPUT
data_i[71:66] Yes Yes T97,T128,T19 Yes T5,T97,T128 INPUT
data_o[1:0] Yes Yes T5,T11,T133 Yes T5,T11,T133 OUTPUT
data_o[2] No No No OUTPUT
data_o[5:3] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[7:6] No No No OUTPUT
data_o[8] Yes Yes *T5,*T11,*T133 Yes T5,T11,T133 OUTPUT
data_o[9] No No No OUTPUT
data_o[12:10] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[13] No No No OUTPUT
data_o[14] Yes Yes *T5,*T11,*T133 Yes T5,T11,T133 OUTPUT
data_o[15] No No No OUTPUT
data_o[24:16] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[25] No No No OUTPUT
data_o[30:26] Yes Yes T5,T11,T133 Yes T5,T11,T133 OUTPUT
data_o[31] No No No OUTPUT
data_o[32] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[33] No No No OUTPUT
data_o[34] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[35] No No No OUTPUT
data_o[36] Yes Yes *T5,*T11,*T133 Yes T5,T11,T133 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[39] No No No OUTPUT
data_o[42:40] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[43] No No No OUTPUT
data_o[45:44] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[46] No No No OUTPUT
data_o[48:47] Yes Yes T5,T11,T133 Yes T5,T11,T133 OUTPUT
data_o[49] No No No OUTPUT
data_o[52:50] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[53] No No No OUTPUT
data_o[61:54] Yes Yes T5,T11,T133 Yes T5,T11,T133 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[6] No No No INPUT
data_i[7] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[8] No No No INPUT
data_i[10:9] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[12:11] No No No INPUT
data_i[15:13] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[16] No No No INPUT
data_i[20:17] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[21] No No No INPUT
data_i[24:22] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 INPUT
data_i[25] No No No INPUT
data_i[27:26] Yes Yes T5,T11,T133 Yes T5,T11,T133 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes T5,T11,T133 Yes T5,T11,T133 INPUT
data_i[31] No No No INPUT
data_i[33:32] Yes Yes T133,T94,*T96 Yes T133,T94,T104 INPUT
data_i[35:34] No No No INPUT
data_i[39:36] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T133,*T94,*T96 Yes T133,T94,T104 INPUT
data_i[42] No No No INPUT
data_i[43] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[44] No No No INPUT
data_i[54:45] Yes Yes *T133,*T94,*T96 Yes T133,T94,T104 INPUT
data_i[55] No No No INPUT
data_i[59:56] Yes Yes *T297,*T4,*T5 Yes T297,T4,T5 INPUT
data_i[60] No No No INPUT
data_i[71:61] Yes Yes T133,T94,T96 Yes T133,T94,T104 INPUT
data_o[5:0] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[6] No No No OUTPUT
data_o[7] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[8] No No No OUTPUT
data_o[10:9] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[12:11] No No No OUTPUT
data_o[15:13] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[16] No No No OUTPUT
data_o[20:17] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[21] No No No OUTPUT
data_o[24:22] Yes Yes *T4,T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[25] No No No OUTPUT
data_o[27:26] Yes Yes T5,T11,T133 Yes T5,T11,T133 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes T5,T11,T133 Yes T5,T11,T133 OUTPUT
data_o[31] No No No OUTPUT
data_o[33:32] Yes Yes T133,T94,*T96 Yes T133,T94,T104 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[39:36] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T133,*T94,*T96 Yes T133,T94,T104 OUTPUT
data_o[42] No No No OUTPUT
data_o[43] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[44] No No No OUTPUT
data_o[54:45] Yes Yes *T133,*T94,*T96 Yes T133,T94,T104 OUTPUT
data_o[55] No No No OUTPUT
data_o[59:56] Yes Yes *T297,*T4,*T5 Yes T297,T4,T5 OUTPUT
data_o[60] No No No OUTPUT
data_o[63:61] Yes Yes T133,T94,T96 Yes T133,T94,T104 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 232 85.29
Total Bits 0->1 136 116 85.29
Total Bits 1->0 136 116 85.29

Ports 2 0 0.00
Port Bits 272 232 85.29
Port Bits 0->1 136 116 85.29
Port Bits 1->0 136 116 85.29

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[7:6] No No No INPUT
data_i[9:8] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[11:10] No No No INPUT
data_i[17:12] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[18] No No No INPUT
data_i[20:19] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[21] No No No INPUT
data_i[24:22] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[25] No No No INPUT
data_i[41:26] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[42] No No No INPUT
data_i[52:43] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[53] No No No INPUT
data_i[62:54] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T4,T6,T11 Yes T4,T5,T6 INPUT
data_o[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[7:6] No No No OUTPUT
data_o[9:8] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[17:12] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[18] No No No OUTPUT
data_o[20:19] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[21] No No No OUTPUT
data_o[24:22] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[25] No No No OUTPUT
data_o[41:26] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[42] No No No OUTPUT
data_o[52:43] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[53] No No No OUTPUT
data_o[62:54] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 232 85.29
Total Bits 0->1 136 116 85.29
Total Bits 1->0 136 116 85.29

Ports 2 0 0.00
Port Bits 272 232 85.29
Port Bits 0->1 136 116 85.29
Port Bits 1->0 136 116 85.29

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_i[4] No No No INPUT
data_i[5] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[6] No No No INPUT
data_i[7] Yes Yes *T6,*T11,*T134 Yes T5,T6,T11 INPUT
data_i[8] No No No INPUT
data_i[11:9] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[12] No No No INPUT
data_i[13] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[14] No No No INPUT
data_i[29:15] Yes Yes *T6,*T11,*T134 Yes T5,T6,T11 INPUT
data_i[30] No No No INPUT
data_i[33:31] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
data_i[35:34] No No No INPUT
data_i[40:36] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 INPUT
data_i[42:41] No No No INPUT
data_i[71:43] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
data_o[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
data_o[4] No No No OUTPUT
data_o[5] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[6] No No No OUTPUT
data_o[7] Yes Yes *T6,*T11,*T134 Yes T5,T6,T11 OUTPUT
data_o[8] No No No OUTPUT
data_o[11:9] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[12] No No No OUTPUT
data_o[13] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[14] No No No OUTPUT
data_o[29:15] Yes Yes *T6,*T11,*T134 Yes T5,T6,T11 OUTPUT
data_o[30] No No No OUTPUT
data_o[33:31] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[40:36] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
data_o[42:41] No No No OUTPUT
data_o[63:43] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T103,T95 Yes T12,T103,T95 INPUT
data_o[63:0] Yes Yes T12,T103,T95 Yes T12,T103,T95 OUTPUT
syndrome_o[2:0] Yes Yes T110,T172,T183 Yes T110,T172,T183 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T110,*T172,*T183 Yes T110,T172,T183 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T12,T104,T96 Yes T12,T104,T96 INPUT
data_o[63:0] Yes Yes T12,T104,T96 Yes T12,T104,T96 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T191 Yes T109,T110,T191 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T110,*T191 Yes T109,T110,T191 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T18,T130 Yes T1,T18,T130 INPUT
data_o[63:0] Yes Yes T1,T18,T130 Yes T1,T18,T130 OUTPUT
syndrome_o[2:0] Yes Yes T172,T183,T191 Yes T172,T183,T191 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T172,*T183,*T191 Yes T172,T183,T191 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T97,T18 Yes T1,T97,T18 INPUT
data_o[63:0] Yes Yes T1,T97,T18 Yes T1,T97,T18 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T172 Yes T109,T110,T172 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T110,*T172 Yes T109,T110,T172 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T6,T126,T142 Yes T6,T126,T142 INPUT
data_o[63:0] Yes Yes T6,T126,T142 Yes T6,T126,T142 OUTPUT
syndrome_o[2:0] Yes Yes T109,T110,T183 Yes T109,T110,T183 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T109,*T110,*T183 Yes T109,T110,T183 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T5,T130 Yes T1,T5,T130 INPUT
data_o[63:0] Yes Yes T1,T5,T130 Yes T1,T5,T130 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T51,T235,T237 Yes T51,T235,T237 INPUT
data_o[63:0] Yes Yes T51,T235,T237 Yes T51,T235,T237 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T298,T262 Yes T95,T238,T299 INPUT
data_o[63:0] Yes Yes T95,T298,T262 Yes T95,T238,T299 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T134,T124,T125 Yes T134,T124,T125 INPUT
data_o[63:0] Yes Yes T134,T124,T125 Yes T134,T124,T125 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T18,T51,T107 Yes T18,T51,T107 INPUT
data_o[63:0] Yes Yes T18,T51,T107 Yes T18,T51,T107 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T40,T258,T260 Yes T40,T258,T300 INPUT
data_o[63:0] Yes Yes T40,T258,T260 Yes T40,T258,T300 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T11,T96 Yes T4,T11,T96 INPUT
data_o[63:0] Yes Yes T4,T11,T96 Yes T4,T11,T96 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T130,T107,T142 Yes T130,T107,T142 INPUT
data_o[63:0] Yes Yes T130,T107,T142 Yes T130,T107,T142 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T5,T134 Yes T4,T5,T134 INPUT
data_o[63:0] Yes Yes T4,T5,T134 Yes T4,T5,T134 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T40,T134,T97 Yes T40,T134,T97 INPUT
data_o[63:0] Yes Yes T40,T134,T97 Yes T40,T134,T97 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T6,T11,T12 Yes T6,T11,T12 INPUT
data_o[63:0] Yes Yes T6,T11,T12 Yes T6,T11,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T6,T12 Yes T4,T6,T12 INPUT
data_o[63:0] Yes Yes T4,T6,T12 Yes T4,T6,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T124,T51 Yes T5,T95,T124 INPUT
data_o[63:0] Yes Yes T95,T124,T51 Yes T5,T95,T124 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T124,T127,T19 Yes T124,T127,T19 INPUT
data_o[63:0] Yes Yes T124,T127,T19 Yes T124,T127,T19 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T11,T124,T266 Yes T11,T124,T266 INPUT
data_o[63:0] Yes Yes T11,T124,T266 Yes T11,T124,T266 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T124,T51,T266 Yes T124,T51,T266 INPUT
data_o[63:0] Yes Yes T124,T51,T266 Yes T124,T51,T266 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T266,T125,T301 Yes T266,T125,T301 INPUT
data_o[63:0] Yes Yes T266,T125,T301 Yes T266,T125,T301 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T11,T40,T125 Yes T11,T40,T125 INPUT
data_o[63:0] Yes Yes T11,T40,T125 Yes T11,T40,T125 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T11,T95 Yes T4,T11,T95 INPUT
data_o[63:0] Yes Yes T4,T11,T95 Yes T4,T11,T95 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T6,T266 Yes T5,T6,T231 INPUT
data_o[63:0] Yes Yes T5,T6,T266 Yes T5,T6,T231 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T18,T265,T149 Yes T18,T265,T149 INPUT
data_o[63:0] Yes Yes T18,T265,T149 Yes T18,T265,T149 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T11,T51,T266 Yes T11,T51,T266 INPUT
data_o[63:0] Yes Yes T11,T51,T266 Yes T11,T51,T266 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T11,T124,T51 Yes T11,T124,T51 INPUT
data_o[63:0] Yes Yes T11,T124,T51 Yes T11,T124,T51 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T51,T266 Yes T5,T6,T95 INPUT
data_o[63:0] Yes Yes T95,T51,T266 Yes T5,T6,T95 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%