| T1078 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.777383083 |
|
|
Feb 09 04:49:49 AM UTC 25 |
Feb 09 04:49:55 AM UTC 25 |
103427686 ps |
| T1079 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.3445760651 |
|
|
Feb 09 04:49:44 AM UTC 25 |
Feb 09 04:49:56 AM UTC 25 |
1107607428 ps |
| T1080 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.2432491792 |
|
|
Feb 09 04:49:16 AM UTC 25 |
Feb 09 04:49:56 AM UTC 25 |
3544933709 ps |
| T278 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.3318512195 |
|
|
Feb 09 04:50:05 AM UTC 25 |
Feb 09 04:50:12 AM UTC 25 |
190338868 ps |
| T1081 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.323589751 |
|
|
Feb 09 04:49:49 AM UTC 25 |
Feb 09 04:49:56 AM UTC 25 |
506078852 ps |
| T1082 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2611774147 |
|
|
Feb 09 04:49:48 AM UTC 25 |
Feb 09 04:49:57 AM UTC 25 |
1890090240 ps |
| T1083 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.983232560 |
|
|
Feb 09 04:50:05 AM UTC 25 |
Feb 09 04:50:11 AM UTC 25 |
182371275 ps |
| T1084 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2552775541 |
|
|
Feb 09 04:49:42 AM UTC 25 |
Feb 09 04:49:58 AM UTC 25 |
448313134 ps |
| T1085 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.1738845787 |
|
|
Feb 09 04:49:51 AM UTC 25 |
Feb 09 04:49:58 AM UTC 25 |
438088139 ps |
| T1086 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4176053172 |
|
|
Feb 09 04:49:54 AM UTC 25 |
Feb 09 04:49:59 AM UTC 25 |
163544768 ps |
| T1087 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3452951149 |
|
|
Feb 09 04:50:05 AM UTC 25 |
Feb 09 04:50:11 AM UTC 25 |
118023361 ps |
| T1088 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.2892994224 |
|
|
Feb 09 04:50:09 AM UTC 25 |
Feb 09 04:50:14 AM UTC 25 |
284003342 ps |
| T1089 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.2303004704 |
|
|
Feb 09 04:49:54 AM UTC 25 |
Feb 09 04:50:00 AM UTC 25 |
229959067 ps |
| T205 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2535494748 |
|
|
Feb 09 04:49:50 AM UTC 25 |
Feb 09 04:50:00 AM UTC 25 |
2032881359 ps |
| T1090 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.2345730175 |
|
|
Feb 09 04:49:54 AM UTC 25 |
Feb 09 04:50:00 AM UTC 25 |
205723958 ps |
| T1091 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3515984915 |
|
|
Feb 09 04:49:42 AM UTC 25 |
Feb 09 04:50:01 AM UTC 25 |
484759022 ps |
| T1092 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.3257207073 |
|
|
Feb 09 04:49:44 AM UTC 25 |
Feb 09 04:50:03 AM UTC 25 |
494088441 ps |
| T1093 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.453731228 |
|
|
Feb 09 04:49:40 AM UTC 25 |
Feb 09 04:50:03 AM UTC 25 |
3242974895 ps |
| T1094 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.2130696297 |
|
|
Feb 09 04:49:57 AM UTC 25 |
Feb 09 04:50:03 AM UTC 25 |
344410534 ps |
| T1095 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1950224320 |
|
|
Feb 09 04:49:57 AM UTC 25 |
Feb 09 04:50:04 AM UTC 25 |
649548456 ps |
| T1096 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.89358255 |
|
|
Feb 09 04:49:57 AM UTC 25 |
Feb 09 04:50:04 AM UTC 25 |
186686087 ps |
| T58 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1257103068 |
|
|
Feb 09 04:49:57 AM UTC 25 |
Feb 09 04:50:06 AM UTC 25 |
1491135976 ps |
| T1097 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2612333433 |
|
|
Feb 09 04:49:57 AM UTC 25 |
Feb 09 04:50:07 AM UTC 25 |
2667931278 ps |
| T1098 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1974510166 |
|
|
Feb 09 04:49:45 AM UTC 25 |
Feb 09 04:50:07 AM UTC 25 |
1085640288 ps |
| T1099 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2187060606 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:07 AM UTC 25 |
241067728 ps |
| T1100 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.4047630315 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:08 AM UTC 25 |
514420617 ps |
| T112 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3692036195 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:09 AM UTC 25 |
283713539 ps |
| T1101 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3850087725 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:09 AM UTC 25 |
563983624 ps |
| T1102 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.458186133 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:09 AM UTC 25 |
118499947 ps |
| T1103 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2393915177 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:09 AM UTC 25 |
362047839 ps |
| T1104 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3753091588 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:09 AM UTC 25 |
187740629 ps |
| T1105 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.4019007532 |
|
|
Feb 09 04:50:02 AM UTC 25 |
Feb 09 04:50:10 AM UTC 25 |
2183025945 ps |
| T1106 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2851203179 |
|
|
Feb 09 04:50:05 AM UTC 25 |
Feb 09 04:50:11 AM UTC 25 |
127483293 ps |
| T1107 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.4165784224 |
|
|
Feb 09 04:50:05 AM UTC 25 |
Feb 09 04:50:11 AM UTC 25 |
167677508 ps |
| T1108 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1220587301 |
|
|
Feb 09 04:50:09 AM UTC 25 |
Feb 09 04:50:14 AM UTC 25 |
136671567 ps |
| T1109 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.534471839 |
|
|
Feb 09 04:50:09 AM UTC 25 |
Feb 09 04:50:16 AM UTC 25 |
336248638 ps |
| T1110 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2342076495 |
|
|
Feb 09 04:50:11 AM UTC 25 |
Feb 09 04:50:16 AM UTC 25 |
177082512 ps |
| T114 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.1793120871 |
|
|
Feb 09 04:50:11 AM UTC 25 |
Feb 09 04:50:17 AM UTC 25 |
149603192 ps |
| T1111 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.1628565015 |
|
|
Feb 09 04:50:09 AM UTC 25 |
Feb 09 04:50:18 AM UTC 25 |
2066560105 ps |
| T1112 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3416273751 |
|
|
Feb 09 04:50:11 AM UTC 25 |
Feb 09 04:50:18 AM UTC 25 |
257071747 ps |
| T1113 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.2435062534 |
|
|
Feb 09 04:50:11 AM UTC 25 |
Feb 09 04:50:18 AM UTC 25 |
253236893 ps |
| T1114 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.1428593875 |
|
|
Feb 09 04:50:11 AM UTC 25 |
Feb 09 04:50:18 AM UTC 25 |
196559814 ps |
| T115 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1288852204 |
|
|
Feb 09 04:50:13 AM UTC 25 |
Feb 09 04:50:19 AM UTC 25 |
116049809 ps |
| T1115 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1084305223 |
|
|
Feb 09 04:50:13 AM UTC 25 |
Feb 09 04:50:20 AM UTC 25 |
115785342 ps |
| T1116 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.3226225944 |
|
|
Feb 09 04:50:12 AM UTC 25 |
Feb 09 04:50:20 AM UTC 25 |
113469504 ps |
| T1117 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3903581153 |
|
|
Feb 09 04:50:09 AM UTC 25 |
Feb 09 04:50:20 AM UTC 25 |
2078918265 ps |
| T1118 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.718903561 |
|
|
Feb 09 04:50:13 AM UTC 25 |
Feb 09 04:50:20 AM UTC 25 |
349142391 ps |
| T206 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1119763927 |
|
|
Feb 09 04:50:15 AM UTC 25 |
Feb 09 04:50:21 AM UTC 25 |
167419428 ps |
| T1119 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.4273090546 |
|
|
Feb 09 04:50:14 AM UTC 25 |
Feb 09 04:50:21 AM UTC 25 |
165454560 ps |
| T1120 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.468008232 |
|
|
Feb 09 04:50:16 AM UTC 25 |
Feb 09 04:50:22 AM UTC 25 |
175272187 ps |
| T1121 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1478620161 |
|
|
Feb 09 04:50:15 AM UTC 25 |
Feb 09 04:50:22 AM UTC 25 |
492034594 ps |
| T1122 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3840101331 |
|
|
Feb 09 04:50:15 AM UTC 25 |
Feb 09 04:50:22 AM UTC 25 |
190368194 ps |
| T1123 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.3601696664 |
|
|
Feb 09 04:50:19 AM UTC 25 |
Feb 09 04:50:25 AM UTC 25 |
92420008 ps |
| T1124 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.2442976383 |
|
|
Feb 09 04:50:17 AM UTC 25 |
Feb 09 04:50:25 AM UTC 25 |
153352060 ps |
| T1125 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.157955012 |
|
|
Feb 09 04:50:19 AM UTC 25 |
Feb 09 04:50:26 AM UTC 25 |
524474303 ps |
| T1126 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.90801097 |
|
|
Feb 09 04:50:19 AM UTC 25 |
Feb 09 04:50:26 AM UTC 25 |
222240139 ps |
| T1127 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3300009507 |
|
|
Feb 09 04:50:19 AM UTC 25 |
Feb 09 04:50:27 AM UTC 25 |
171790660 ps |
| T1128 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.2438148851 |
|
|
Feb 09 04:50:20 AM UTC 25 |
Feb 09 04:50:27 AM UTC 25 |
241623877 ps |
| T1129 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.21668471 |
|
|
Feb 09 04:50:19 AM UTC 25 |
Feb 09 04:50:27 AM UTC 25 |
345999260 ps |
| T1130 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.1088175558 |
|
|
Feb 09 04:50:19 AM UTC 25 |
Feb 09 04:50:27 AM UTC 25 |
2182855652 ps |
| T1131 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1248064778 |
|
|
Feb 09 04:50:22 AM UTC 25 |
Feb 09 04:50:28 AM UTC 25 |
138951858 ps |
| T1132 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.4293229424 |
|
|
Feb 09 04:50:22 AM UTC 25 |
Feb 09 04:50:28 AM UTC 25 |
230801514 ps |
| T1133 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.4258781512 |
|
|
Feb 09 04:50:22 AM UTC 25 |
Feb 09 04:50:29 AM UTC 25 |
177788952 ps |
| T1134 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1584001077 |
|
|
Feb 09 04:50:23 AM UTC 25 |
Feb 09 04:50:29 AM UTC 25 |
155837827 ps |
| T1135 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.1817329344 |
|
|
Feb 09 04:50:23 AM UTC 25 |
Feb 09 04:50:29 AM UTC 25 |
118857388 ps |
| T1136 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.197093338 |
|
|
Feb 09 04:50:22 AM UTC 25 |
Feb 09 04:50:30 AM UTC 25 |
324511618 ps |
| T1137 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1550797070 |
|
|
Feb 09 04:50:23 AM UTC 25 |
Feb 09 04:50:30 AM UTC 25 |
153680028 ps |
| T1138 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.782112313 |
|
|
Feb 09 04:50:20 AM UTC 25 |
Feb 09 04:50:32 AM UTC 25 |
2243004448 ps |
| T1139 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3694896019 |
|
|
Feb 09 04:50:27 AM UTC 25 |
Feb 09 04:50:33 AM UTC 25 |
306935092 ps |
| T1140 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.1444845634 |
|
|
Feb 09 04:50:27 AM UTC 25 |
Feb 09 04:50:34 AM UTC 25 |
1474710044 ps |
| T1141 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.4011502955 |
|
|
Feb 09 04:50:27 AM UTC 25 |
Feb 09 04:50:35 AM UTC 25 |
292681213 ps |
| T1142 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.4239495051 |
|
|
Feb 09 04:50:27 AM UTC 25 |
Feb 09 04:50:35 AM UTC 25 |
177294274 ps |
| T1143 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.2107841016 |
|
|
Feb 09 04:50:29 AM UTC 25 |
Feb 09 04:50:35 AM UTC 25 |
446576497 ps |
| T1144 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2860646846 |
|
|
Feb 09 04:50:30 AM UTC 25 |
Feb 09 04:50:36 AM UTC 25 |
210990453 ps |
| T1145 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.2821371660 |
|
|
Feb 09 04:50:29 AM UTC 25 |
Feb 09 04:50:36 AM UTC 25 |
156914235 ps |
| T1146 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.264191440 |
|
|
Feb 09 04:50:29 AM UTC 25 |
Feb 09 04:50:36 AM UTC 25 |
1568474507 ps |
| T1147 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.521900350 |
|
|
Feb 09 04:50:29 AM UTC 25 |
Feb 09 04:50:36 AM UTC 25 |
511214629 ps |
| T1148 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.1519696214 |
|
|
Feb 09 04:50:30 AM UTC 25 |
Feb 09 04:50:37 AM UTC 25 |
2359724439 ps |
| T148 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.1014687493 |
|
|
Feb 09 04:50:30 AM UTC 25 |
Feb 09 04:50:38 AM UTC 25 |
178298162 ps |
| T1149 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3785832146 |
|
|
Feb 09 04:50:32 AM UTC 25 |
Feb 09 04:50:39 AM UTC 25 |
237014497 ps |
| T1150 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.4171833492 |
|
|
Feb 09 04:50:32 AM UTC 25 |
Feb 09 04:50:40 AM UTC 25 |
276292617 ps |
| T1151 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.1730354589 |
|
|
Feb 09 04:50:30 AM UTC 25 |
Feb 09 04:50:40 AM UTC 25 |
2288454352 ps |
| T1152 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.1926920585 |
|
|
Feb 09 04:50:34 AM UTC 25 |
Feb 09 04:50:41 AM UTC 25 |
94580497 ps |
| T1153 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.1366458317 |
|
|
Feb 09 04:50:33 AM UTC 25 |
Feb 09 04:50:42 AM UTC 25 |
2674638070 ps |
| T1154 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.424306928 |
|
|
Feb 09 04:50:30 AM UTC 25 |
Feb 09 04:50:42 AM UTC 25 |
2452518707 ps |
| T1155 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2295891102 |
|
|
Feb 09 04:26:58 AM UTC 25 |
Feb 09 04:50:42 AM UTC 25 |
58984049177 ps |
| T1156 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1911381507 |
|
|
Feb 09 04:50:37 AM UTC 25 |
Feb 09 04:50:43 AM UTC 25 |
269332282 ps |
| T1157 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.3708508013 |
|
|
Feb 09 04:50:35 AM UTC 25 |
Feb 09 04:50:43 AM UTC 25 |
457110962 ps |
| T1158 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.870034186 |
|
|
Feb 09 04:50:37 AM UTC 25 |
Feb 09 04:50:44 AM UTC 25 |
114326471 ps |
| T1159 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2552394019 |
|
|
Feb 09 04:50:37 AM UTC 25 |
Feb 09 04:50:44 AM UTC 25 |
218034984 ps |
| T1160 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1825687257 |
|
|
Feb 09 04:50:38 AM UTC 25 |
Feb 09 04:50:44 AM UTC 25 |
1683641860 ps |
| T1161 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2793689525 |
|
|
Feb 09 04:50:38 AM UTC 25 |
Feb 09 04:50:45 AM UTC 25 |
119970218 ps |
| T1162 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3869171798 |
|
|
Feb 09 04:50:39 AM UTC 25 |
Feb 09 04:50:45 AM UTC 25 |
120653001 ps |
| T1163 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.1076320360 |
|
|
Feb 09 04:50:37 AM UTC 25 |
Feb 09 04:50:45 AM UTC 25 |
348809698 ps |
| T1164 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3934291557 |
|
|
Feb 09 04:50:37 AM UTC 25 |
Feb 09 04:50:45 AM UTC 25 |
2094729161 ps |
| T1165 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.480695997 |
|
|
Feb 09 04:50:37 AM UTC 25 |
Feb 09 04:50:46 AM UTC 25 |
654725408 ps |
| T1166 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.3830453637 |
|
|
Feb 09 04:50:39 AM UTC 25 |
Feb 09 04:50:47 AM UTC 25 |
181020731 ps |
| T1167 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.1977413576 |
|
|
Feb 09 04:50:42 AM UTC 25 |
Feb 09 04:50:47 AM UTC 25 |
409413856 ps |
| T1168 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.104845337 |
|
|
Feb 09 04:50:40 AM UTC 25 |
Feb 09 04:50:48 AM UTC 25 |
542587826 ps |
| T1169 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.567461569 |
|
|
Feb 09 04:50:44 AM UTC 25 |
Feb 09 04:50:49 AM UTC 25 |
124704653 ps |
| T1170 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3095887578 |
|
|
Feb 09 04:50:42 AM UTC 25 |
Feb 09 04:50:49 AM UTC 25 |
578048013 ps |
| T1171 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.2091039809 |
|
|
Feb 09 04:50:44 AM UTC 25 |
Feb 09 04:50:49 AM UTC 25 |
158696739 ps |
| T1172 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.17504710 |
|
|
Feb 09 04:50:44 AM UTC 25 |
Feb 09 04:50:50 AM UTC 25 |
182898297 ps |
| T207 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3712808546 |
|
|
Feb 09 04:50:46 AM UTC 25 |
Feb 09 04:50:51 AM UTC 25 |
232012009 ps |
| T1173 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3099021195 |
|
|
Feb 09 04:50:44 AM UTC 25 |
Feb 09 04:50:51 AM UTC 25 |
163007562 ps |
| T1174 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1489740666 |
|
|
Feb 09 04:50:44 AM UTC 25 |
Feb 09 04:50:52 AM UTC 25 |
1657970313 ps |
| T386 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3831847980 |
|
|
Feb 09 04:30:23 AM UTC 25 |
Feb 09 04:51:19 AM UTC 25 |
54701159614 ps |
| T395 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.307902325 |
|
|
Feb 09 04:37:15 AM UTC 25 |
Feb 09 04:52:24 AM UTC 25 |
91149512815 ps |
| T497 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4085045664 |
|
|
Feb 09 04:36:53 AM UTC 25 |
Feb 09 04:52:25 AM UTC 25 |
36902364219 ps |
| T1175 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2774272011 |
|
|
Feb 09 04:31:19 AM UTC 25 |
Feb 09 04:52:46 AM UTC 25 |
64650738965 ps |
| T508 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.1525020477 |
|
|
Feb 09 04:20:44 AM UTC 25 |
Feb 09 04:52:58 AM UTC 25 |
125405155174 ps |
| T1176 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.221800394 |
|
|
Feb 09 04:31:09 AM UTC 25 |
Feb 09 04:54:19 AM UTC 25 |
582349053891 ps |
| T1177 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1525582483 |
|
|
Feb 09 04:31:27 AM UTC 25 |
Feb 09 04:54:50 AM UTC 25 |
326893612298 ps |
| T1178 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2987108024 |
|
|
Feb 09 04:33:14 AM UTC 25 |
Feb 09 04:55:05 AM UTC 25 |
207395434139 ps |
| T1179 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1815118846 |
|
|
Feb 09 04:44:33 AM UTC 25 |
Feb 09 04:55:13 AM UTC 25 |
34846143518 ps |
| T341 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1031124659 |
|
|
Feb 09 04:13:19 AM UTC 25 |
Feb 09 04:55:29 AM UTC 25 |
260454384855 ps |
| T1180 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3687963709 |
|
|
Feb 09 04:41:32 AM UTC 25 |
Feb 09 04:56:25 AM UTC 25 |
56027647113 ps |
| T1181 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2070051016 |
|
|
Feb 09 04:40:18 AM UTC 25 |
Feb 09 04:56:34 AM UTC 25 |
255568331038 ps |
| T342 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.626761526 |
|
|
Feb 09 04:30:36 AM UTC 25 |
Feb 09 04:56:50 AM UTC 25 |
200413268844 ps |
| T347 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.516201353 |
|
|
Feb 09 04:19:25 AM UTC 25 |
Feb 09 04:57:23 AM UTC 25 |
1498641692895 ps |
| T154 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3899683662 |
|
|
Feb 09 04:37:55 AM UTC 25 |
Feb 09 04:58:02 AM UTC 25 |
146612895233 ps |
| T348 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3190233401 |
|
|
Feb 09 04:29:58 AM UTC 25 |
Feb 09 04:58:11 AM UTC 25 |
95954211466 ps |
| T349 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1152889154 |
|
|
Feb 09 04:37:32 AM UTC 25 |
Feb 09 04:58:35 AM UTC 25 |
69012842879 ps |
| T350 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1826785808 |
|
|
Feb 09 04:27:17 AM UTC 25 |
Feb 09 04:59:09 AM UTC 25 |
90300363940 ps |
| T351 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3001393752 |
|
|
Feb 09 04:38:09 AM UTC 25 |
Feb 09 04:59:15 AM UTC 25 |
139729374325 ps |
| T352 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.4115360884 |
|
|
Feb 09 04:30:32 AM UTC 25 |
Feb 09 05:04:59 AM UTC 25 |
80859201231 ps |
| T343 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.69444039 |
|
|
Feb 09 04:36:25 AM UTC 25 |
Feb 09 05:06:53 AM UTC 25 |
202604003649 ps |
| T353 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2822850685 |
|
|
Feb 09 04:31:59 AM UTC 25 |
Feb 09 05:07:03 AM UTC 25 |
847669631517 ps |
| T344 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.4131423082 |
|
|
Feb 09 04:26:37 AM UTC 25 |
Feb 09 05:07:20 AM UTC 25 |
450900723963 ps |
| T1182 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3720756752 |
|
|
Feb 09 04:28:41 AM UTC 25 |
Feb 09 05:08:00 AM UTC 25 |
326372645831 ps |
| T1183 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.426919371 |
|
|
Feb 09 04:44:48 AM UTC 25 |
Feb 09 05:10:55 AM UTC 25 |
87670188246 ps |
| T1184 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1755626213 |
|
|
Feb 09 04:17:28 AM UTC 25 |
Feb 09 05:14:18 AM UTC 25 |
493011207301 ps |
| T282 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3685496467 |
|
|
Feb 09 04:14:09 AM UTC 25 |
Feb 09 05:14:46 AM UTC 25 |
1136494205054 ps |
| T1185 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1243367884 |
|
|
Feb 09 04:40:44 AM UTC 25 |
Feb 09 05:15:59 AM UTC 25 |
74033932918 ps |
| T155 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2361480225 |
|
|
Feb 09 04:31:31 AM UTC 25 |
Feb 09 05:16:35 AM UTC 25 |
1214292780171 ps |
| T1186 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1189296675 |
|
|
Feb 09 04:34:33 AM UTC 25 |
Feb 09 05:17:30 AM UTC 25 |
317682133034 ps |
| T345 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3571255750 |
|
|
Feb 09 04:26:23 AM UTC 25 |
Feb 09 05:17:34 AM UTC 25 |
360859197268 ps |
| T1187 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1407630960 |
|
|
Feb 09 04:35:29 AM UTC 25 |
Feb 09 05:17:54 AM UTC 25 |
87251225156 ps |
| T297 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1453539398 |
|
|
Feb 09 04:25:59 AM UTC 25 |
Feb 09 05:20:19 AM UTC 25 |
156563712924 ps |
| T1188 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1645129350 |
|
|
Feb 09 04:39:31 AM UTC 25 |
Feb 09 05:24:30 AM UTC 25 |
111039686474 ps |
| T1189 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.3681023484 |
|
|
Feb 09 04:16:08 AM UTC 25 |
Feb 09 05:26:17 AM UTC 25 |
436977220528 ps |
| T346 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1203367881 |
|
|
Feb 09 04:32:53 AM UTC 25 |
Feb 09 05:30:21 AM UTC 25 |
2101660269108 ps |
| T354 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.77759094 |
|
|
Feb 09 04:45:09 AM UTC 25 |
Feb 09 05:32:27 AM UTC 25 |
1194047508678 ps |
| T1190 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4211570675 |
|
|
Feb 09 03:52:40 AM UTC 25 |
Feb 09 03:52:43 AM UTC 25 |
139630993 ps |
| T1191 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1532609237 |
|
|
Feb 09 03:52:40 AM UTC 25 |
Feb 09 03:52:43 AM UTC 25 |
96239135 ps |
| T1192 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1851141003 |
|
|
Feb 09 03:52:36 AM UTC 25 |
Feb 09 03:52:44 AM UTC 25 |
85226823 ps |
| T1193 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3778042900 |
|
|
Feb 09 03:52:44 AM UTC 25 |
Feb 09 03:52:47 AM UTC 25 |
36088241 ps |
| T312 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2179749933 |
|
|
Feb 09 03:52:44 AM UTC 25 |
Feb 09 03:52:48 AM UTC 25 |
53293291 ps |
| T313 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1146451742 |
|
|
Feb 09 03:52:44 AM UTC 25 |
Feb 09 03:52:49 AM UTC 25 |
103759508 ps |
| T314 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.734106972 |
|
|
Feb 09 03:52:48 AM UTC 25 |
Feb 09 03:52:53 AM UTC 25 |
69995728 ps |
| T1194 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2069978683 |
|
|
Feb 09 03:52:49 AM UTC 25 |
Feb 09 03:52:53 AM UTC 25 |
147344844 ps |
| T305 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1563701093 |
|
|
Feb 09 03:52:39 AM UTC 25 |
Feb 09 03:52:54 AM UTC 25 |
677969504 ps |
| T309 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2213655702 |
|
|
Feb 09 03:52:49 AM UTC 25 |
Feb 09 03:52:54 AM UTC 25 |
295054989 ps |
| T310 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1255076202 |
|
|
Feb 09 03:52:45 AM UTC 25 |
Feb 09 03:52:55 AM UTC 25 |
125864543 ps |
| T355 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3569300860 |
|
|
Feb 09 03:52:48 AM UTC 25 |
Feb 09 03:52:55 AM UTC 25 |
108762345 ps |
| T1195 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4268151310 |
|
|
Feb 09 03:52:51 AM UTC 25 |
Feb 09 03:52:55 AM UTC 25 |
60920960 ps |
| T1196 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4025183025 |
|
|
Feb 09 03:52:53 AM UTC 25 |
Feb 09 03:52:57 AM UTC 25 |
45041826 ps |
| T356 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3990385358 |
|
|
Feb 09 03:52:55 AM UTC 25 |
Feb 09 03:52:58 AM UTC 25 |
165025192 ps |
| T1197 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3035337271 |
|
|
Feb 09 03:52:49 AM UTC 25 |
Feb 09 03:52:58 AM UTC 25 |
153280996 ps |
| T1198 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2290677472 |
|
|
Feb 09 03:52:54 AM UTC 25 |
Feb 09 03:52:58 AM UTC 25 |
115685814 ps |
| T311 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2230849170 |
|
|
Feb 09 03:52:56 AM UTC 25 |
Feb 09 03:53:00 AM UTC 25 |
125412049 ps |
| T1199 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.501805913 |
|
|
Feb 09 03:52:56 AM UTC 25 |
Feb 09 03:53:00 AM UTC 25 |
1122681372 ps |
| T357 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4030063762 |
|
|
Feb 09 03:52:55 AM UTC 25 |
Feb 09 03:53:01 AM UTC 25 |
209076843 ps |
| T387 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1074832571 |
|
|
Feb 09 03:52:55 AM UTC 25 |
Feb 09 03:53:01 AM UTC 25 |
189474960 ps |
| T1200 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1239591618 |
|
|
Feb 09 03:52:58 AM UTC 25 |
Feb 09 03:53:01 AM UTC 25 |
70595730 ps |
| T1201 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2902439695 |
|
|
Feb 09 03:52:59 AM UTC 25 |
Feb 09 03:53:02 AM UTC 25 |
70867830 ps |
| T1202 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3817557727 |
|
|
Feb 09 03:52:56 AM UTC 25 |
Feb 09 03:53:02 AM UTC 25 |
159496273 ps |
| T362 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1251361030 |
|
|
Feb 09 03:52:59 AM UTC 25 |
Feb 09 03:53:03 AM UTC 25 |
103808164 ps |
| T1203 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3405555247 |
|
|
Feb 09 03:52:59 AM UTC 25 |
Feb 09 03:53:03 AM UTC 25 |
554789440 ps |
| T454 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1889650961 |
|
|
Feb 09 03:53:01 AM UTC 25 |
Feb 09 03:53:05 AM UTC 25 |
57290097 ps |
| T1204 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.715993489 |
|
|
Feb 09 03:53:03 AM UTC 25 |
Feb 09 03:53:07 AM UTC 25 |
36618561 ps |
| T1205 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.850801355 |
|
|
Feb 09 03:53:03 AM UTC 25 |
Feb 09 03:53:07 AM UTC 25 |
36249741 ps |
| T453 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.4128567688 |
|
|
Feb 09 03:53:02 AM UTC 25 |
Feb 09 03:53:07 AM UTC 25 |
134800748 ps |
| T371 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3442856103 |
|
|
Feb 09 03:53:02 AM UTC 25 |
Feb 09 03:53:07 AM UTC 25 |
112883820 ps |
| T1206 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.4272614552 |
|
|
Feb 09 03:53:06 AM UTC 25 |
Feb 09 03:53:09 AM UTC 25 |
71374884 ps |
| T358 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3715419005 |
|
|
Feb 09 03:53:01 AM UTC 25 |
Feb 09 03:53:09 AM UTC 25 |
1748394826 ps |
| T1207 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1816519949 |
|
|
Feb 09 03:53:01 AM UTC 25 |
Feb 09 03:53:09 AM UTC 25 |
394121323 ps |
| T372 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2279253190 |
|
|
Feb 09 03:53:08 AM UTC 25 |
Feb 09 03:53:11 AM UTC 25 |
161655003 ps |
| T1208 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2736245173 |
|
|
Feb 09 03:53:08 AM UTC 25 |
Feb 09 03:53:11 AM UTC 25 |
68642940 ps |
| T306 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3299308206 |
|
|
Feb 09 03:52:49 AM UTC 25 |
Feb 09 03:53:12 AM UTC 25 |
1957416035 ps |
| T1209 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3729889700 |
|
|
Feb 09 03:53:03 AM UTC 25 |
Feb 09 03:53:14 AM UTC 25 |
1761669779 ps |
| T307 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2306043857 |
|
|
Feb 09 03:52:58 AM UTC 25 |
Feb 09 03:53:15 AM UTC 25 |
1305882648 ps |
| T1210 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.668111220 |
|
|
Feb 09 03:53:12 AM UTC 25 |
Feb 09 03:53:15 AM UTC 25 |
77679853 ps |
| T373 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2840963785 |
|
|
Feb 09 03:53:10 AM UTC 25 |
Feb 09 03:53:15 AM UTC 25 |
94039343 ps |
| T1211 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2128046504 |
|
|
Feb 09 03:53:10 AM UTC 25 |
Feb 09 03:53:15 AM UTC 25 |
225876861 ps |
| T1212 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2849372198 |
|
|
Feb 09 03:53:13 AM UTC 25 |
Feb 09 03:53:16 AM UTC 25 |
73194062 ps |
| T1213 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3513842527 |
|
|
Feb 09 03:53:09 AM UTC 25 |
Feb 09 03:53:17 AM UTC 25 |
1936257638 ps |
| T1214 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1415047612 |
|
|
Feb 09 03:53:14 AM UTC 25 |
Feb 09 03:53:17 AM UTC 25 |
537962486 ps |
| T363 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2139212680 |
|
|
Feb 09 03:53:08 AM UTC 25 |
Feb 09 03:53:18 AM UTC 25 |
1969247763 ps |
| T1215 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.503678248 |
|
|
Feb 09 03:53:10 AM UTC 25 |
Feb 09 03:53:19 AM UTC 25 |
145443649 ps |
| T359 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1210284834 |
|
|
Feb 09 03:53:15 AM UTC 25 |
Feb 09 03:53:19 AM UTC 25 |
71752107 ps |
| T1216 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1191810881 |
|
|
Feb 09 03:53:36 AM UTC 25 |
Feb 09 03:53:43 AM UTC 25 |
158508556 ps |
| T360 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.972950091 |
|
|
Feb 09 03:53:16 AM UTC 25 |
Feb 09 03:53:20 AM UTC 25 |
172150718 ps |
| T434 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1120763568 |
|
|
Feb 09 03:53:03 AM UTC 25 |
Feb 09 03:53:21 AM UTC 25 |
627788464 ps |
| T374 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1046289036 |
|
|
Feb 09 03:53:17 AM UTC 25 |
Feb 09 03:53:21 AM UTC 25 |
273766817 ps |
| T361 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2897851438 |
|
|
Feb 09 03:53:16 AM UTC 25 |
Feb 09 03:53:23 AM UTC 25 |
156134623 ps |
| T1217 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.2706607924 |
|
|
Feb 09 03:53:20 AM UTC 25 |
Feb 09 03:53:23 AM UTC 25 |
72085410 ps |
| T364 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.187429265 |
|
|
Feb 09 03:53:20 AM UTC 25 |
Feb 09 03:53:23 AM UTC 25 |
677702269 ps |
| T1218 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1749169219 |
|
|
Feb 09 03:53:18 AM UTC 25 |
Feb 09 03:53:25 AM UTC 25 |
1121226151 ps |
| T375 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2746916964 |
|
|
Feb 09 03:53:21 AM UTC 25 |
Feb 09 03:53:25 AM UTC 25 |
67360025 ps |
| T365 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2600207970 |
|
|
Feb 09 03:53:16 AM UTC 25 |
Feb 09 03:53:26 AM UTC 25 |
129649520 ps |
| T1219 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.3808389535 |
|
|
Feb 09 03:53:24 AM UTC 25 |
Feb 09 03:53:27 AM UTC 25 |
76221516 ps |
| T366 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4092512445 |
|
|
Feb 09 03:53:24 AM UTC 25 |
Feb 09 03:53:27 AM UTC 25 |
84007121 ps |
| T1220 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1219846974 |
|
|
Feb 09 03:53:22 AM UTC 25 |
Feb 09 03:53:27 AM UTC 25 |
57890849 ps |
| T1221 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.580065506 |
|
|
Feb 09 03:53:22 AM UTC 25 |
Feb 09 03:53:27 AM UTC 25 |
1705405077 ps |
| T1222 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.356958682 |
|
|
Feb 09 03:53:18 AM UTC 25 |
Feb 09 03:53:29 AM UTC 25 |
664597668 ps |
| T1223 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2134579781 |
|
|
Feb 09 03:53:26 AM UTC 25 |
Feb 09 03:53:31 AM UTC 25 |
190288481 ps |
| T1224 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.2590990171 |
|
|
Feb 09 03:53:28 AM UTC 25 |
Feb 09 03:53:31 AM UTC 25 |
42267293 ps |
| T367 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.291093694 |
|
|
Feb 09 03:53:28 AM UTC 25 |
Feb 09 03:53:32 AM UTC 25 |
77821760 ps |
| T376 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3284095047 |
|
|
Feb 09 03:53:26 AM UTC 25 |
Feb 09 03:53:32 AM UTC 25 |
1296310724 ps |
| T1225 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2725777940 |
|
|
Feb 09 03:53:27 AM UTC 25 |
Feb 09 03:53:33 AM UTC 25 |
107334039 ps |
| T1226 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2062204255 |
|
|
Feb 09 03:53:28 AM UTC 25 |
Feb 09 03:53:34 AM UTC 25 |
157968141 ps |
| T1227 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1297999692 |
|
|
Feb 09 03:53:30 AM UTC 25 |
Feb 09 03:53:35 AM UTC 25 |
176932254 ps |
| T437 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1264494518 |
|
|
Feb 09 03:53:24 AM UTC 25 |
Feb 09 03:53:35 AM UTC 25 |
793632811 ps |
| T1228 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.412482974 |
|
|
Feb 09 03:53:33 AM UTC 25 |
Feb 09 03:53:37 AM UTC 25 |
39616285 ps |
| T368 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.525166553 |
|
|
Feb 09 03:53:33 AM UTC 25 |
Feb 09 03:53:37 AM UTC 25 |
146581677 ps |
| T1229 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3445378371 |
|
|
Feb 09 03:53:33 AM UTC 25 |
Feb 09 03:53:38 AM UTC 25 |
139393800 ps |
| T435 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.571409601 |
|
|
Feb 09 03:53:12 AM UTC 25 |
Feb 09 03:53:38 AM UTC 25 |
1921526732 ps |
| T1230 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3083152230 |
|
|
Feb 09 03:53:32 AM UTC 25 |
Feb 09 03:53:38 AM UTC 25 |
170566495 ps |
| T1231 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1095818882 |
|
|
Feb 09 03:53:35 AM UTC 25 |
Feb 09 03:53:40 AM UTC 25 |
1075703500 ps |
| T1232 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2664608695 |
|
|
Feb 09 03:53:38 AM UTC 25 |
Feb 09 03:53:41 AM UTC 25 |
544290222 ps |
| T1233 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.4281647974 |
|
|
Feb 09 03:53:38 AM UTC 25 |
Feb 09 03:53:42 AM UTC 25 |
508826667 ps |
| T1234 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3344532697 |
|
|
Feb 09 03:53:39 AM UTC 25 |
Feb 09 03:53:43 AM UTC 25 |
153538122 ps |
| T436 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3509531618 |
|
|
Feb 09 03:53:28 AM UTC 25 |
Feb 09 03:53:44 AM UTC 25 |
10357338778 ps |
| T1235 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2330283822 |
|
|
Feb 09 03:53:39 AM UTC 25 |
Feb 09 03:53:44 AM UTC 25 |
134506220 ps |
| T1236 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3916977142 |
|
|
Feb 09 03:53:42 AM UTC 25 |
Feb 09 03:53:45 AM UTC 25 |
46005315 ps |
| T369 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1636521852 |
|
|
Feb 09 03:53:42 AM UTC 25 |
Feb 09 03:53:46 AM UTC 25 |
593114261 ps |
| T432 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1190843852 |
|
|
Feb 09 03:53:32 AM UTC 25 |
Feb 09 03:53:47 AM UTC 25 |
671359047 ps |
| T1237 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3712676762 |
|
|
Feb 09 03:53:39 AM UTC 25 |
Feb 09 03:53:47 AM UTC 25 |
598157392 ps |
| T1238 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2935692377 |
|
|
Feb 09 03:53:44 AM UTC 25 |
Feb 09 03:53:49 AM UTC 25 |
128578301 ps |
| T1239 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.2795564675 |
|
|
Feb 09 03:53:46 AM UTC 25 |
Feb 09 03:53:50 AM UTC 25 |
36821104 ps |
| T1240 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2787160511 |
|
|
Feb 09 03:53:44 AM UTC 25 |
Feb 09 03:53:50 AM UTC 25 |
424571314 ps |
| T433 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1444881650 |
|
|
Feb 09 03:53:36 AM UTC 25 |
Feb 09 03:53:51 AM UTC 25 |
724097349 ps |
| T1241 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1719075985 |
|
|
Feb 09 03:53:47 AM UTC 25 |
Feb 09 03:53:52 AM UTC 25 |
93329100 ps |
| T1242 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3072730268 |
|
|
Feb 09 03:53:47 AM UTC 25 |
Feb 09 03:53:52 AM UTC 25 |
630401059 ps |
| T1243 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2669847944 |
|
|
Feb 09 03:53:48 AM UTC 25 |
Feb 09 03:53:52 AM UTC 25 |
73228936 ps |
| T1244 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3277271982 |
|
|
Feb 09 03:53:51 AM UTC 25 |
Feb 09 03:53:54 AM UTC 25 |
41955438 ps |
| T1245 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4192225275 |
|
|
Feb 09 03:53:51 AM UTC 25 |
Feb 09 03:53:55 AM UTC 25 |
45607924 ps |
| T1246 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4225921463 |
|
|
Feb 09 03:53:45 AM UTC 25 |
Feb 09 03:53:55 AM UTC 25 |
297150413 ps |
| T315 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2820661968 |
|
|
Feb 09 03:53:19 AM UTC 25 |
Feb 09 03:53:55 AM UTC 25 |
2243824916 ps |
| T1247 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2697781097 |
|
|
Feb 09 03:53:52 AM UTC 25 |
Feb 09 03:53:57 AM UTC 25 |
1015689455 ps |
| T1248 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.747455482 |
|
|
Feb 09 03:53:52 AM UTC 25 |
Feb 09 03:53:57 AM UTC 25 |
148390646 ps |
| T1249 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.12853153 |
|
|
Feb 09 03:53:50 AM UTC 25 |
Feb 09 03:53:57 AM UTC 25 |
1096674870 ps |
| T442 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4263374648 |
|
|
Feb 09 03:53:45 AM UTC 25 |
Feb 09 03:53:58 AM UTC 25 |
727323990 ps |
| T1250 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.2674841990 |
|
|
Feb 09 03:53:55 AM UTC 25 |
Feb 09 03:53:59 AM UTC 25 |
148087470 ps |
| T1251 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1534073782 |
|
|
Feb 09 03:53:55 AM UTC 25 |
Feb 09 03:53:59 AM UTC 25 |
41349456 ps |
| T1252 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.325489807 |
|
|
Feb 09 03:53:56 AM UTC 25 |
Feb 09 03:54:00 AM UTC 25 |
85421800 ps |
| T1253 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1261253236 |
|
|
Feb 09 03:53:41 AM UTC 25 |
Feb 09 03:54:00 AM UTC 25 |
752227076 ps |
| T1254 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4215431301 |
|
|
Feb 09 03:53:52 AM UTC 25 |
Feb 09 03:54:01 AM UTC 25 |
2594077724 ps |
| T1255 |
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.446724063 |
|
|
Feb 09 03:53:57 AM UTC 25 |
Feb 09 03:54:01 AM UTC 25 |
593574343 ps |