| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1952949948 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:47:50 AM UTC 24 |
228664315 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.2726230593 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:50 AM UTC 24 |
159842536 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.4051716521 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:47:50 AM UTC 24 |
1796835119 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.893474444 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:50 AM UTC 24 |
519118121 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.226731165 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
310683762 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3285221895 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
120030121 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.2009086098 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
103026951 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.3982155142 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
435185098 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2577341542 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
143138469 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.3258041658 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
145004233 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.3403183052 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
126893054 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.2438444991 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
139470788 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1996902150 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
475290698 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.1610795987 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:51 AM UTC 24 |
278176631 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.579697221 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:52 AM UTC 24 |
165574488 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.1140471276 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:47:52 AM UTC 24 |
115243335 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1359140831 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:52 AM UTC 24 |
160766832 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.4200475135 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:47:53 AM UTC 24 |
385421831 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.1643791018 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:53 AM UTC 24 |
1830481675 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3584089902 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:53 AM UTC 24 |
1055058771 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.292040748 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:53 AM UTC 24 |
986997391 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1219406820 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:54 AM UTC 24 |
298768896 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.459344638 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:47:54 AM UTC 24 |
334508162 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.3475769804 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
160024873 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.4165284993 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
102566985 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.1749003877 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
153481864 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2797434718 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
1054932306 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2117393489 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
123768880 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.3385717625 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
113367505 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1051685061 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:47:59 AM UTC 24 |
145323485 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.1335300773 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
151344882 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2300400602 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
299815660 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1419798318 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
247639408 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.1445611759 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
214735683 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.990667383 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
150822756 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.1694133495 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
128597918 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.2898025607 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
246857802 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.652801237 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
312063293 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1070751983 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
489816260 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.1173972577 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
275640973 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1510179708 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
137459641 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3590349549 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
111114165 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.565626968 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
2355773266 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2732238683 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
149533997 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.1154362666 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
1764031055 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.3635713240 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
1084099869 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2252577879 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
2810640247 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.834065199 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
689492906 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.153692295 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:00 AM UTC 24 |
1580351667 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4255180928 |
|
|
Oct 15 09:48:07 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
536744457 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.941310433 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
222720081 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.3436472469 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
136392973 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.1498091135 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
1743738032 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2158863680 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
2726664961 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.2785432827 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
333027706 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1355303606 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
496906168 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1944618184 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
2691068027 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3741731830 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
122304178 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.3366567393 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
2522385969 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3363994375 |
|
|
Oct 15 09:47:55 AM UTC 24 |
Oct 15 09:48:01 AM UTC 24 |
126696463 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1121829799 |
|
|
Oct 15 09:47:54 AM UTC 24 |
Oct 15 09:48:02 AM UTC 24 |
2727144906 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2525691406 |
|
|
Oct 15 09:47:58 AM UTC 24 |
Oct 15 09:48:02 AM UTC 24 |
143344683 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1946834455 |
|
|
Oct 15 09:47:58 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
301079261 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.259153572 |
|
|
Oct 15 09:46:07 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
14430586060 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.3763145987 |
|
|
Oct 15 09:47:59 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
490668028 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1022278585 |
|
|
Oct 15 09:47:59 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
112610918 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.3384794973 |
|
|
Oct 15 09:47:59 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
2171064910 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.1002766258 |
|
|
Oct 15 09:47:58 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
177298803 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.3258725518 |
|
|
Oct 15 09:47:58 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
167295649 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.2824451460 |
|
|
Oct 15 09:47:58 AM UTC 24 |
Oct 15 09:48:03 AM UTC 24 |
323123422 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3003645075 |
|
|
Oct 15 09:45:03 AM UTC 24 |
Oct 15 09:48:04 AM UTC 24 |
27745128428 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.838203123 |
|
|
Oct 15 09:47:18 AM UTC 24 |
Oct 15 09:48:05 AM UTC 24 |
15869337094 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.567825567 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:48:05 AM UTC 24 |
1050098505 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3475103200 |
|
|
Oct 15 09:47:46 AM UTC 24 |
Oct 15 09:48:06 AM UTC 24 |
1477208181 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.2149318784 |
|
|
Oct 15 09:47:59 AM UTC 24 |
Oct 15 09:48:06 AM UTC 24 |
2136757313 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1721912693 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
103441807 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.894249382 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
121190360 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.720383241 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
287579734 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1288800468 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
104598885 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1955299688 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
87074378 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.3123511763 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
98162701 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.614874181 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
126294625 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1191575840 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
270112987 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2386242911 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:10 AM UTC 24 |
554899803 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3986742304 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
244975073 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.1051305012 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
153462101 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.1568796759 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
104491950 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.37663933 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
1832910890 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.844257933 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
107390301 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.518794166 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
270277529 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.849521097 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
1659070942 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.805084622 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
215485456 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2229983047 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
345015499 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.665308323 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
182863464 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3423192621 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
299379482 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2750725450 |
|
|
Oct 15 09:48:07 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
146694597 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.585586069 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
568452845 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3477832644 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:11 AM UTC 24 |
315394114 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1256326629 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
426868326 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3382153314 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
169527052 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3354181048 |
|
|
Oct 15 09:48:07 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
213909235 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.4212704523 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
1750955793 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.2581116086 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
134934284 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1337797871 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:12 AM UTC 24 |
2127305098 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3375464053 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:13 AM UTC 24 |
2421691283 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.1945428590 |
|
|
Oct 15 09:48:06 AM UTC 24 |
Oct 15 09:48:13 AM UTC 24 |
1999090775 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1700111458 |
|
|
Oct 15 09:47:45 AM UTC 24 |
Oct 15 09:48:13 AM UTC 24 |
17014175922 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.731200217 |
|
|
Oct 15 09:48:07 AM UTC 24 |
Oct 15 09:48:15 AM UTC 24 |
3057532223 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.3342243766 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:21 AM UTC 24 |
271442690 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3322857835 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:21 AM UTC 24 |
357848138 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3443667526 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:21 AM UTC 24 |
167978264 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.745954111 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
231236777 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.111470581 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
111347858 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.572682088 |
|
|
Oct 15 09:48:16 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
258744588 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3844789729 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
150661451 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1127029702 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
180682113 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.2352189840 |
|
|
Oct 15 09:48:16 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
264016784 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.317361308 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
179557595 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.4026153985 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
154414977 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1115978845 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
1329164552 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.492156468 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
158266561 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2651246405 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:22 AM UTC 24 |
244099827 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3059102057 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:23 AM UTC 24 |
530320488 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.1700531923 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:23 AM UTC 24 |
2614792065 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.758394424 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:23 AM UTC 24 |
224841753 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.1239830912 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:24 AM UTC 24 |
1833019950 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2131405867 |
|
|
Oct 15 09:48:17 AM UTC 24 |
Oct 15 09:48:24 AM UTC 24 |
1480498591 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.3528594797 |
|
|
Oct 15 09:44:13 AM UTC 24 |
Oct 15 09:48:25 AM UTC 24 |
47715193862 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.1603750006 |
|
|
Oct 15 09:44:30 AM UTC 24 |
Oct 15 09:48:31 AM UTC 24 |
31694623654 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.756454091 |
|
|
Oct 15 09:46:12 AM UTC 24 |
Oct 15 09:48:36 AM UTC 24 |
18595347167 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2476239546 |
|
|
Oct 15 09:46:28 AM UTC 24 |
Oct 15 09:48:40 AM UTC 24 |
24183324928 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1147857918 |
|
|
Oct 15 09:44:30 AM UTC 24 |
Oct 15 09:48:50 AM UTC 24 |
48339649004 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1972050540 |
|
|
Oct 15 09:46:20 AM UTC 24 |
Oct 15 09:48:59 AM UTC 24 |
58867247702 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.433910652 |
|
|
Oct 15 09:44:07 AM UTC 24 |
Oct 15 09:53:26 AM UTC 24 |
64446567999 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1666684339 |
|
|
Oct 15 09:36:09 AM UTC 24 |
Oct 15 09:36:12 AM UTC 24 |
37564638 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1871144896 |
|
|
Oct 15 09:36:07 AM UTC 24 |
Oct 15 09:36:13 AM UTC 24 |
121195986 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1504032223 |
|
|
Oct 15 09:36:09 AM UTC 24 |
Oct 15 09:36:13 AM UTC 24 |
538318496 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1475865033 |
|
|
Oct 15 09:36:12 AM UTC 24 |
Oct 15 09:36:15 AM UTC 24 |
72546477 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.4289243527 |
|
|
Oct 15 09:36:13 AM UTC 24 |
Oct 15 09:36:17 AM UTC 24 |
74711967 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.735827989 |
|
|
Oct 15 09:36:14 AM UTC 24 |
Oct 15 09:36:18 AM UTC 24 |
667208563 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3748201779 |
|
|
Oct 15 09:36:15 AM UTC 24 |
Oct 15 09:36:20 AM UTC 24 |
90046221 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2418310088 |
|
|
Oct 15 09:36:14 AM UTC 24 |
Oct 15 09:36:22 AM UTC 24 |
1197048484 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1528343334 |
|
|
Oct 15 09:36:17 AM UTC 24 |
Oct 15 09:36:22 AM UTC 24 |
87330015 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.759563799 |
|
|
Oct 15 09:36:18 AM UTC 24 |
Oct 15 09:36:22 AM UTC 24 |
77954439 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.54017636 |
|
|
Oct 15 09:36:17 AM UTC 24 |
Oct 15 09:36:23 AM UTC 24 |
1668295135 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3854773171 |
|
|
Oct 15 09:36:20 AM UTC 24 |
Oct 15 09:36:24 AM UTC 24 |
544670783 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.559311396 |
|
|
Oct 15 09:36:14 AM UTC 24 |
Oct 15 09:36:25 AM UTC 24 |
837851855 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4159608356 |
|
|
Oct 15 09:36:22 AM UTC 24 |
Oct 15 09:36:25 AM UTC 24 |
42337304 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2174843264 |
|
|
Oct 15 09:36:22 AM UTC 24 |
Oct 15 09:36:26 AM UTC 24 |
249948109 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3511628473 |
|
|
Oct 15 09:36:23 AM UTC 24 |
Oct 15 09:36:26 AM UTC 24 |
189489451 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1162816078 |
|
|
Oct 15 09:36:23 AM UTC 24 |
Oct 15 09:36:26 AM UTC 24 |
129367839 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.893957922 |
|
|
Oct 15 09:36:23 AM UTC 24 |
Oct 15 09:36:28 AM UTC 24 |
95013508 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2606831755 |
|
|
Oct 15 09:36:26 AM UTC 24 |
Oct 15 09:36:29 AM UTC 24 |
104559955 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.111620008 |
|
|
Oct 15 09:36:23 AM UTC 24 |
Oct 15 09:36:29 AM UTC 24 |
166685736 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.829907180 |
|
|
Oct 15 09:36:26 AM UTC 24 |
Oct 15 09:36:29 AM UTC 24 |
41178124 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1496153695 |
|
|
Oct 15 09:36:26 AM UTC 24 |
Oct 15 09:36:29 AM UTC 24 |
72259663 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3863620778 |
|
|
Oct 15 09:36:27 AM UTC 24 |
Oct 15 09:36:30 AM UTC 24 |
75299906 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.460232485 |
|
|
Oct 15 09:36:24 AM UTC 24 |
Oct 15 09:36:30 AM UTC 24 |
998895991 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.351234765 |
|
|
Oct 15 09:36:18 AM UTC 24 |
Oct 15 09:36:31 AM UTC 24 |
2008004290 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.908996029 |
|
|
Oct 15 09:36:27 AM UTC 24 |
Oct 15 09:36:31 AM UTC 24 |
195723189 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.401854841 |
|
|
Oct 15 09:36:25 AM UTC 24 |
Oct 15 09:36:34 AM UTC 24 |
2632296309 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2652075337 |
|
|
Oct 15 09:36:31 AM UTC 24 |
Oct 15 09:36:34 AM UTC 24 |
38601942 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.4201960459 |
|
|
Oct 15 09:36:30 AM UTC 24 |
Oct 15 09:36:35 AM UTC 24 |
198154979 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2870997717 |
|
|
Oct 15 09:36:08 AM UTC 24 |
Oct 15 09:36:35 AM UTC 24 |
20068072503 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.313566244 |
|
|
Oct 15 09:36:31 AM UTC 24 |
Oct 15 09:36:35 AM UTC 24 |
591894645 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2882912361 |
|
|
Oct 15 09:36:32 AM UTC 24 |
Oct 15 09:36:35 AM UTC 24 |
38229385 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2162473677 |
|
|
Oct 15 09:36:32 AM UTC 24 |
Oct 15 09:36:36 AM UTC 24 |
143378851 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2784572668 |
|
|
Oct 15 09:36:30 AM UTC 24 |
Oct 15 09:36:36 AM UTC 24 |
105013626 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3484819296 |
|
|
Oct 15 09:36:32 AM UTC 24 |
Oct 15 09:36:36 AM UTC 24 |
101716946 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.695483181 |
|
|
Oct 15 09:36:30 AM UTC 24 |
Oct 15 09:36:38 AM UTC 24 |
138029517 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1400596465 |
|
|
Oct 15 09:36:28 AM UTC 24 |
Oct 15 09:36:39 AM UTC 24 |
1220628469 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2652606927 |
|
|
Oct 15 09:36:36 AM UTC 24 |
Oct 15 09:36:40 AM UTC 24 |
43203435 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3204851482 |
|
|
Oct 15 09:36:25 AM UTC 24 |
Oct 15 09:36:40 AM UTC 24 |
897801666 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2073865248 |
|
|
Oct 15 09:36:36 AM UTC 24 |
Oct 15 09:36:41 AM UTC 24 |
90655099 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2106267419 |
|
|
Oct 15 09:36:37 AM UTC 24 |
Oct 15 09:36:41 AM UTC 24 |
72073638 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1081321020 |
|
|
Oct 15 09:36:35 AM UTC 24 |
Oct 15 09:36:41 AM UTC 24 |
126419104 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3157956024 |
|
|
Oct 15 09:36:37 AM UTC 24 |
Oct 15 09:36:41 AM UTC 24 |
41759712 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3498924481 |
|
|
Oct 15 09:36:35 AM UTC 24 |
Oct 15 09:36:41 AM UTC 24 |
1282592882 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2353359540 |
|
|
Oct 15 09:36:27 AM UTC 24 |
Oct 15 09:36:42 AM UTC 24 |
485268331 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4126177702 |
|
|
Oct 15 09:36:34 AM UTC 24 |
Oct 15 09:36:42 AM UTC 24 |
608059601 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2337213745 |
|
|
Oct 15 09:36:40 AM UTC 24 |
Oct 15 09:36:43 AM UTC 24 |
50562196 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3215071135 |
|
|
Oct 15 09:36:36 AM UTC 24 |
Oct 15 09:36:44 AM UTC 24 |
288370513 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.1190197467 |
|
|
Oct 15 09:36:42 AM UTC 24 |
Oct 15 09:36:45 AM UTC 24 |
69628453 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1081617973 |
|
|
Oct 15 09:36:40 AM UTC 24 |
Oct 15 09:36:45 AM UTC 24 |
1623856220 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3825610018 |
|
|
Oct 15 09:36:42 AM UTC 24 |
Oct 15 09:36:46 AM UTC 24 |
86240348 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3203411382 |
|
|
Oct 15 09:36:43 AM UTC 24 |
Oct 15 09:36:46 AM UTC 24 |
42182644 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.833954433 |
|
|
Oct 15 09:36:42 AM UTC 24 |
Oct 15 09:36:47 AM UTC 24 |
267547338 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.733917181 |
|
|
Oct 15 09:36:43 AM UTC 24 |
Oct 15 09:36:47 AM UTC 24 |
96183841 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3311507554 |
|
|
Oct 15 09:36:44 AM UTC 24 |
Oct 15 09:36:48 AM UTC 24 |
100935734 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3060150432 |
|
|
Oct 15 09:36:42 AM UTC 24 |
Oct 15 09:36:49 AM UTC 24 |
99382761 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1546042317 |
|
|
Oct 15 09:36:46 AM UTC 24 |
Oct 15 09:36:49 AM UTC 24 |
100076499 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1939421868 |
|
|
Oct 15 09:36:42 AM UTC 24 |
Oct 15 09:36:49 AM UTC 24 |
163978889 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2750452413 |
|
|
Oct 15 09:36:46 AM UTC 24 |
Oct 15 09:36:50 AM UTC 24 |
140200309 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2066516651 |
|
|
Oct 15 09:36:41 AM UTC 24 |
Oct 15 09:36:51 AM UTC 24 |
4131753869 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.595004095 |
|
|
Oct 15 09:36:45 AM UTC 24 |
Oct 15 09:36:51 AM UTC 24 |
67627851 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2144430404 |
|
|
Oct 15 09:36:48 AM UTC 24 |
Oct 15 09:36:52 AM UTC 24 |
131194641 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1879301144 |
|
|
Oct 15 09:36:49 AM UTC 24 |
Oct 15 09:36:52 AM UTC 24 |
138304023 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3681955507 |
|
|
Oct 15 09:36:47 AM UTC 24 |
Oct 15 09:36:52 AM UTC 24 |
120822391 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3443642866 |
|
|
Oct 15 09:36:50 AM UTC 24 |
Oct 15 09:36:53 AM UTC 24 |
86512204 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.941903343 |
|
|
Oct 15 09:36:50 AM UTC 24 |
Oct 15 09:36:54 AM UTC 24 |
158061811 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3470639497 |
|
|
Oct 15 09:36:50 AM UTC 24 |
Oct 15 09:36:55 AM UTC 24 |
112843668 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1296058861 |
|
|
Oct 15 09:36:52 AM UTC 24 |
Oct 15 09:36:56 AM UTC 24 |
542127058 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1867210667 |
|
|
Oct 15 09:36:52 AM UTC 24 |
Oct 15 09:36:56 AM UTC 24 |
139011132 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3429950280 |
|
|
Oct 15 09:36:52 AM UTC 24 |
Oct 15 09:36:56 AM UTC 24 |
102205698 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4048062283 |
|
|
Oct 15 09:36:30 AM UTC 24 |
Oct 15 09:36:56 AM UTC 24 |
3963223035 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.538704999 |
|
|
Oct 15 09:36:48 AM UTC 24 |
Oct 15 09:36:58 AM UTC 24 |
183247869 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.760308853 |
|
|
Oct 15 09:36:53 AM UTC 24 |
Oct 15 09:36:59 AM UTC 24 |
114731864 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.2756932757 |
|
|
Oct 15 09:36:56 AM UTC 24 |
Oct 15 09:37:00 AM UTC 24 |
39498448 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2856020431 |
|
|
Oct 15 09:36:56 AM UTC 24 |
Oct 15 09:37:00 AM UTC 24 |
59393630 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3776033892 |
|
|
Oct 15 09:36:54 AM UTC 24 |
Oct 15 09:37:00 AM UTC 24 |
1169990911 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3234114586 |
|
|
Oct 15 09:36:49 AM UTC 24 |
Oct 15 09:37:00 AM UTC 24 |
666895324 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.789898679 |
|
|
Oct 15 09:36:56 AM UTC 24 |
Oct 15 09:37:01 AM UTC 24 |
47016594 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.999633254 |
|
|
Oct 15 09:36:51 AM UTC 24 |
Oct 15 09:37:01 AM UTC 24 |
3120669550 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.182537332 |
|
|
Oct 15 09:36:56 AM UTC 24 |
Oct 15 09:37:02 AM UTC 24 |
206672737 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.2776762212 |
|
|
Oct 15 09:36:59 AM UTC 24 |
Oct 15 09:37:02 AM UTC 24 |
43021062 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1051304133 |
|
|
Oct 15 09:36:57 AM UTC 24 |
Oct 15 09:37:03 AM UTC 24 |
102943313 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.859987154 |
|
|
Oct 15 09:37:00 AM UTC 24 |
Oct 15 09:37:04 AM UTC 24 |
598624857 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.4184002691 |
|
|
Oct 15 09:37:02 AM UTC 24 |
Oct 15 09:37:05 AM UTC 24 |
40176804 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1128021325 |
|
|
Oct 15 09:37:02 AM UTC 24 |
Oct 15 09:37:05 AM UTC 24 |
56447149 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3577903046 |
|
|
Oct 15 09:36:52 AM UTC 24 |
Oct 15 09:37:05 AM UTC 24 |
1448512093 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4224601325 |
|
|
Oct 15 09:36:42 AM UTC 24 |
Oct 15 09:37:06 AM UTC 24 |
4758802851 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3522286503 |
|
|
Oct 15 09:37:01 AM UTC 24 |
Oct 15 09:37:07 AM UTC 24 |
109103112 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.491887361 |
|
|
Oct 15 09:37:03 AM UTC 24 |
Oct 15 09:37:07 AM UTC 24 |
160324267 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2793981146 |
|
|
Oct 15 09:37:28 AM UTC 24 |
Oct 15 09:37:31 AM UTC 24 |
134684024 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3497748088 |
|
|
Oct 15 09:37:28 AM UTC 24 |
Oct 15 09:37:31 AM UTC 24 |
68585768 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1419300871 |
|
|
Oct 15 09:36:36 AM UTC 24 |
Oct 15 09:37:07 AM UTC 24 |
4979661111 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2317524691 |
|
|
Oct 15 09:37:02 AM UTC 24 |
Oct 15 09:37:08 AM UTC 24 |
98935447 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.947891257 |
|
|
Oct 15 09:37:05 AM UTC 24 |
Oct 15 09:37:09 AM UTC 24 |
44936072 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3138441262 |
|
|
Oct 15 09:37:05 AM UTC 24 |
Oct 15 09:37:09 AM UTC 24 |
621921828 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2026691341 |
|
|
Oct 15 09:36:55 AM UTC 24 |
Oct 15 09:37:10 AM UTC 24 |
703954970 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1831625205 |
|
|
Oct 15 09:37:05 AM UTC 24 |
Oct 15 09:37:10 AM UTC 24 |
99907322 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3844008071 |
|
|
Oct 15 09:37:01 AM UTC 24 |
Oct 15 09:37:10 AM UTC 24 |
1263680682 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.735689799 |
|
|
Oct 15 09:37:01 AM UTC 24 |
Oct 15 09:37:10 AM UTC 24 |
272261170 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.445197714 |
|
|
Oct 15 09:36:45 AM UTC 24 |
Oct 15 09:37:11 AM UTC 24 |
9661259277 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1905194941 |
|
|
Oct 15 09:37:08 AM UTC 24 |
Oct 15 09:37:11 AM UTC 24 |
37703638 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2947557621 |
|
|
Oct 15 09:37:08 AM UTC 24 |
Oct 15 09:37:11 AM UTC 24 |
44774111 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3554314739 |
|
|
Oct 15 09:37:03 AM UTC 24 |
Oct 15 09:37:11 AM UTC 24 |
172153106 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2786633199 |
|
|
Oct 15 09:37:07 AM UTC 24 |
Oct 15 09:37:12 AM UTC 24 |
193073356 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3098784765 |
|
|
Oct 15 09:37:09 AM UTC 24 |
Oct 15 09:37:12 AM UTC 24 |
66694563 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.39254591 |
|
|
Oct 15 09:37:09 AM UTC 24 |
Oct 15 09:37:13 AM UTC 24 |
98977426 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.66967810 |
|
|
Oct 15 09:37:10 AM UTC 24 |
Oct 15 09:37:13 AM UTC 24 |
101195524 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2466191842 |
|
|
Oct 15 09:37:10 AM UTC 24 |
Oct 15 09:37:14 AM UTC 24 |
149554966 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1500178152 |
|
|
Oct 15 09:37:11 AM UTC 24 |
Oct 15 09:37:14 AM UTC 24 |
73467420 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.561126301 |
|
|
Oct 15 09:37:10 AM UTC 24 |
Oct 15 09:37:15 AM UTC 24 |
1153642625 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2611284198 |
|
|
Oct 15 09:37:13 AM UTC 24 |
Oct 15 09:37:16 AM UTC 24 |
36408106 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3689061099 |
|
|
Oct 15 09:37:07 AM UTC 24 |
Oct 15 09:37:16 AM UTC 24 |
167603017 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2041249418 |
|
|
Oct 15 09:37:13 AM UTC 24 |
Oct 15 09:37:16 AM UTC 24 |
79551892 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1985581321 |
|
|
Oct 15 09:37:11 AM UTC 24 |
Oct 15 09:37:17 AM UTC 24 |
1582994946 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.128565666 |
|
|
Oct 15 09:37:11 AM UTC 24 |
Oct 15 09:37:17 AM UTC 24 |
271031260 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.226937608 |
|
|
Oct 15 09:37:13 AM UTC 24 |
Oct 15 09:37:17 AM UTC 24 |
302791818 ps |