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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.89 93.81 96.15 95.69 91.89 97.10 96.34 93.28


Total test records in report: 1318
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1256 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3541049533 Feb 09 03:53:56 AM UTC 25 Feb 09 03:54:02 AM UTC 25 114128173 ps
T370 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3198527519 Feb 09 03:53:59 AM UTC 25 Feb 09 03:54:03 AM UTC 25 57928504 ps
T1257 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4062902864 Feb 09 03:54:00 AM UTC 25 Feb 09 03:54:03 AM UTC 25 171289576 ps
T1258 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1420565498 Feb 09 03:53:57 AM UTC 25 Feb 09 03:54:04 AM UTC 25 1481746688 ps
T1259 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1545411968 Feb 09 03:54:00 AM UTC 25 Feb 09 03:54:05 AM UTC 25 101521598 ps
T1260 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.833156297 Feb 09 03:54:02 AM UTC 25 Feb 09 03:54:05 AM UTC 25 38543467 ps
T1261 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.419582899 Feb 09 03:54:02 AM UTC 25 Feb 09 03:54:06 AM UTC 25 563504782 ps
T1262 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.364028173 Feb 09 03:54:01 AM UTC 25 Feb 09 03:54:06 AM UTC 25 157251789 ps
T1263 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3748413334 Feb 09 03:54:03 AM UTC 25 Feb 09 03:54:07 AM UTC 25 1251635524 ps
T1264 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4189903515 Feb 09 03:54:04 AM UTC 25 Feb 09 03:54:09 AM UTC 25 104123980 ps
T1265 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.117123234 Feb 09 03:54:05 AM UTC 25 Feb 09 03:54:09 AM UTC 25 630113754 ps
T1266 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3471694487 Feb 09 03:54:06 AM UTC 25 Feb 09 03:54:10 AM UTC 25 53057870 ps
T1267 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.549741156 Feb 09 03:54:04 AM UTC 25 Feb 09 03:54:11 AM UTC 25 882309312 ps
T1268 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3885250975 Feb 09 03:54:07 AM UTC 25 Feb 09 03:54:13 AM UTC 25 112010460 ps
T1269 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3903382276 Feb 09 03:54:07 AM UTC 25 Feb 09 03:54:13 AM UTC 25 1032627813 ps
T1270 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1513433100 Feb 09 03:54:10 AM UTC 25 Feb 09 03:54:14 AM UTC 25 115637871 ps
T1271 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.732789481 Feb 09 03:54:10 AM UTC 25 Feb 09 03:54:14 AM UTC 25 83588015 ps
T1272 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1872840269 Feb 09 03:54:08 AM UTC 25 Feb 09 03:54:14 AM UTC 25 82686012 ps
T438 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4119524843 Feb 09 03:53:53 AM UTC 25 Feb 09 03:54:16 AM UTC 25 1312120796 ps
T1273 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.623920543 Feb 09 03:54:11 AM UTC 25 Feb 09 03:54:16 AM UTC 25 72186597 ps
T1274 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3873105023 Feb 09 03:54:02 AM UTC 25 Feb 09 03:54:18 AM UTC 25 622054093 ps
T1275 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.757043490 Feb 09 03:54:15 AM UTC 25 Feb 09 03:54:18 AM UTC 25 80604089 ps
T439 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3891494869 Feb 09 03:53:50 AM UTC 25 Feb 09 03:54:18 AM UTC 25 1199769675 ps
T1276 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2475395380 Feb 09 03:54:05 AM UTC 25 Feb 09 03:54:19 AM UTC 25 1663520539 ps
T1277 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.495154198 Feb 09 03:54:15 AM UTC 25 Feb 09 03:54:19 AM UTC 25 550595096 ps
T1278 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.841434136 Feb 09 03:54:14 AM UTC 25 Feb 09 03:54:20 AM UTC 25 390621158 ps
T1279 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.476224606 Feb 09 03:54:17 AM UTC 25 Feb 09 03:54:21 AM UTC 25 59946462 ps
T1280 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2166682976 Feb 09 03:54:15 AM UTC 25 Feb 09 03:54:22 AM UTC 25 131488292 ps
T1281 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1731490123 Feb 09 03:54:19 AM UTC 25 Feb 09 03:54:22 AM UTC 25 36315109 ps
T444 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3091693019 Feb 09 03:53:57 AM UTC 25 Feb 09 03:54:22 AM UTC 25 2584819974 ps
T1282 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2068201461 Feb 09 03:54:17 AM UTC 25 Feb 09 03:54:23 AM UTC 25 321805237 ps
T1283 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.265158479 Feb 09 03:54:20 AM UTC 25 Feb 09 03:54:23 AM UTC 25 80735686 ps
T1284 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2633616265 Feb 09 03:54:19 AM UTC 25 Feb 09 03:54:24 AM UTC 25 82781530 ps
T1285 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.940844914 Feb 09 03:54:21 AM UTC 25 Feb 09 03:54:24 AM UTC 25 42005282 ps
T1286 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3488594594 Feb 09 03:54:22 AM UTC 25 Feb 09 03:54:25 AM UTC 25 149721040 ps
T1287 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3300219334 Feb 09 03:54:21 AM UTC 25 Feb 09 03:54:26 AM UTC 25 1104516843 ps
T1288 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3655755188 Feb 09 03:54:23 AM UTC 25 Feb 09 03:54:27 AM UTC 25 142207672 ps
T1289 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3654621106 Feb 09 03:54:23 AM UTC 25 Feb 09 03:54:27 AM UTC 25 53562631 ps
T1290 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.3368840069 Feb 09 03:54:23 AM UTC 25 Feb 09 03:54:27 AM UTC 25 139875845 ps
T1291 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1866212786 Feb 09 03:54:24 AM UTC 25 Feb 09 03:54:27 AM UTC 25 152460569 ps
T1292 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2210083633 Feb 09 03:54:25 AM UTC 25 Feb 09 03:54:28 AM UTC 25 42670785 ps
T1293 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.862658299 Feb 09 03:54:20 AM UTC 25 Feb 09 03:54:28 AM UTC 25 1276032546 ps
T1294 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1464445980 Feb 09 03:54:25 AM UTC 25 Feb 09 03:54:29 AM UTC 25 45475715 ps
T1295 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.120668044 Feb 09 03:54:09 AM UTC 25 Feb 09 03:54:29 AM UTC 25 1278111305 ps
T1296 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.1226457745 Feb 09 03:54:30 AM UTC 25 Feb 09 03:54:32 AM UTC 25 44194970 ps
T1297 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2034349509 Feb 09 03:54:26 AM UTC 25 Feb 09 03:54:30 AM UTC 25 62173059 ps
T1298 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1216702483 Feb 09 03:54:28 AM UTC 25 Feb 09 03:54:30 AM UTC 25 37811467 ps
T1299 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.3874917429 Feb 09 03:54:28 AM UTC 25 Feb 09 03:54:31 AM UTC 25 38724397 ps
T1300 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.326987264 Feb 09 03:54:28 AM UTC 25 Feb 09 03:54:31 AM UTC 25 71399935 ps
T1301 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2599450847 Feb 09 03:54:28 AM UTC 25 Feb 09 03:54:31 AM UTC 25 70822944 ps
T1302 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.848346243 Feb 09 03:54:29 AM UTC 25 Feb 09 03:54:32 AM UTC 25 72681876 ps
T1303 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.195902679 Feb 09 03:54:30 AM UTC 25 Feb 09 03:54:33 AM UTC 25 92036182 ps
T1304 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2190704558 Feb 09 03:54:30 AM UTC 25 Feb 09 03:54:33 AM UTC 25 75193989 ps
T1305 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1994368864 Feb 09 03:54:31 AM UTC 25 Feb 09 03:54:34 AM UTC 25 93086551 ps
T1306 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2609084348 Feb 09 03:54:29 AM UTC 25 Feb 09 03:54:34 AM UTC 25 542810401 ps
T1307 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1394292960 Feb 09 03:54:31 AM UTC 25 Feb 09 03:54:34 AM UTC 25 52738145 ps
T1308 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3448091772 Feb 09 03:54:31 AM UTC 25 Feb 09 03:54:34 AM UTC 25 42292579 ps
T1309 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1480757218 Feb 09 03:54:32 AM UTC 25 Feb 09 03:54:35 AM UTC 25 87307251 ps
T1310 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.242453702 Feb 09 03:54:32 AM UTC 25 Feb 09 03:54:36 AM UTC 25 545720090 ps
T1311 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.180139293 Feb 09 03:54:33 AM UTC 25 Feb 09 03:54:36 AM UTC 25 82453702 ps
T1312 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2604264124 Feb 09 03:54:33 AM UTC 25 Feb 09 03:54:37 AM UTC 25 523294226 ps
T1313 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.2300150049 Feb 09 03:54:35 AM UTC 25 Feb 09 03:54:39 AM UTC 25 136746097 ps
T1314 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.82467160 Feb 09 03:54:35 AM UTC 25 Feb 09 03:54:39 AM UTC 25 66787022 ps
T1315 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.873985477 Feb 09 03:54:35 AM UTC 25 Feb 09 03:54:39 AM UTC 25 154746949 ps
T1316 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3147238775 Feb 09 03:54:36 AM UTC 25 Feb 09 03:54:39 AM UTC 25 573103766 ps
T1317 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3146225445 Feb 09 03:54:36 AM UTC 25 Feb 09 03:54:40 AM UTC 25 548473939 ps
T1318 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1883733316 Feb 09 03:54:19 AM UTC 25 Feb 09 03:54:41 AM UTC 25 858292368 ps
T443 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3568695949 Feb 09 03:54:15 AM UTC 25 Feb 09 03:54:49 AM UTC 25 1741820799 ps

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.3969361644
Short name T11
Test name
Test status
Simulation time 831706417 ps
CPU time 13.28 seconds
Started Feb 09 04:11:40 AM UTC 25
Finished Feb 09 04:11:55 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969361644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3969361644
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.3081214303
Short name T260
Test name
Test status
Simulation time 21471357393 ps
CPU time 174 seconds
Started Feb 09 04:11:45 AM UTC 25
Finished Feb 09 04:14:42 AM UTC 25
Peak memory 257288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081214303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.3081214303
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.3780169675
Short name T97
Test name
Test status
Simulation time 1019068921 ps
CPU time 27.98 seconds
Started Feb 09 04:11:41 AM UTC 25
Finished Feb 09 04:12:11 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780169675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3780169675
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2078978544
Short name T107
Test name
Test status
Simulation time 22286032434 ps
CPU time 67.83 seconds
Started Feb 09 04:12:05 AM UTC 25
Finished Feb 09 04:13:14 AM UTC 25
Peak memory 255240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078978544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.2078978544
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.1568631655
Short name T14
Test name
Test status
Simulation time 10326045239 ps
CPU time 300.67 seconds
Started Feb 09 04:14:51 AM UTC 25
Finished Feb 09 04:19:55 AM UTC 25
Peak memory 267776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1568631655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_al
l_with_rand_reset.1568631655
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.2206012731
Short name T12
Test name
Test status
Simulation time 564988782 ps
CPU time 12.32 seconds
Started Feb 09 04:11:41 AM UTC 25
Finished Feb 09 04:11:55 AM UTC 25
Peak memory 251068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206012731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2206012731
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.4247062096
Short name T308
Test name
Test status
Simulation time 15356489135 ps
CPU time 163.5 seconds
Started Feb 09 04:12:23 AM UTC 25
Finished Feb 09 04:15:09 AM UTC 25
Peak memory 267740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247062096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.4247062096
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.4199834987
Short name T27
Test name
Test status
Simulation time 10250508313 ps
CPU time 185.39 seconds
Started Feb 09 04:11:47 AM UTC 25
Finished Feb 09 04:14:55 AM UTC 25
Peak memory 289472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199834987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.4199834987
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.522296452
Short name T191
Test name
Test status
Simulation time 1684952022 ps
CPU time 7.38 seconds
Started Feb 09 04:46:43 AM UTC 25
Finished Feb 09 04:46:51 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522296452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.522296452
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2118361328
Short name T149
Test name
Test status
Simulation time 24584136951 ps
CPU time 39.93 seconds
Started Feb 09 04:12:49 AM UTC 25
Finished Feb 09 04:13:30 AM UTC 25
Peak memory 253468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118361328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2118361328
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.2193426230
Short name T96
Test name
Test status
Simulation time 1679951979 ps
CPU time 37.68 seconds
Started Feb 09 04:11:40 AM UTC 25
Finished Feb 09 04:12:19 AM UTC 25
Peak memory 257336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193426230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2193426230
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.3889671130
Short name T175
Test name
Test status
Simulation time 10707602224 ps
CPU time 113.29 seconds
Started Feb 09 04:14:53 AM UTC 25
Finished Feb 09 04:16:48 AM UTC 25
Peak memory 267832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889671130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.3889671130
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.1157454580
Short name T177
Test name
Test status
Simulation time 1008868050 ps
CPU time 38.85 seconds
Started Feb 09 04:12:43 AM UTC 25
Finished Feb 09 04:13:24 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157454580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1157454580
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.455274909
Short name T51
Test name
Test status
Simulation time 13574035067 ps
CPU time 29.77 seconds
Started Feb 09 04:12:01 AM UTC 25
Finished Feb 09 04:12:32 AM UTC 25
Peak memory 257596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455274909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.455274909
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3299308206
Short name T306
Test name
Test status
Simulation time 1957416035 ps
CPU time 21.15 seconds
Started Feb 09 03:52:49 AM UTC 25
Finished Feb 09 03:53:12 AM UTC 25
Peak memory 257108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299308206 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.3299308206
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.1728714865
Short name T31
Test name
Test status
Simulation time 511290678 ps
CPU time 4.47 seconds
Started Feb 09 04:48:38 AM UTC 25
Finished Feb 09 04:48:44 AM UTC 25
Peak memory 253368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728714865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1728714865
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.2754010898
Short name T283
Test name
Test status
Simulation time 66782113087 ps
CPU time 362.66 seconds
Started Feb 09 04:13:54 AM UTC 25
Finished Feb 09 04:20:02 AM UTC 25
Peak memory 284088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754010898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.2754010898
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.2416333989
Short name T43
Test name
Test status
Simulation time 196339145 ps
CPU time 5.29 seconds
Started Feb 09 04:14:35 AM UTC 25
Finished Feb 09 04:14:41 AM UTC 25
Peak memory 250868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416333989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2416333989
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.254530964
Short name T392
Test name
Test status
Simulation time 164241949220 ps
CPU time 948.48 seconds
Started Feb 09 04:25:18 AM UTC 25
Finished Feb 09 04:41:17 AM UTC 25
Peak memory 355624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=254530964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_al
l_with_rand_reset.254530964
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.144202691
Short name T54
Test name
Test status
Simulation time 184331959 ps
CPU time 7.02 seconds
Started Feb 09 04:14:19 AM UTC 25
Finished Feb 09 04:14:27 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144202691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.144202691
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.1141337025
Short name T178
Test name
Test status
Simulation time 4424666347 ps
CPU time 30.17 seconds
Started Feb 09 04:16:21 AM UTC 25
Finished Feb 09 04:16:53 AM UTC 25
Peak memory 257376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141337025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1141337025
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.3369656590
Short name T99
Test name
Test status
Simulation time 509107097 ps
CPU time 16.7 seconds
Started Feb 09 04:11:41 AM UTC 25
Finished Feb 09 04:12:00 AM UTC 25
Peak memory 257436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369656590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3369656590
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1468198801
Short name T431
Test name
Test status
Simulation time 18654619092 ps
CPU time 118.09 seconds
Started Feb 09 04:14:12 AM UTC 25
Finished Feb 09 04:16:12 AM UTC 25
Peak memory 257468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468198801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1468198801
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2493735074
Short name T40
Test name
Test status
Simulation time 500173598 ps
CPU time 8.26 seconds
Started Feb 09 04:11:53 AM UTC 25
Finished Feb 09 04:12:02 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493735074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2493735074
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.626761526
Short name T342
Test name
Test status
Simulation time 200413268844 ps
CPU time 1557.14 seconds
Started Feb 09 04:30:36 AM UTC 25
Finished Feb 09 04:56:50 AM UTC 25
Peak memory 290304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=626761526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_al
l_with_rand_reset.626761526
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.3450788864
Short name T163
Test name
Test status
Simulation time 2634135915 ps
CPU time 51.61 seconds
Started Feb 09 04:15:28 AM UTC 25
Finished Feb 09 04:16:22 AM UTC 25
Peak memory 257288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450788864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.3450788864
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.1948074613
Short name T39
Test name
Test status
Simulation time 1482557002 ps
CPU time 10.73 seconds
Started Feb 09 04:22:01 AM UTC 25
Finished Feb 09 04:22:13 AM UTC 25
Peak memory 257468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948074613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.1948074613
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.2394637618
Short name T241
Test name
Test status
Simulation time 37183876705 ps
CPU time 183.73 seconds
Started Feb 09 04:15:51 AM UTC 25
Finished Feb 09 04:18:58 AM UTC 25
Peak memory 273852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394637618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.2394637618
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.3979053799
Short name T183
Test name
Test status
Simulation time 2018430733 ps
CPU time 9.05 seconds
Started Feb 09 04:46:21 AM UTC 25
Finished Feb 09 04:46:31 AM UTC 25
Peak memory 251024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979053799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3979053799
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.3318273084
Short name T77
Test name
Test status
Simulation time 1929647042 ps
CPU time 6.31 seconds
Started Feb 09 04:23:19 AM UTC 25
Finished Feb 09 04:23:27 AM UTC 25
Peak memory 251268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318273084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3318273084
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3688448843
Short name T74
Test name
Test status
Simulation time 2531648020 ps
CPU time 6.74 seconds
Started Feb 09 04:18:34 AM UTC 25
Finished Feb 09 04:18:42 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688448843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3688448843
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3569300860
Short name T355
Test name
Test status
Simulation time 108762345 ps
CPU time 5.32 seconds
Started Feb 09 03:52:48 AM UTC 25
Finished Feb 09 03:52:55 AM UTC 25
Peak memory 253068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569300860 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.3569300860
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.688029414
Short name T87
Test name
Test status
Simulation time 557813673 ps
CPU time 5.83 seconds
Started Feb 09 04:14:57 AM UTC 25
Finished Feb 09 04:15:04 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688029414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.688029414
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.576581440
Short name T10
Test name
Test status
Simulation time 52583885 ps
CPU time 2.69 seconds
Started Feb 09 04:11:49 AM UTC 25
Finished Feb 09 04:11:52 AM UTC 25
Peak memory 251032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576581440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.576581440
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.1246261579
Short name T69
Test name
Test status
Simulation time 214817216 ps
CPU time 6.3 seconds
Started Feb 09 04:46:38 AM UTC 25
Finished Feb 09 04:46:45 AM UTC 25
Peak memory 251392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246261579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1246261579
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.2285850389
Short name T966
Test name
Test status
Simulation time 150929093 ps
CPU time 5.04 seconds
Started Feb 09 04:47:41 AM UTC 25
Finished Feb 09 04:47:47 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285850389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2285850389
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3760851024
Short name T57
Test name
Test status
Simulation time 180114421 ps
CPU time 6.12 seconds
Started Feb 09 04:45:53 AM UTC 25
Finished Feb 09 04:46:01 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760851024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3760851024
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.2299804438
Short name T72
Test name
Test status
Simulation time 3573925927 ps
CPU time 28.2 seconds
Started Feb 09 04:17:58 AM UTC 25
Finished Feb 09 04:18:27 AM UTC 25
Peak memory 251260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299804438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2299804438
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.4241764853
Short name T3
Test name
Test status
Simulation time 1463775533 ps
CPU time 6.64 seconds
Started Feb 09 04:11:40 AM UTC 25
Finished Feb 09 04:11:48 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241764853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.4241764853
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2918523915
Short name T137
Test name
Test status
Simulation time 5224730602 ps
CPU time 62.62 seconds
Started Feb 09 04:15:07 AM UTC 25
Finished Feb 09 04:16:12 AM UTC 25
Peak memory 255496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918523915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.2918523915
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3220187691
Short name T23
Test name
Test status
Simulation time 69712724987 ps
CPU time 1329.42 seconds
Started Feb 09 04:18:00 AM UTC 25
Finished Feb 09 04:40:25 AM UTC 25
Peak memory 288252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3220187691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_a
ll_with_rand_reset.3220187691
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1936138336
Short name T187
Test name
Test status
Simulation time 98704024 ps
CPU time 3.93 seconds
Started Feb 09 04:15:15 AM UTC 25
Finished Feb 09 04:15:21 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936138336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1936138336
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3770123960
Short name T28
Test name
Test status
Simulation time 45065073100 ps
CPU time 173.66 seconds
Started Feb 09 04:12:07 AM UTC 25
Finished Feb 09 04:15:03 AM UTC 25
Peak memory 287364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770123960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3770123960
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3578475514
Short name T917
Test name
Test status
Simulation time 80263522076 ps
CPU time 818.46 seconds
Started Feb 09 04:31:42 AM UTC 25
Finished Feb 09 04:45:30 AM UTC 25
Peak memory 311008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3578475514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_a
ll_with_rand_reset.3578475514
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.524971248
Short name T158
Test name
Test status
Simulation time 483913258 ps
CPU time 3.89 seconds
Started Feb 09 04:48:14 AM UTC 25
Finished Feb 09 04:48:19 AM UTC 25
Peak memory 251064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524971248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.524971248
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.914818381
Short name T266
Test name
Test status
Simulation time 7768396444 ps
CPU time 23.55 seconds
Started Feb 09 04:12:09 AM UTC 25
Finished Feb 09 04:12:34 AM UTC 25
Peak memory 253320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914818381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.otp_ctrl_smoke.914818381
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.1817103808
Short name T45
Test name
Test status
Simulation time 182656630 ps
CPU time 4.61 seconds
Started Feb 09 04:15:35 AM UTC 25
Finished Feb 09 04:15:41 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817103808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1817103808
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2306043857
Short name T307
Test name
Test status
Simulation time 1305882648 ps
CPU time 15.72 seconds
Started Feb 09 03:52:58 AM UTC 25
Finished Feb 09 03:53:15 AM UTC 25
Peak memory 257008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306043857 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.2306043857
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2504348681
Short name T25
Test name
Test status
Simulation time 42127029411 ps
CPU time 716.39 seconds
Started Feb 09 04:18:28 AM UTC 25
Finished Feb 09 04:30:34 AM UTC 25
Peak memory 290556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2504348681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_a
ll_with_rand_reset.2504348681
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.523704401
Short name T448
Test name
Test status
Simulation time 296662572 ps
CPU time 6.51 seconds
Started Feb 09 04:15:24 AM UTC 25
Finished Feb 09 04:15:32 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523704401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.523704401
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2582516245
Short name T440
Test name
Test status
Simulation time 11855696106 ps
CPU time 117.12 seconds
Started Feb 09 04:14:32 AM UTC 25
Finished Feb 09 04:16:32 AM UTC 25
Peak memory 257396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582516245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.2582516245
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.3752616532
Short name T50
Test name
Test status
Simulation time 2462447477 ps
CPU time 48.83 seconds
Started Feb 09 04:24:11 AM UTC 25
Finished Feb 09 04:25:02 AM UTC 25
Peak memory 253216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752616532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3752616532
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3002508422
Short name T105
Test name
Test status
Simulation time 24792556442 ps
CPU time 173.07 seconds
Started Feb 09 04:17:32 AM UTC 25
Finished Feb 09 04:20:28 AM UTC 25
Peak memory 267592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002508422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.3002508422
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.4110466646
Short name T239
Test name
Test status
Simulation time 298671392 ps
CPU time 15.46 seconds
Started Feb 09 04:17:21 AM UTC 25
Finished Feb 09 04:17:38 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110466646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.4110466646
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.1356239231
Short name T287
Test name
Test status
Simulation time 32835649922 ps
CPU time 156.47 seconds
Started Feb 09 04:26:40 AM UTC 25
Finished Feb 09 04:29:19 AM UTC 25
Peak memory 257480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356239231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.1356239231
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.456567641
Short name T171
Test name
Test status
Simulation time 164632745 ps
CPU time 3.65 seconds
Started Feb 09 04:30:51 AM UTC 25
Finished Feb 09 04:30:56 AM UTC 25
Peak memory 250776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456567641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.456567641
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2607922669
Short name T22
Test name
Test status
Simulation time 42098009362 ps
CPU time 566.91 seconds
Started Feb 09 04:27:39 AM UTC 25
Finished Feb 09 04:37:13 AM UTC 25
Peak memory 268028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2607922669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_a
ll_with_rand_reset.2607922669
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.2014507565
Short name T168
Test name
Test status
Simulation time 2618876997 ps
CPU time 6.56 seconds
Started Feb 09 04:17:04 AM UTC 25
Finished Feb 09 04:17:12 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014507565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2014507565
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.296948127
Short name T333
Test name
Test status
Simulation time 5222463569 ps
CPU time 53.34 seconds
Started Feb 09 04:45:27 AM UTC 25
Finished Feb 09 04:46:23 AM UTC 25
Peak memory 253236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296948127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.296948127
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2302788459
Short name T32
Test name
Test status
Simulation time 198002506 ps
CPU time 4.84 seconds
Started Feb 09 04:49:29 AM UTC 25
Finished Feb 09 04:49:35 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302788459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2302788459
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.1014687493
Short name T148
Test name
Test status
Simulation time 178298162 ps
CPU time 5.84 seconds
Started Feb 09 04:50:30 AM UTC 25
Finished Feb 09 04:50:38 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014687493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1014687493
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.3594271047
Short name T166
Test name
Test status
Simulation time 153506951 ps
CPU time 5.36 seconds
Started Feb 09 04:24:36 AM UTC 25
Finished Feb 09 04:24:42 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594271047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3594271047
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.2583224032
Short name T279
Test name
Test status
Simulation time 9926978049 ps
CPU time 97.8 seconds
Started Feb 09 04:17:00 AM UTC 25
Finished Feb 09 04:18:39 AM UTC 25
Peak memory 255584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583224032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.2583224032
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.548513094
Short name T446
Test name
Test status
Simulation time 327910724 ps
CPU time 15.41 seconds
Started Feb 09 04:16:26 AM UTC 25
Finished Feb 09 04:16:43 AM UTC 25
Peak memory 251012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548513094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.548513094
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2050641725
Short name T450
Test name
Test status
Simulation time 490926846 ps
CPU time 13.23 seconds
Started Feb 09 04:17:59 AM UTC 25
Finished Feb 09 04:18:13 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050641725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2050641725
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.3692995867
Short name T262
Test name
Test status
Simulation time 41703479942 ps
CPU time 142.4 seconds
Started Feb 09 04:13:22 AM UTC 25
Finished Feb 09 04:15:47 AM UTC 25
Peak memory 259480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692995867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.3692995867
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.134936914
Short name T70
Test name
Test status
Simulation time 124058776 ps
CPU time 5.4 seconds
Started Feb 09 04:23:28 AM UTC 25
Finished Feb 09 04:23:34 AM UTC 25
Peak memory 251188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134936914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.134936914
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.3906686453
Short name T36
Test name
Test status
Simulation time 139219419 ps
CPU time 5.76 seconds
Started Feb 09 04:26:29 AM UTC 25
Finished Feb 09 04:26:36 AM UTC 25
Peak memory 257340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906686453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3906686453
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1563701093
Short name T305
Test name
Test status
Simulation time 677969504 ps
CPU time 13.68 seconds
Started Feb 09 03:52:39 AM UTC 25
Finished Feb 09 03:52:54 AM UTC 25
Peak memory 257028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563701093 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.1563701093
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3933220727
Short name T393
Test name
Test status
Simulation time 208336265599 ps
CPU time 1822.47 seconds
Started Feb 09 04:17:47 AM UTC 25
Finished Feb 09 04:48:29 AM UTC 25
Peak memory 452092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3933220727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_a
ll_with_rand_reset.3933220727
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.734106972
Short name T314
Test name
Test status
Simulation time 69995728 ps
CPU time 3.33 seconds
Started Feb 09 03:52:48 AM UTC 25
Finished Feb 09 03:52:53 AM UTC 25
Peak memory 252880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734106972 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.734106972
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.507072494
Short name T30
Test name
Test status
Simulation time 201013391 ps
CPU time 5.9 seconds
Started Feb 09 04:47:10 AM UTC 25
Finished Feb 09 04:47:17 AM UTC 25
Peak memory 253172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507072494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.507072494
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2493942858
Short name T84
Test name
Test status
Simulation time 1473163282 ps
CPU time 40.76 seconds
Started Feb 09 04:14:46 AM UTC 25
Finished Feb 09 04:15:28 AM UTC 25
Peak memory 257276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493942858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2493942858
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.812580261
Short name T38
Test name
Test status
Simulation time 1239904886 ps
CPU time 26.73 seconds
Started Feb 09 04:18:20 AM UTC 25
Finished Feb 09 04:18:48 AM UTC 25
Peak memory 257268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812580261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.812580261
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2654358706
Short name T153
Test name
Test status
Simulation time 67442327638 ps
CPU time 1311.95 seconds
Started Feb 09 04:24:00 AM UTC 25
Finished Feb 09 04:46:06 AM UTC 25
Peak memory 394940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2654358706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_a
ll_with_rand_reset.2654358706
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.590728226
Short name T83
Test name
Test status
Simulation time 20060795032 ps
CPU time 48.1 seconds
Started Feb 09 04:19:15 AM UTC 25
Finished Feb 09 04:20:05 AM UTC 25
Peak memory 255540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590728226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.590728226
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1661516649
Short name T246
Test name
Test status
Simulation time 14562601946 ps
CPU time 142.49 seconds
Started Feb 09 04:23:15 AM UTC 25
Finished Feb 09 04:25:40 AM UTC 25
Peak memory 286072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661516649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.1661516649
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.728443881
Short name T430
Test name
Test status
Simulation time 14268681389 ps
CPU time 54.04 seconds
Started Feb 09 04:14:46 AM UTC 25
Finished Feb 09 04:15:42 AM UTC 25
Peak memory 269656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728443881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.728443881
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.1010156864
Short name T504
Test name
Test status
Simulation time 3294086078 ps
CPU time 22.27 seconds
Started Feb 09 04:16:04 AM UTC 25
Finished Feb 09 04:16:27 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010156864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1010156864
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.2896015654
Short name T136
Test name
Test status
Simulation time 264805169 ps
CPU time 5.42 seconds
Started Feb 09 04:45:38 AM UTC 25
Finished Feb 09 04:45:45 AM UTC 25
Peak memory 252900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896015654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2896015654
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.1507929706
Short name T922
Test name
Test status
Simulation time 185621737 ps
CPU time 6.06 seconds
Started Feb 09 04:46:06 AM UTC 25
Finished Feb 09 04:46:13 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507929706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1507929706
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.3622397877
Short name T101
Test name
Test status
Simulation time 97649885 ps
CPU time 5.17 seconds
Started Feb 09 04:12:10 AM UTC 25
Finished Feb 09 04:12:17 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622397877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3622397877
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.3288943436
Short name T242
Test name
Test status
Simulation time 46052934518 ps
CPU time 133.68 seconds
Started Feb 09 04:17:13 AM UTC 25
Finished Feb 09 04:19:29 AM UTC 25
Peak memory 257288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288943436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.3288943436
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2361480225
Short name T155
Test name
Test status
Simulation time 1214292780171 ps
CPU time 2676.32 seconds
Started Feb 09 04:31:31 AM UTC 25
Finished Feb 09 05:16:35 AM UTC 25
Peak memory 386524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2361480225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_a
ll_with_rand_reset.2361480225
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1435676768
Short name T125
Test name
Test status
Simulation time 2182109122 ps
CPU time 24.66 seconds
Started Feb 09 04:12:12 AM UTC 25
Finished Feb 09 04:12:38 AM UTC 25
Peak memory 257504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435676768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1435676768
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2040067212
Short name T2
Test name
Test status
Simulation time 737252867 ps
CPU time 3.29 seconds
Started Feb 09 04:11:39 AM UTC 25
Finished Feb 09 04:11:43 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040067212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2040067212
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2450819700
Short name T415
Test name
Test status
Simulation time 11322642533 ps
CPU time 68.46 seconds
Started Feb 09 04:12:47 AM UTC 25
Finished Feb 09 04:13:57 AM UTC 25
Peak memory 257320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450819700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2450819700
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1453539398
Short name T297
Test name
Test status
Simulation time 156563712924 ps
CPU time 3226.28 seconds
Started Feb 09 04:25:59 AM UTC 25
Finished Feb 09 05:20:19 AM UTC 25
Peak memory 407228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1453539398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_a
ll_with_rand_reset.1453539398
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2820661968
Short name T315
Test name
Test status
Simulation time 2243824916 ps
CPU time 34.17 seconds
Started Feb 09 03:53:19 AM UTC 25
Finished Feb 09 03:53:55 AM UTC 25
Peak memory 257088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820661968 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2820661968
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.3318512195
Short name T278
Test name
Test status
Simulation time 190338868 ps
CPU time 5.9 seconds
Started Feb 09 04:50:05 AM UTC 25
Finished Feb 09 04:50:12 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318512195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3318512195
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.957857520
Short name T491
Test name
Test status
Simulation time 2246448335 ps
CPU time 27.19 seconds
Started Feb 09 04:17:28 AM UTC 25
Finished Feb 09 04:17:57 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957857520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.957857520
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.1269839455
Short name T124
Test name
Test status
Simulation time 13500518996 ps
CPU time 24.63 seconds
Started Feb 09 04:11:57 AM UTC 25
Finished Feb 09 04:12:23 AM UTC 25
Peak memory 253216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269839455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1269839455
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1288852204
Short name T115
Test name
Test status
Simulation time 116049809 ps
CPU time 4.68 seconds
Started Feb 09 04:50:13 AM UTC 25
Finished Feb 09 04:50:19 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288852204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1288852204
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.3052144840
Short name T325
Test name
Test status
Simulation time 1236373017 ps
CPU time 21.67 seconds
Started Feb 09 04:16:26 AM UTC 25
Finished Feb 09 04:16:49 AM UTC 25
Peak memory 257004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052144840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3052144840
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.1307490682
Short name T140
Test name
Test status
Simulation time 51237973045 ps
CPU time 120.62 seconds
Started Feb 09 04:16:27 AM UTC 25
Finished Feb 09 04:18:30 AM UTC 25
Peak memory 267588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307490682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.1307490682
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.802658142
Short name T195
Test name
Test status
Simulation time 567687484 ps
CPU time 18.17 seconds
Started Feb 09 04:15:20 AM UTC 25
Finished Feb 09 04:15:40 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802658142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.802658142
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1255076202
Short name T310
Test name
Test status
Simulation time 125864543 ps
CPU time 8.38 seconds
Started Feb 09 03:52:45 AM UTC 25
Finished Feb 09 03:52:55 AM UTC 25
Peak memory 242744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255076202 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.1255076202
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1146451742
Short name T313
Test name
Test status
Simulation time 103759508 ps
CPU time 3.52 seconds
Started Feb 09 03:52:44 AM UTC 25
Finished Feb 09 03:52:49 AM UTC 25
Peak memory 252996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146451742 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.1146451742
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2213655702
Short name T309
Test name
Test status
Simulation time 295054989 ps
CPU time 3.79 seconds
Started Feb 09 03:52:49 AM UTC 25
Finished Feb 09 03:52:54 AM UTC 25
Peak memory 259236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22136
55702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_res
et.2213655702
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2179749933
Short name T312
Test name
Test status
Simulation time 53293291 ps
CPU time 2.5 seconds
Started Feb 09 03:52:44 AM UTC 25
Finished Feb 09 03:52:48 AM UTC 25
Peak memory 252868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179749933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2179749933
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1532609237
Short name T1191
Test name
Test status
Simulation time 96239135 ps
CPU time 2.04 seconds
Started Feb 09 03:52:40 AM UTC 25
Finished Feb 09 03:52:43 AM UTC 25
Peak memory 242584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532609237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1532609237
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3778042900
Short name T1193
Test name
Test status
Simulation time 36088241 ps
CPU time 2.19 seconds
Started Feb 09 03:52:44 AM UTC 25
Finished Feb 09 03:52:47 AM UTC 25
Peak memory 242364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778042900 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.3778042900
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4211570675
Short name T1190
Test name
Test status
Simulation time 139630993 ps
CPU time 1.87 seconds
Started Feb 09 03:52:40 AM UTC 25
Finished Feb 09 03:52:43 AM UTC 25
Peak memory 241472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211570675 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.4211570675
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1851141003
Short name T1192
Test name
Test status
Simulation time 85226823 ps
CPU time 6.75 seconds
Started Feb 09 03:52:36 AM UTC 25
Finished Feb 09 03:52:44 AM UTC 25
Peak memory 259072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851141003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1851141003
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4030063762
Short name T357
Test name
Test status
Simulation time 209076843 ps
CPU time 4.79 seconds
Started Feb 09 03:52:55 AM UTC 25
Finished Feb 09 03:53:01 AM UTC 25
Peak memory 253060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030063762 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.4030063762
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1074832571
Short name T387
Test name
Test status
Simulation time 189474960 ps
CPU time 5.34 seconds
Started Feb 09 03:52:55 AM UTC 25
Finished Feb 09 03:53:01 AM UTC 25
Peak memory 252868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074832571 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.1074832571
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2290677472
Short name T1198
Test name
Test status
Simulation time 115685814 ps
CPU time 3.16 seconds
Started Feb 09 03:52:54 AM UTC 25
Finished Feb 09 03:52:58 AM UTC 25
Peak memory 253048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290677472 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.2290677472
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.501805913
Short name T1199
Test name
Test status
Simulation time 1122681372 ps
CPU time 3.46 seconds
Started Feb 09 03:52:56 AM UTC 25
Finished Feb 09 03:53:00 AM UTC 25
Peak memory 259136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50180
5913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.501805913
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3990385358
Short name T356
Test name
Test status
Simulation time 165025192 ps
CPU time 1.89 seconds
Started Feb 09 03:52:55 AM UTC 25
Finished Feb 09 03:52:58 AM UTC 25
Peak memory 253936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990385358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3990385358
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2069978683
Short name T1194
Test name
Test status
Simulation time 147344844 ps
CPU time 2.37 seconds
Started Feb 09 03:52:49 AM UTC 25
Finished Feb 09 03:52:53 AM UTC 25
Peak memory 241916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069978683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2069978683
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4025183025
Short name T1196
Test name
Test status
Simulation time 45041826 ps
CPU time 2.2 seconds
Started Feb 09 03:52:53 AM UTC 25
Finished Feb 09 03:52:57 AM UTC 25
Peak memory 241548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025183025 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.4025183025
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4268151310
Short name T1195
Test name
Test status
Simulation time 60920960 ps
CPU time 2.19 seconds
Started Feb 09 03:52:51 AM UTC 25
Finished Feb 09 03:52:55 AM UTC 25
Peak memory 242424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268151310 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.4268151310
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2230849170
Short name T311
Test name
Test status
Simulation time 125412049 ps
CPU time 3.39 seconds
Started Feb 09 03:52:56 AM UTC 25
Finished Feb 09 03:53:00 AM UTC 25
Peak memory 252924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230849170 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.2230849170
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3035337271
Short name T1197
Test name
Test status
Simulation time 153280996 ps
CPU time 7.27 seconds
Started Feb 09 03:52:49 AM UTC 25
Finished Feb 09 03:52:58 AM UTC 25
Peak memory 259120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035337271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3035337271
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2787160511
Short name T1240
Test name
Test status
Simulation time 424571314 ps
CPU time 4.61 seconds
Started Feb 09 03:53:44 AM UTC 25
Finished Feb 09 03:53:50 AM UTC 25
Peak memory 259272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27871
60511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_re
set.2787160511
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1636521852
Short name T369
Test name
Test status
Simulation time 593114261 ps
CPU time 2.9 seconds
Started Feb 09 03:53:42 AM UTC 25
Finished Feb 09 03:53:46 AM UTC 25
Peak memory 253072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636521852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1636521852
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3916977142
Short name T1236
Test name
Test status
Simulation time 46005315 ps
CPU time 2.28 seconds
Started Feb 09 03:53:42 AM UTC 25
Finished Feb 09 03:53:45 AM UTC 25
Peak memory 241960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916977142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3916977142
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2935692377
Short name T1238
Test name
Test status
Simulation time 128578301 ps
CPU time 3.59 seconds
Started Feb 09 03:53:44 AM UTC 25
Finished Feb 09 03:53:49 AM UTC 25
Peak memory 252996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935692377 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.2935692377
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3712676762
Short name T1237
Test name
Test status
Simulation time 598157392 ps
CPU time 7.14 seconds
Started Feb 09 03:53:39 AM UTC 25
Finished Feb 09 03:53:47 AM UTC 25
Peak memory 252876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712676762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3712676762
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1261253236
Short name T1253
Test name
Test status
Simulation time 752227076 ps
CPU time 18.28 seconds
Started Feb 09 03:53:41 AM UTC 25
Finished Feb 09 03:54:00 AM UTC 25
Peak memory 256960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261253236 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.1261253236
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2669847944
Short name T1243
Test name
Test status
Simulation time 73228936 ps
CPU time 2.66 seconds
Started Feb 09 03:53:48 AM UTC 25
Finished Feb 09 03:53:52 AM UTC 25
Peak memory 257144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26698
47944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_re
set.2669847944
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3072730268
Short name T1242
Test name
Test status
Simulation time 630401059 ps
CPU time 3.24 seconds
Started Feb 09 03:53:47 AM UTC 25
Finished Feb 09 03:53:52 AM UTC 25
Peak memory 252884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072730268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3072730268
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.2795564675
Short name T1239
Test name
Test status
Simulation time 36821104 ps
CPU time 2.21 seconds
Started Feb 09 03:53:46 AM UTC 25
Finished Feb 09 03:53:50 AM UTC 25
Peak memory 242168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795564675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2795564675
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1719075985
Short name T1241
Test name
Test status
Simulation time 93329100 ps
CPU time 3.12 seconds
Started Feb 09 03:53:47 AM UTC 25
Finished Feb 09 03:53:52 AM UTC 25
Peak memory 254680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719075985 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.1719075985
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4225921463
Short name T1246
Test name
Test status
Simulation time 297150413 ps
CPU time 8.66 seconds
Started Feb 09 03:53:45 AM UTC 25
Finished Feb 09 03:53:55 AM UTC 25
Peak memory 259060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225921463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.4225921463
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4263374648
Short name T442
Test name
Test status
Simulation time 727323990 ps
CPU time 11.98 seconds
Started Feb 09 03:53:45 AM UTC 25
Finished Feb 09 03:53:58 AM UTC 25
Peak memory 257024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263374648 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.4263374648
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.747455482
Short name T1248
Test name
Test status
Simulation time 148390646 ps
CPU time 3.76 seconds
Started Feb 09 03:53:52 AM UTC 25
Finished Feb 09 03:53:57 AM UTC 25
Peak memory 259200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74745
5482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.747455482
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4192225275
Short name T1245
Test name
Test status
Simulation time 45607924 ps
CPU time 2.74 seconds
Started Feb 09 03:53:51 AM UTC 25
Finished Feb 09 03:53:55 AM UTC 25
Peak memory 254860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192225275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4192225275
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3277271982
Short name T1244
Test name
Test status
Simulation time 41955438 ps
CPU time 2.28 seconds
Started Feb 09 03:53:51 AM UTC 25
Finished Feb 09 03:53:54 AM UTC 25
Peak memory 241752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277271982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3277271982
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2697781097
Short name T1247
Test name
Test status
Simulation time 1015689455 ps
CPU time 3.64 seconds
Started Feb 09 03:53:52 AM UTC 25
Finished Feb 09 03:53:57 AM UTC 25
Peak memory 253012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697781097 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.2697781097
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.12853153
Short name T1249
Test name
Test status
Simulation time 1096674870 ps
CPU time 6.16 seconds
Started Feb 09 03:53:50 AM UTC 25
Finished Feb 09 03:53:57 AM UTC 25
Peak memory 259072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12853153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.12853153
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3891494869
Short name T439
Test name
Test status
Simulation time 1199769675 ps
CPU time 26.93 seconds
Started Feb 09 03:53:50 AM UTC 25
Finished Feb 09 03:54:18 AM UTC 25
Peak memory 259196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891494869 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.3891494869
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.325489807
Short name T1252
Test name
Test status
Simulation time 85421800 ps
CPU time 2.54 seconds
Started Feb 09 03:53:56 AM UTC 25
Finished Feb 09 03:54:00 AM UTC 25
Peak memory 259188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32548
9807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.325489807
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1534073782
Short name T1251
Test name
Test status
Simulation time 41349456 ps
CPU time 2.49 seconds
Started Feb 09 03:53:55 AM UTC 25
Finished Feb 09 03:53:59 AM UTC 25
Peak memory 254864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534073782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1534073782
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.2674841990
Short name T1250
Test name
Test status
Simulation time 148087470 ps
CPU time 2.39 seconds
Started Feb 09 03:53:55 AM UTC 25
Finished Feb 09 03:53:59 AM UTC 25
Peak memory 242388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674841990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2674841990
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3541049533
Short name T1256
Test name
Test status
Simulation time 114128173 ps
CPU time 5.03 seconds
Started Feb 09 03:53:56 AM UTC 25
Finished Feb 09 03:54:02 AM UTC 25
Peak memory 252940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541049533 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.3541049533
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4215431301
Short name T1254
Test name
Test status
Simulation time 2594077724 ps
CPU time 7.8 seconds
Started Feb 09 03:53:52 AM UTC 25
Finished Feb 09 03:54:01 AM UTC 25
Peak memory 259072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215431301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.4215431301
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4119524843
Short name T438
Test name
Test status
Simulation time 1312120796 ps
CPU time 21.45 seconds
Started Feb 09 03:53:53 AM UTC 25
Finished Feb 09 03:54:16 AM UTC 25
Peak memory 252940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119524843 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.4119524843
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1545411968
Short name T1259
Test name
Test status
Simulation time 101521598 ps
CPU time 3.92 seconds
Started Feb 09 03:54:00 AM UTC 25
Finished Feb 09 03:54:05 AM UTC 25
Peak memory 259212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15454
11968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_re
set.1545411968
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3198527519
Short name T370
Test name
Test status
Simulation time 57928504 ps
CPU time 2.5 seconds
Started Feb 09 03:53:59 AM UTC 25
Finished Feb 09 03:54:03 AM UTC 25
Peak memory 253064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198527519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3198527519
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.446724063
Short name T1255
Test name
Test status
Simulation time 593574343 ps
CPU time 2.71 seconds
Started Feb 09 03:53:57 AM UTC 25
Finished Feb 09 03:54:01 AM UTC 25
Peak memory 242580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446724063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.446724063
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4062902864
Short name T1257
Test name
Test status
Simulation time 171289576 ps
CPU time 2.6 seconds
Started Feb 09 03:54:00 AM UTC 25
Finished Feb 09 03:54:03 AM UTC 25
Peak memory 252868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062902864 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.4062902864
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1420565498
Short name T1258
Test name
Test status
Simulation time 1481746688 ps
CPU time 6.06 seconds
Started Feb 09 03:53:57 AM UTC 25
Finished Feb 09 03:54:04 AM UTC 25
Peak memory 259068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420565498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1420565498
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3091693019
Short name T444
Test name
Test status
Simulation time 2584819974 ps
CPU time 23.5 seconds
Started Feb 09 03:53:57 AM UTC 25
Finished Feb 09 03:54:22 AM UTC 25
Peak memory 253188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091693019 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.3091693019
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4189903515
Short name T1264
Test name
Test status
Simulation time 104123980 ps
CPU time 3.73 seconds
Started Feb 09 03:54:04 AM UTC 25
Finished Feb 09 03:54:09 AM UTC 25
Peak memory 259196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41899
03515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_re
set.4189903515
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.419582899
Short name T1261
Test name
Test status
Simulation time 563504782 ps
CPU time 2.88 seconds
Started Feb 09 03:54:02 AM UTC 25
Finished Feb 09 03:54:06 AM UTC 25
Peak memory 252968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419582899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.419582899
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.833156297
Short name T1260
Test name
Test status
Simulation time 38543467 ps
CPU time 2.22 seconds
Started Feb 09 03:54:02 AM UTC 25
Finished Feb 09 03:54:05 AM UTC 25
Peak memory 242000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833156297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.833156297
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3748413334
Short name T1263
Test name
Test status
Simulation time 1251635524 ps
CPU time 3.06 seconds
Started Feb 09 03:54:03 AM UTC 25
Finished Feb 09 03:54:07 AM UTC 25
Peak memory 252928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748413334 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.3748413334
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.364028173
Short name T1262
Test name
Test status
Simulation time 157251789 ps
CPU time 4.4 seconds
Started Feb 09 03:54:01 AM UTC 25
Finished Feb 09 03:54:06 AM UTC 25
Peak memory 259012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364028173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.364028173
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3873105023
Short name T1274
Test name
Test status
Simulation time 622054093 ps
CPU time 14.95 seconds
Started Feb 09 03:54:02 AM UTC 25
Finished Feb 09 03:54:18 AM UTC 25
Peak memory 257084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873105023 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.3873105023
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3885250975
Short name T1268
Test name
Test status
Simulation time 112010460 ps
CPU time 5.15 seconds
Started Feb 09 03:54:07 AM UTC 25
Finished Feb 09 03:54:13 AM UTC 25
Peak memory 259204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38852
50975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_re
set.3885250975
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3471694487
Short name T1266
Test name
Test status
Simulation time 53057870 ps
CPU time 2.72 seconds
Started Feb 09 03:54:06 AM UTC 25
Finished Feb 09 03:54:10 AM UTC 25
Peak memory 255020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471694487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3471694487
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.117123234
Short name T1265
Test name
Test status
Simulation time 630113754 ps
CPU time 3.46 seconds
Started Feb 09 03:54:05 AM UTC 25
Finished Feb 09 03:54:09 AM UTC 25
Peak memory 241968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117123234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.117123234
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3903382276
Short name T1269
Test name
Test status
Simulation time 1032627813 ps
CPU time 5.27 seconds
Started Feb 09 03:54:07 AM UTC 25
Finished Feb 09 03:54:13 AM UTC 25
Peak memory 252864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903382276 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.3903382276
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.549741156
Short name T1267
Test name
Test status
Simulation time 882309312 ps
CPU time 5.92 seconds
Started Feb 09 03:54:04 AM UTC 25
Finished Feb 09 03:54:11 AM UTC 25
Peak memory 259244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549741156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.549741156
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2475395380
Short name T1276
Test name
Test status
Simulation time 1663520539 ps
CPU time 12.55 seconds
Started Feb 09 03:54:05 AM UTC 25
Finished Feb 09 03:54:19 AM UTC 25
Peak memory 257164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475395380 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2475395380
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.841434136
Short name T1278
Test name
Test status
Simulation time 390621158 ps
CPU time 4.69 seconds
Started Feb 09 03:54:14 AM UTC 25
Finished Feb 09 03:54:20 AM UTC 25
Peak memory 259204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84143
4136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.841434136
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.732789481
Short name T1271
Test name
Test status
Simulation time 83588015 ps
CPU time 2.55 seconds
Started Feb 09 03:54:10 AM UTC 25
Finished Feb 09 03:54:14 AM UTC 25
Peak memory 254892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732789481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.732789481
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1513433100
Short name T1270
Test name
Test status
Simulation time 115637871 ps
CPU time 2.12 seconds
Started Feb 09 03:54:10 AM UTC 25
Finished Feb 09 03:54:14 AM UTC 25
Peak memory 242628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513433100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1513433100
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.623920543
Short name T1273
Test name
Test status
Simulation time 72186597 ps
CPU time 3.43 seconds
Started Feb 09 03:54:11 AM UTC 25
Finished Feb 09 03:54:16 AM UTC 25
Peak memory 255024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623920543 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.623920543
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1872840269
Short name T1272
Test name
Test status
Simulation time 82686012 ps
CPU time 4.81 seconds
Started Feb 09 03:54:08 AM UTC 25
Finished Feb 09 03:54:14 AM UTC 25
Peak memory 259068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872840269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1872840269
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.120668044
Short name T1295
Test name
Test status
Simulation time 1278111305 ps
CPU time 18.26 seconds
Started Feb 09 03:54:09 AM UTC 25
Finished Feb 09 03:54:29 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120668044 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.120668044
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2068201461
Short name T1282
Test name
Test status
Simulation time 321805237 ps
CPU time 4.89 seconds
Started Feb 09 03:54:17 AM UTC 25
Finished Feb 09 03:54:23 AM UTC 25
Peak memory 259200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20682
01461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_re
set.2068201461
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.495154198
Short name T1277
Test name
Test status
Simulation time 550595096 ps
CPU time 3.01 seconds
Started Feb 09 03:54:15 AM UTC 25
Finished Feb 09 03:54:19 AM UTC 25
Peak memory 253012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495154198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.495154198
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.757043490
Short name T1275
Test name
Test status
Simulation time 80604089 ps
CPU time 2.28 seconds
Started Feb 09 03:54:15 AM UTC 25
Finished Feb 09 03:54:18 AM UTC 25
Peak memory 241764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757043490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.757043490
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.476224606
Short name T1279
Test name
Test status
Simulation time 59946462 ps
CPU time 2.93 seconds
Started Feb 09 03:54:17 AM UTC 25
Finished Feb 09 03:54:21 AM UTC 25
Peak memory 252864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476224606 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.476224606
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2166682976
Short name T1280
Test name
Test status
Simulation time 131488292 ps
CPU time 5.94 seconds
Started Feb 09 03:54:15 AM UTC 25
Finished Feb 09 03:54:22 AM UTC 25
Peak memory 259060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166682976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2166682976
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3568695949
Short name T443
Test name
Test status
Simulation time 1741820799 ps
CPU time 33.23 seconds
Started Feb 09 03:54:15 AM UTC 25
Finished Feb 09 03:54:49 AM UTC 25
Peak memory 257100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568695949 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.3568695949
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3300219334
Short name T1287
Test name
Test status
Simulation time 1104516843 ps
CPU time 4.11 seconds
Started Feb 09 03:54:21 AM UTC 25
Finished Feb 09 03:54:26 AM UTC 25
Peak memory 259152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33002
19334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_re
set.3300219334
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.265158479
Short name T1283
Test name
Test status
Simulation time 80735686 ps
CPU time 2.44 seconds
Started Feb 09 03:54:20 AM UTC 25
Finished Feb 09 03:54:23 AM UTC 25
Peak memory 252824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265158479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.265158479
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1731490123
Short name T1281
Test name
Test status
Simulation time 36315109 ps
CPU time 1.98 seconds
Started Feb 09 03:54:19 AM UTC 25
Finished Feb 09 03:54:22 AM UTC 25
Peak memory 241664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731490123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1731490123
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.862658299
Short name T1293
Test name
Test status
Simulation time 1276032546 ps
CPU time 7.34 seconds
Started Feb 09 03:54:20 AM UTC 25
Finished Feb 09 03:54:28 AM UTC 25
Peak memory 252916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862658299 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.862658299
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2633616265
Short name T1284
Test name
Test status
Simulation time 82781530 ps
CPU time 4.06 seconds
Started Feb 09 03:54:19 AM UTC 25
Finished Feb 09 03:54:24 AM UTC 25
Peak memory 259260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633616265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2633616265
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1883733316
Short name T1318
Test name
Test status
Simulation time 858292368 ps
CPU time 20.39 seconds
Started Feb 09 03:54:19 AM UTC 25
Finished Feb 09 03:54:41 AM UTC 25
Peak memory 257096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883733316 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1883733316
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3715419005
Short name T358
Test name
Test status
Simulation time 1748394826 ps
CPU time 6.28 seconds
Started Feb 09 03:53:01 AM UTC 25
Finished Feb 09 03:53:09 AM UTC 25
Peak memory 242888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715419005 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.3715419005
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1816519949
Short name T1207
Test name
Test status
Simulation time 394121323 ps
CPU time 6.96 seconds
Started Feb 09 03:53:01 AM UTC 25
Finished Feb 09 03:53:09 AM UTC 25
Peak memory 252936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816519949 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.1816519949
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1251361030
Short name T362
Test name
Test status
Simulation time 103808164 ps
CPU time 2.58 seconds
Started Feb 09 03:52:59 AM UTC 25
Finished Feb 09 03:53:03 AM UTC 25
Peak memory 252932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251361030 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.1251361030
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.4128567688
Short name T453
Test name
Test status
Simulation time 134800748 ps
CPU time 3.7 seconds
Started Feb 09 03:53:02 AM UTC 25
Finished Feb 09 03:53:07 AM UTC 25
Peak memory 259236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41285
67688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_res
et.4128567688
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1889650961
Short name T454
Test name
Test status
Simulation time 57290097 ps
CPU time 2.68 seconds
Started Feb 09 03:53:01 AM UTC 25
Finished Feb 09 03:53:05 AM UTC 25
Peak memory 252940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889650961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1889650961
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1239591618
Short name T1200
Test name
Test status
Simulation time 70595730 ps
CPU time 2.48 seconds
Started Feb 09 03:52:58 AM UTC 25
Finished Feb 09 03:53:01 AM UTC 25
Peak memory 241748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239591618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1239591618
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2902439695
Short name T1201
Test name
Test status
Simulation time 70867830 ps
CPU time 2.25 seconds
Started Feb 09 03:52:59 AM UTC 25
Finished Feb 09 03:53:02 AM UTC 25
Peak memory 241884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902439695 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.2902439695
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3405555247
Short name T1203
Test name
Test status
Simulation time 554789440 ps
CPU time 2.6 seconds
Started Feb 09 03:52:59 AM UTC 25
Finished Feb 09 03:53:03 AM UTC 25
Peak memory 242624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405555247 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.3405555247
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3442856103
Short name T371
Test name
Test status
Simulation time 112883820 ps
CPU time 3.96 seconds
Started Feb 09 03:53:02 AM UTC 25
Finished Feb 09 03:53:07 AM UTC 25
Peak memory 252996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442856103 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.3442856103
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3817557727
Short name T1202
Test name
Test status
Simulation time 159496273 ps
CPU time 5.46 seconds
Started Feb 09 03:52:56 AM UTC 25
Finished Feb 09 03:53:02 AM UTC 25
Peak memory 259124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817557727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3817557727
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.940844914
Short name T1285
Test name
Test status
Simulation time 42005282 ps
CPU time 2.1 seconds
Started Feb 09 03:54:21 AM UTC 25
Finished Feb 09 03:54:24 AM UTC 25
Peak memory 241768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940844914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.940844914
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3488594594
Short name T1286
Test name
Test status
Simulation time 149721040 ps
CPU time 2.25 seconds
Started Feb 09 03:54:22 AM UTC 25
Finished Feb 09 03:54:25 AM UTC 25
Peak memory 242568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488594594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3488594594
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.3368840069
Short name T1290
Test name
Test status
Simulation time 139875845 ps
CPU time 2.48 seconds
Started Feb 09 03:54:23 AM UTC 25
Finished Feb 09 03:54:27 AM UTC 25
Peak memory 242584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368840069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3368840069
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3655755188
Short name T1288
Test name
Test status
Simulation time 142207672 ps
CPU time 2.24 seconds
Started Feb 09 03:54:23 AM UTC 25
Finished Feb 09 03:54:27 AM UTC 25
Peak memory 241888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655755188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3655755188
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3654621106
Short name T1289
Test name
Test status
Simulation time 53562631 ps
CPU time 2.25 seconds
Started Feb 09 03:54:23 AM UTC 25
Finished Feb 09 03:54:27 AM UTC 25
Peak memory 242232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654621106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3654621106
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1866212786
Short name T1291
Test name
Test status
Simulation time 152460569 ps
CPU time 1.87 seconds
Started Feb 09 03:54:24 AM UTC 25
Finished Feb 09 03:54:27 AM UTC 25
Peak memory 241664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866212786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1866212786
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2210083633
Short name T1292
Test name
Test status
Simulation time 42670785 ps
CPU time 1.67 seconds
Started Feb 09 03:54:25 AM UTC 25
Finished Feb 09 03:54:28 AM UTC 25
Peak memory 241436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210083633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2210083633
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1464445980
Short name T1294
Test name
Test status
Simulation time 45475715 ps
CPU time 2.16 seconds
Started Feb 09 03:54:25 AM UTC 25
Finished Feb 09 03:54:29 AM UTC 25
Peak memory 241968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464445980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1464445980
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2034349509
Short name T1297
Test name
Test status
Simulation time 62173059 ps
CPU time 2.19 seconds
Started Feb 09 03:54:26 AM UTC 25
Finished Feb 09 03:54:30 AM UTC 25
Peak memory 241752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034349509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2034349509
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.3874917429
Short name T1299
Test name
Test status
Simulation time 38724397 ps
CPU time 1.93 seconds
Started Feb 09 03:54:28 AM UTC 25
Finished Feb 09 03:54:31 AM UTC 25
Peak memory 241724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874917429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3874917429
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3513842527
Short name T1213
Test name
Test status
Simulation time 1936257638 ps
CPU time 7.34 seconds
Started Feb 09 03:53:09 AM UTC 25
Finished Feb 09 03:53:17 AM UTC 25
Peak memory 254968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513842527 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.3513842527
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2139212680
Short name T363
Test name
Test status
Simulation time 1969247763 ps
CPU time 9.47 seconds
Started Feb 09 03:53:08 AM UTC 25
Finished Feb 09 03:53:18 AM UTC 25
Peak memory 252996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139212680 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.2139212680
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2736245173
Short name T1208
Test name
Test status
Simulation time 68642940 ps
CPU time 2.19 seconds
Started Feb 09 03:53:08 AM UTC 25
Finished Feb 09 03:53:11 AM UTC 25
Peak memory 252948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736245173 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.2736245173
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2128046504
Short name T1211
Test name
Test status
Simulation time 225876861 ps
CPU time 4.52 seconds
Started Feb 09 03:53:10 AM UTC 25
Finished Feb 09 03:53:15 AM UTC 25
Peak memory 259364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21280
46504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_res
et.2128046504
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2279253190
Short name T372
Test name
Test status
Simulation time 161655003 ps
CPU time 2.25 seconds
Started Feb 09 03:53:08 AM UTC 25
Finished Feb 09 03:53:11 AM UTC 25
Peak memory 254984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279253190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2279253190
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.715993489
Short name T1204
Test name
Test status
Simulation time 36618561 ps
CPU time 2.18 seconds
Started Feb 09 03:53:03 AM UTC 25
Finished Feb 09 03:53:07 AM UTC 25
Peak memory 242064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715993489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.715993489
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.4272614552
Short name T1206
Test name
Test status
Simulation time 71374884 ps
CPU time 2.03 seconds
Started Feb 09 03:53:06 AM UTC 25
Finished Feb 09 03:53:09 AM UTC 25
Peak memory 241732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272614552 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.4272614552
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.850801355
Short name T1205
Test name
Test status
Simulation time 36249741 ps
CPU time 2.23 seconds
Started Feb 09 03:53:03 AM UTC 25
Finished Feb 09 03:53:07 AM UTC 25
Peak memory 241952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850801355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.850801355
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2840963785
Short name T373
Test name
Test status
Simulation time 94039343 ps
CPU time 4.48 seconds
Started Feb 09 03:53:10 AM UTC 25
Finished Feb 09 03:53:15 AM UTC 25
Peak memory 255044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840963785 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.2840963785
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3729889700
Short name T1209
Test name
Test status
Simulation time 1761669779 ps
CPU time 9.3 seconds
Started Feb 09 03:53:03 AM UTC 25
Finished Feb 09 03:53:14 AM UTC 25
Peak memory 252996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729889700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3729889700
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1120763568
Short name T434
Test name
Test status
Simulation time 627788464 ps
CPU time 16.19 seconds
Started Feb 09 03:53:03 AM UTC 25
Finished Feb 09 03:53:21 AM UTC 25
Peak memory 252936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120763568 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.1120763568
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.326987264
Short name T1300
Test name
Test status
Simulation time 71399935 ps
CPU time 2.13 seconds
Started Feb 09 03:54:28 AM UTC 25
Finished Feb 09 03:54:31 AM UTC 25
Peak memory 241776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326987264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.326987264
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1216702483
Short name T1298
Test name
Test status
Simulation time 37811467 ps
CPU time 1.52 seconds
Started Feb 09 03:54:28 AM UTC 25
Finished Feb 09 03:54:30 AM UTC 25
Peak memory 241664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216702483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1216702483
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2599450847
Short name T1301
Test name
Test status
Simulation time 70822944 ps
CPU time 2.31 seconds
Started Feb 09 03:54:28 AM UTC 25
Finished Feb 09 03:54:31 AM UTC 25
Peak memory 242700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599450847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2599450847
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.848346243
Short name T1302
Test name
Test status
Simulation time 72681876 ps
CPU time 2.21 seconds
Started Feb 09 03:54:29 AM UTC 25
Finished Feb 09 03:54:32 AM UTC 25
Peak memory 241944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848346243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.848346243
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2609084348
Short name T1306
Test name
Test status
Simulation time 542810401 ps
CPU time 3.62 seconds
Started Feb 09 03:54:29 AM UTC 25
Finished Feb 09 03:54:34 AM UTC 25
Peak memory 241788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609084348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2609084348
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.1226457745
Short name T1296
Test name
Test status
Simulation time 44194970 ps
CPU time 1.52 seconds
Started Feb 09 03:54:30 AM UTC 25
Finished Feb 09 03:54:32 AM UTC 25
Peak memory 241664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226457745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1226457745
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2190704558
Short name T1304
Test name
Test status
Simulation time 75193989 ps
CPU time 2.31 seconds
Started Feb 09 03:54:30 AM UTC 25
Finished Feb 09 03:54:33 AM UTC 25
Peak memory 241968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190704558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2190704558
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.195902679
Short name T1303
Test name
Test status
Simulation time 92036182 ps
CPU time 2.27 seconds
Started Feb 09 03:54:30 AM UTC 25
Finished Feb 09 03:54:33 AM UTC 25
Peak memory 241816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195902679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.195902679
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3448091772
Short name T1308
Test name
Test status
Simulation time 42292579 ps
CPU time 2.2 seconds
Started Feb 09 03:54:31 AM UTC 25
Finished Feb 09 03:54:34 AM UTC 25
Peak memory 241828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448091772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3448091772
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1994368864
Short name T1305
Test name
Test status
Simulation time 93086551 ps
CPU time 1.5 seconds
Started Feb 09 03:54:31 AM UTC 25
Finished Feb 09 03:54:34 AM UTC 25
Peak memory 241664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994368864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1994368864
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2897851438
Short name T361
Test name
Test status
Simulation time 156134623 ps
CPU time 5.42 seconds
Started Feb 09 03:53:16 AM UTC 25
Finished Feb 09 03:53:23 AM UTC 25
Peak memory 252948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897851438 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.2897851438
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2600207970
Short name T365
Test name
Test status
Simulation time 129649520 ps
CPU time 8.48 seconds
Started Feb 09 03:53:16 AM UTC 25
Finished Feb 09 03:53:26 AM UTC 25
Peak memory 252920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600207970 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.2600207970
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1210284834
Short name T359
Test name
Test status
Simulation time 71752107 ps
CPU time 2.91 seconds
Started Feb 09 03:53:15 AM UTC 25
Finished Feb 09 03:53:19 AM UTC 25
Peak memory 252932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210284834 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1210284834
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1749169219
Short name T1218
Test name
Test status
Simulation time 1121226151 ps
CPU time 5.2 seconds
Started Feb 09 03:53:18 AM UTC 25
Finished Feb 09 03:53:25 AM UTC 25
Peak memory 259236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17491
69219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_res
et.1749169219
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.972950091
Short name T360
Test name
Test status
Simulation time 172150718 ps
CPU time 3.08 seconds
Started Feb 09 03:53:16 AM UTC 25
Finished Feb 09 03:53:20 AM UTC 25
Peak memory 254968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972950091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.972950091
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.668111220
Short name T1210
Test name
Test status
Simulation time 77679853 ps
CPU time 2.12 seconds
Started Feb 09 03:53:12 AM UTC 25
Finished Feb 09 03:53:15 AM UTC 25
Peak memory 241868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668111220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.668111220
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1415047612
Short name T1214
Test name
Test status
Simulation time 537962486 ps
CPU time 2.15 seconds
Started Feb 09 03:53:14 AM UTC 25
Finished Feb 09 03:53:17 AM UTC 25
Peak memory 241548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415047612 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.1415047612
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2849372198
Short name T1212
Test name
Test status
Simulation time 73194062 ps
CPU time 2.1 seconds
Started Feb 09 03:53:13 AM UTC 25
Finished Feb 09 03:53:16 AM UTC 25
Peak memory 241904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849372198 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctr
l-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.2849372198
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1046289036
Short name T374
Test name
Test status
Simulation time 273766817 ps
CPU time 2.36 seconds
Started Feb 09 03:53:17 AM UTC 25
Finished Feb 09 03:53:21 AM UTC 25
Peak memory 255044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046289036 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.1046289036
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.503678248
Short name T1215
Test name
Test status
Simulation time 145443649 ps
CPU time 8.17 seconds
Started Feb 09 03:53:10 AM UTC 25
Finished Feb 09 03:53:19 AM UTC 25
Peak memory 259304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503678248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.503678248
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.571409601
Short name T435
Test name
Test status
Simulation time 1921526732 ps
CPU time 24.47 seconds
Started Feb 09 03:53:12 AM UTC 25
Finished Feb 09 03:53:38 AM UTC 25
Peak memory 253048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571409601 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.571409601
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1394292960
Short name T1307
Test name
Test status
Simulation time 52738145 ps
CPU time 1.92 seconds
Started Feb 09 03:54:31 AM UTC 25
Finished Feb 09 03:54:34 AM UTC 25
Peak memory 241104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394292960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1394292960
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1480757218
Short name T1309
Test name
Test status
Simulation time 87307251 ps
CPU time 1.76 seconds
Started Feb 09 03:54:32 AM UTC 25
Finished Feb 09 03:54:35 AM UTC 25
Peak memory 241664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480757218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1480757218
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.242453702
Short name T1310
Test name
Test status
Simulation time 545720090 ps
CPU time 2.43 seconds
Started Feb 09 03:54:32 AM UTC 25
Finished Feb 09 03:54:36 AM UTC 25
Peak memory 242280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242453702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.242453702
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.180139293
Short name T1311
Test name
Test status
Simulation time 82453702 ps
CPU time 2.1 seconds
Started Feb 09 03:54:33 AM UTC 25
Finished Feb 09 03:54:36 AM UTC 25
Peak memory 242176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180139293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.180139293
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2604264124
Short name T1312
Test name
Test status
Simulation time 523294226 ps
CPU time 3.11 seconds
Started Feb 09 03:54:33 AM UTC 25
Finished Feb 09 03:54:37 AM UTC 25
Peak memory 242572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604264124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2604264124
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.82467160
Short name T1314
Test name
Test status
Simulation time 66787022 ps
CPU time 2.34 seconds
Started Feb 09 03:54:35 AM UTC 25
Finished Feb 09 03:54:39 AM UTC 25
Peak memory 242156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82467160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.82467160
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.2300150049
Short name T1313
Test name
Test status
Simulation time 136746097 ps
CPU time 2.19 seconds
Started Feb 09 03:54:35 AM UTC 25
Finished Feb 09 03:54:39 AM UTC 25
Peak memory 241964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300150049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2300150049
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.873985477
Short name T1315
Test name
Test status
Simulation time 154746949 ps
CPU time 2.76 seconds
Started Feb 09 03:54:35 AM UTC 25
Finished Feb 09 03:54:39 AM UTC 25
Peak memory 242176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873985477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.873985477
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3147238775
Short name T1316
Test name
Test status
Simulation time 573103766 ps
CPU time 2.78 seconds
Started Feb 09 03:54:36 AM UTC 25
Finished Feb 09 03:54:39 AM UTC 25
Peak memory 241764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147238775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3147238775
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3146225445
Short name T1317
Test name
Test status
Simulation time 548473939 ps
CPU time 2.91 seconds
Started Feb 09 03:54:36 AM UTC 25
Finished Feb 09 03:54:40 AM UTC 25
Peak memory 242568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146225445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3146225445
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.580065506
Short name T1221
Test name
Test status
Simulation time 1705405077 ps
CPU time 4.76 seconds
Started Feb 09 03:53:22 AM UTC 25
Finished Feb 09 03:53:27 AM UTC 25
Peak memory 259004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58006
5506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.580065506
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.187429265
Short name T364
Test name
Test status
Simulation time 677702269 ps
CPU time 2.79 seconds
Started Feb 09 03:53:20 AM UTC 25
Finished Feb 09 03:53:23 AM UTC 25
Peak memory 252876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187429265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.187429265
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.2706607924
Short name T1217
Test name
Test status
Simulation time 72085410 ps
CPU time 2.42 seconds
Started Feb 09 03:53:20 AM UTC 25
Finished Feb 09 03:53:23 AM UTC 25
Peak memory 242560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706607924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2706607924
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2746916964
Short name T375
Test name
Test status
Simulation time 67360025 ps
CPU time 3.36 seconds
Started Feb 09 03:53:21 AM UTC 25
Finished Feb 09 03:53:25 AM UTC 25
Peak memory 252932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746916964 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.2746916964
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.356958682
Short name T1222
Test name
Test status
Simulation time 664597668 ps
CPU time 9.48 seconds
Started Feb 09 03:53:18 AM UTC 25
Finished Feb 09 03:53:29 AM UTC 25
Peak memory 252976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356958682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.356958682
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2134579781
Short name T1223
Test name
Test status
Simulation time 190288481 ps
CPU time 4.25 seconds
Started Feb 09 03:53:26 AM UTC 25
Finished Feb 09 03:53:31 AM UTC 25
Peak memory 259220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21345
79781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_res
et.2134579781
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4092512445
Short name T366
Test name
Test status
Simulation time 84007121 ps
CPU time 2.48 seconds
Started Feb 09 03:53:24 AM UTC 25
Finished Feb 09 03:53:27 AM UTC 25
Peak memory 252868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092512445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.4092512445
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.3808389535
Short name T1219
Test name
Test status
Simulation time 76221516 ps
CPU time 2.35 seconds
Started Feb 09 03:53:24 AM UTC 25
Finished Feb 09 03:53:27 AM UTC 25
Peak memory 242580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808389535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3808389535
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3284095047
Short name T376
Test name
Test status
Simulation time 1296310724 ps
CPU time 5.2 seconds
Started Feb 09 03:53:26 AM UTC 25
Finished Feb 09 03:53:32 AM UTC 25
Peak memory 252876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284095047 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3284095047
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1219846974
Short name T1220
Test name
Test status
Simulation time 57890849 ps
CPU time 4.71 seconds
Started Feb 09 03:53:22 AM UTC 25
Finished Feb 09 03:53:27 AM UTC 25
Peak memory 259040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219846974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1219846974
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1264494518
Short name T437
Test name
Test status
Simulation time 793632811 ps
CPU time 10.03 seconds
Started Feb 09 03:53:24 AM UTC 25
Finished Feb 09 03:53:35 AM UTC 25
Peak memory 257172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264494518 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.1264494518
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1297999692
Short name T1227
Test name
Test status
Simulation time 176932254 ps
CPU time 3.34 seconds
Started Feb 09 03:53:30 AM UTC 25
Finished Feb 09 03:53:35 AM UTC 25
Peak memory 257168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12979
99692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_res
et.1297999692
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.291093694
Short name T367
Test name
Test status
Simulation time 77821760 ps
CPU time 2.64 seconds
Started Feb 09 03:53:28 AM UTC 25
Finished Feb 09 03:53:32 AM UTC 25
Peak memory 253068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291093694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.291093694
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.2590990171
Short name T1224
Test name
Test status
Simulation time 42267293 ps
CPU time 2.3 seconds
Started Feb 09 03:53:28 AM UTC 25
Finished Feb 09 03:53:31 AM UTC 25
Peak memory 242176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590990171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2590990171
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2062204255
Short name T1226
Test name
Test status
Simulation time 157968141 ps
CPU time 4.27 seconds
Started Feb 09 03:53:28 AM UTC 25
Finished Feb 09 03:53:34 AM UTC 25
Peak memory 254916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062204255 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.2062204255
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2725777940
Short name T1225
Test name
Test status
Simulation time 107334039 ps
CPU time 4.65 seconds
Started Feb 09 03:53:27 AM UTC 25
Finished Feb 09 03:53:33 AM UTC 25
Peak memory 259200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725777940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2725777940
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3509531618
Short name T436
Test name
Test status
Simulation time 10357338778 ps
CPU time 14.57 seconds
Started Feb 09 03:53:28 AM UTC 25
Finished Feb 09 03:53:44 AM UTC 25
Peak memory 257220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509531618 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3509531618
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1095818882
Short name T1231
Test name
Test status
Simulation time 1075703500 ps
CPU time 4.17 seconds
Started Feb 09 03:53:35 AM UTC 25
Finished Feb 09 03:53:40 AM UTC 25
Peak memory 259348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10958
18882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_res
et.1095818882
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.525166553
Short name T368
Test name
Test status
Simulation time 146581677 ps
CPU time 2.51 seconds
Started Feb 09 03:53:33 AM UTC 25
Finished Feb 09 03:53:37 AM UTC 25
Peak memory 253132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525166553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t
est +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.525166553
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.412482974
Short name T1228
Test name
Test status
Simulation time 39616285 ps
CPU time 2.27 seconds
Started Feb 09 03:53:33 AM UTC 25
Finished Feb 09 03:53:37 AM UTC 25
Peak memory 241868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412482974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test
+UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.412482974
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3445378371
Short name T1229
Test name
Test status
Simulation time 139393800 ps
CPU time 3.03 seconds
Started Feb 09 03:53:33 AM UTC 25
Finished Feb 09 03:53:38 AM UTC 25
Peak memory 255044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445378371 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.3445378371
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3083152230
Short name T1230
Test name
Test status
Simulation time 170566495 ps
CPU time 4.87 seconds
Started Feb 09 03:53:32 AM UTC 25
Finished Feb 09 03:53:38 AM UTC 25
Peak memory 257216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083152230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3083152230
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1190843852
Short name T432
Test name
Test status
Simulation time 671359047 ps
CPU time 13.03 seconds
Started Feb 09 03:53:32 AM UTC 25
Finished Feb 09 03:53:47 AM UTC 25
Peak memory 257236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190843852 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.1190843852
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2330283822
Short name T1235
Test name
Test status
Simulation time 134506220 ps
CPU time 4.1 seconds
Started Feb 09 03:53:39 AM UTC 25
Finished Feb 09 03:53:44 AM UTC 25
Peak memory 259220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23302
83822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_res
et.2330283822
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2664608695
Short name T1232
Test name
Test status
Simulation time 544290222 ps
CPU time 2.72 seconds
Started Feb 09 03:53:38 AM UTC 25
Finished Feb 09 03:53:41 AM UTC 25
Peak memory 254912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664608695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2664608695
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.4281647974
Short name T1233
Test name
Test status
Simulation time 508826667 ps
CPU time 2.78 seconds
Started Feb 09 03:53:38 AM UTC 25
Finished Feb 09 03:53:42 AM UTC 25
Peak memory 242648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281647974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.4281647974
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3344532697
Short name T1234
Test name
Test status
Simulation time 153538122 ps
CPU time 3.28 seconds
Started Feb 09 03:53:39 AM UTC 25
Finished Feb 09 03:53:43 AM UTC 25
Peak memory 254916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344532697 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.3344532697
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1191810881
Short name T1216
Test name
Test status
Simulation time 158508556 ps
CPU time 6.2 seconds
Started Feb 09 03:53:36 AM UTC 25
Finished Feb 09 03:53:43 AM UTC 25
Peak memory 259136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191810881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1191810881
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1444881650
Short name T433
Test name
Test status
Simulation time 724097349 ps
CPU time 14.48 seconds
Started Feb 09 03:53:36 AM UTC 25
Finished Feb 09 03:53:51 AM UTC 25
Peak memory 257044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444881650 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.1444881650
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.2973872616
Short name T100
Test name
Test status
Simulation time 1367023539 ps
CPU time 17.09 seconds
Started Feb 09 04:11:41 AM UTC 25
Finished Feb 09 04:12:00 AM UTC 25
Peak memory 251112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973872616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2973872616
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.4090597726
Short name T94
Test name
Test status
Simulation time 8860900978 ps
CPU time 33.09 seconds
Started Feb 09 04:11:41 AM UTC 25
Finished Feb 09 04:12:16 AM UTC 25
Peak memory 253320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090597726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.4090597726
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.2917264224
Short name T131
Test name
Test status
Simulation time 6939130359 ps
CPU time 19.87 seconds
Started Feb 09 04:11:40 AM UTC 25
Finished Feb 09 04:12:01 AM UTC 25
Peak memory 251360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917264224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2917264224
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.3749672448
Short name T130
Test name
Test status
Simulation time 833001503 ps
CPU time 36.08 seconds
Started Feb 09 04:11:42 AM UTC 25
Finished Feb 09 04:12:20 AM UTC 25
Peak memory 257252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749672448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3749672448
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.2104768277
Short name T13
Test name
Test status
Simulation time 2817601823 ps
CPU time 17.95 seconds
Started Feb 09 04:11:40 AM UTC 25
Finished Feb 09 04:11:59 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104768277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2104768277
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.3879644639
Short name T5
Test name
Test status
Simulation time 1040669997 ps
CPU time 10.6 seconds
Started Feb 09 04:11:42 AM UTC 25
Finished Feb 09 04:11:54 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879644639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3879644639
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.3243031740
Short name T4
Test name
Test status
Simulation time 571660309 ps
CPU time 9.32 seconds
Started Feb 09 04:11:40 AM UTC 25
Finished Feb 09 04:11:51 AM UTC 25
Peak memory 251180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243031740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3243031740
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3951596307
Short name T388
Test name
Test status
Simulation time 38439665795 ps
CPU time 1246.39 seconds
Started Feb 09 04:11:42 AM UTC 25
Finished Feb 09 04:32:44 AM UTC 25
Peak memory 444096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3951596307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_al
l_with_rand_reset.3951596307
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.3920141150
Short name T6
Test name
Test status
Simulation time 508683019 ps
CPU time 10.82 seconds
Started Feb 09 04:11:42 AM UTC 25
Finished Feb 09 04:11:55 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920141150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3920141150
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1434838460
Short name T17
Test name
Test status
Simulation time 301594218 ps
CPU time 3.69 seconds
Started Feb 09 04:12:08 AM UTC 25
Finished Feb 09 04:12:13 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434838460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1434838460
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.1923932026
Short name T103
Test name
Test status
Simulation time 359124023 ps
CPU time 9.13 seconds
Started Feb 09 04:11:56 AM UTC 25
Finished Feb 09 04:12:06 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923932026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1923932026
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.4198120878
Short name T7
Test name
Test status
Simulation time 936973823 ps
CPU time 17.91 seconds
Started Feb 09 04:11:58 AM UTC 25
Finished Feb 09 04:12:17 AM UTC 25
Peak memory 251396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198120878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.4198120878
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.4019182897
Short name T133
Test name
Test status
Simulation time 257787545 ps
CPU time 6 seconds
Started Feb 09 04:12:01 AM UTC 25
Finished Feb 09 04:12:08 AM UTC 25
Peak memory 257340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019182897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.4019182897
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.1585437377
Short name T127
Test name
Test status
Simulation time 1488096426 ps
CPU time 44.8 seconds
Started Feb 09 04:12:01 AM UTC 25
Finished Feb 09 04:12:48 AM UTC 25
Peak memory 253160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585437377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1585437377
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.1726825469
Short name T132
Test name
Test status
Simulation time 324613915 ps
CPU time 5.95 seconds
Started Feb 09 04:11:57 AM UTC 25
Finished Feb 09 04:12:04 AM UTC 25
Peak memory 250776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726825469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1726825469
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.1362397603
Short name T95
Test name
Test status
Simulation time 1119826950 ps
CPU time 19.32 seconds
Started Feb 09 04:11:56 AM UTC 25
Finished Feb 09 04:12:16 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362397603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1362397603
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1961878789
Short name T135
Test name
Test status
Simulation time 156023062 ps
CPU time 6.48 seconds
Started Feb 09 04:12:02 AM UTC 25
Finished Feb 09 04:12:10 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961878789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1961878789
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.1806196909
Short name T134
Test name
Test status
Simulation time 5103130646 ps
CPU time 15.46 seconds
Started Feb 09 04:11:52 AM UTC 25
Finished Feb 09 04:12:09 AM UTC 25
Peak memory 251244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806196909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1806196909
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.1642310420
Short name T18
Test name
Test status
Simulation time 304757593 ps
CPU time 12.95 seconds
Started Feb 09 04:12:03 AM UTC 25
Finished Feb 09 04:12:18 AM UTC 25
Peak memory 251224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642310420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1642310420
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.2098408533
Short name T525
Test name
Test status
Simulation time 66320397 ps
CPU time 2.69 seconds
Started Feb 09 04:15:30 AM UTC 25
Finished Feb 09 04:15:34 AM UTC 25
Peak memory 251032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098408533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2098408533
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.30778116
Short name T425
Test name
Test status
Simulation time 951496834 ps
CPU time 18.47 seconds
Started Feb 09 04:15:18 AM UTC 25
Finished Feb 09 04:15:38 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30778116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.30778116
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.4091136616
Short name T482
Test name
Test status
Simulation time 11781944234 ps
CPU time 56.99 seconds
Started Feb 09 04:15:18 AM UTC 25
Finished Feb 09 04:16:17 AM UTC 25
Peak memory 257308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091136616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.4091136616
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1285862436
Short name T196
Test name
Test status
Simulation time 6474635418 ps
CPU time 19.86 seconds
Started Feb 09 04:15:20 AM UTC 25
Finished Feb 09 04:15:42 AM UTC 25
Peak memory 251260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285862436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1285862436
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.2480057407
Short name T494
Test name
Test status
Simulation time 1174854279 ps
CPU time 22.63 seconds
Started Feb 09 04:15:21 AM UTC 25
Finished Feb 09 04:15:45 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480057407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.2480057407
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.3427821726
Short name T108
Test name
Test status
Simulation time 564307260 ps
CPU time 15.85 seconds
Started Feb 09 04:15:16 AM UTC 25
Finished Feb 09 04:15:34 AM UTC 25
Peak memory 250904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427821726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3427821726
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.3545908634
Short name T414
Test name
Test status
Simulation time 304371382 ps
CPU time 7 seconds
Started Feb 09 04:15:16 AM UTC 25
Finished Feb 09 04:15:25 AM UTC 25
Peak memory 253132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545908634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3545908634
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.3870039000
Short name T413
Test name
Test status
Simulation time 158849140 ps
CPU time 5.97 seconds
Started Feb 09 04:15:12 AM UTC 25
Finished Feb 09 04:15:19 AM UTC 25
Peak memory 257256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870039000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3870039000
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.932014116
Short name T288
Test name
Test status
Simulation time 184829645655 ps
CPU time 1951.78 seconds
Started Feb 09 04:15:27 AM UTC 25
Finished Feb 09 04:48:19 AM UTC 25
Peak memory 470528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=932014116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_al
l_with_rand_reset.932014116
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.2256600340
Short name T457
Test name
Test status
Simulation time 1174532399 ps
CPU time 11.07 seconds
Started Feb 09 04:15:26 AM UTC 25
Finished Feb 09 04:15:38 AM UTC 25
Peak memory 253172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256600340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2256600340
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.1666525524
Short name T915
Test name
Test status
Simulation time 228435220 ps
CPU time 5.2 seconds
Started Feb 09 04:45:16 AM UTC 25
Finished Feb 09 04:45:22 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666525524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1666525524
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1117610836
Short name T916
Test name
Test status
Simulation time 2561414000 ps
CPU time 7.94 seconds
Started Feb 09 04:45:17 AM UTC 25
Finished Feb 09 04:45:26 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117610836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1117610836
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.3194736700
Short name T918
Test name
Test status
Simulation time 149400230 ps
CPU time 5.63 seconds
Started Feb 09 04:45:23 AM UTC 25
Finished Feb 09 04:45:30 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194736700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3194736700
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.3984311734
Short name T75
Test name
Test status
Simulation time 229168088 ps
CPU time 6.99 seconds
Started Feb 09 04:45:29 AM UTC 25
Finished Feb 09 04:45:37 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984311734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3984311734
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.302557548
Short name T880
Test name
Test status
Simulation time 394116982 ps
CPU time 4.77 seconds
Started Feb 09 04:45:32 AM UTC 25
Finished Feb 09 04:45:38 AM UTC 25
Peak memory 250976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302557548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.302557548
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.202077175
Short name T821
Test name
Test status
Simulation time 219904422 ps
CPU time 6.49 seconds
Started Feb 09 04:45:32 AM UTC 25
Finished Feb 09 04:45:40 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202077175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.202077175
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.2533793760
Short name T920
Test name
Test status
Simulation time 2524039935 ps
CPU time 24.52 seconds
Started Feb 09 04:45:38 AM UTC 25
Finished Feb 09 04:46:04 AM UTC 25
Peak memory 257088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533793760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2533793760
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.1104197651
Short name T919
Test name
Test status
Simulation time 909092039 ps
CPU time 7.53 seconds
Started Feb 09 04:45:41 AM UTC 25
Finished Feb 09 04:45:50 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104197651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1104197651
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.1677803299
Short name T82
Test name
Test status
Simulation time 208061447 ps
CPU time 4.56 seconds
Started Feb 09 04:45:46 AM UTC 25
Finished Feb 09 04:45:52 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677803299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1677803299
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.220393384
Short name T330
Test name
Test status
Simulation time 670467588 ps
CPU time 26 seconds
Started Feb 09 04:45:51 AM UTC 25
Finished Feb 09 04:46:19 AM UTC 25
Peak memory 251288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220393384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.220393384
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.3782996719
Short name T921
Test name
Test status
Simulation time 226570681 ps
CPU time 8.17 seconds
Started Feb 09 04:46:02 AM UTC 25
Finished Feb 09 04:46:12 AM UTC 25
Peak memory 253112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782996719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3782996719
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.3071133797
Short name T332
Test name
Test status
Simulation time 366974316 ps
CPU time 7.56 seconds
Started Feb 09 04:46:12 AM UTC 25
Finished Feb 09 04:46:20 AM UTC 25
Peak memory 253300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071133797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3071133797
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.301217351
Short name T331
Test name
Test status
Simulation time 135582126 ps
CPU time 5.46 seconds
Started Feb 09 04:46:13 AM UTC 25
Finished Feb 09 04:46:19 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301217351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.301217351
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.128556609
Short name T337
Test name
Test status
Simulation time 2187159172 ps
CPU time 18.11 seconds
Started Feb 09 04:46:14 AM UTC 25
Finished Feb 09 04:46:33 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128556609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.128556609
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.3056931888
Short name T334
Test name
Test status
Simulation time 155220588 ps
CPU time 4.99 seconds
Started Feb 09 04:46:17 AM UTC 25
Finished Feb 09 04:46:23 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056931888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3056931888
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2095213759
Short name T924
Test name
Test status
Simulation time 1354846621 ps
CPU time 16.74 seconds
Started Feb 09 04:46:21 AM UTC 25
Finished Feb 09 04:46:39 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095213759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2095213759
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.4183803383
Short name T529
Test name
Test status
Simulation time 181155831 ps
CPU time 2.82 seconds
Started Feb 09 04:15:52 AM UTC 25
Finished Feb 09 04:15:55 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183803383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.4183803383
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2186710807
Short name T145
Test name
Test status
Simulation time 572708614 ps
CPU time 17.23 seconds
Started Feb 09 04:15:41 AM UTC 25
Finished Feb 09 04:16:00 AM UTC 25
Peak memory 253436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186710807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2186710807
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.158008716
Short name T427
Test name
Test status
Simulation time 1088481923 ps
CPU time 14.71 seconds
Started Feb 09 04:15:39 AM UTC 25
Finished Feb 09 04:15:55 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158008716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.158008716
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.4069944913
Short name T461
Test name
Test status
Simulation time 1675013534 ps
CPU time 22.49 seconds
Started Feb 09 04:15:39 AM UTC 25
Finished Feb 09 04:16:03 AM UTC 25
Peak memory 257312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069944913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.4069944913
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.1757783756
Short name T543
Test name
Test status
Simulation time 27417604940 ps
CPU time 60.91 seconds
Started Feb 09 04:15:41 AM UTC 25
Finished Feb 09 04:16:44 AM UTC 25
Peak memory 273792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757783756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1757783756
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.4281671738
Short name T532
Test name
Test status
Simulation time 1110091813 ps
CPU time 21.54 seconds
Started Feb 09 04:15:43 AM UTC 25
Finished Feb 09 04:16:06 AM UTC 25
Peak memory 253348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281671738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.4281671738
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.2261880654
Short name T285
Test name
Test status
Simulation time 1254280078 ps
CPU time 23.65 seconds
Started Feb 09 04:15:35 AM UTC 25
Finished Feb 09 04:16:00 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261880654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2261880654
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3593368442
Short name T528
Test name
Test status
Simulation time 3971216675 ps
CPU time 16.93 seconds
Started Feb 09 04:15:35 AM UTC 25
Finished Feb 09 04:15:54 AM UTC 25
Peak memory 257504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593368442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3593368442
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.680356440
Short name T451
Test name
Test status
Simulation time 539232892 ps
CPU time 6.12 seconds
Started Feb 09 04:15:43 AM UTC 25
Finished Feb 09 04:15:50 AM UTC 25
Peak memory 257192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680356440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.680356440
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.3475360772
Short name T527
Test name
Test status
Simulation time 651897361 ps
CPU time 16.76 seconds
Started Feb 09 04:15:33 AM UTC 25
Finished Feb 09 04:15:51 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475360772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3475360772
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1507818924
Short name T292
Test name
Test status
Simulation time 392547127583 ps
CPU time 882.11 seconds
Started Feb 09 04:15:47 AM UTC 25
Finished Feb 09 04:30:40 AM UTC 25
Peak memory 271868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1507818924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_a
ll_with_rand_reset.1507818924
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.23151674
Short name T530
Test name
Test status
Simulation time 960405513 ps
CPU time 11.89 seconds
Started Feb 09 04:15:43 AM UTC 25
Finished Feb 09 04:15:56 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23151674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.23151674
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.209416362
Short name T335
Test name
Test status
Simulation time 647291497 ps
CPU time 6.98 seconds
Started Feb 09 04:46:21 AM UTC 25
Finished Feb 09 04:46:29 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209416362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.209416362
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.3175516525
Short name T336
Test name
Test status
Simulation time 280842810 ps
CPU time 5.37 seconds
Started Feb 09 04:46:24 AM UTC 25
Finished Feb 09 04:46:30 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175516525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3175516525
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.2290993798
Short name T925
Test name
Test status
Simulation time 229768465 ps
CPU time 16.2 seconds
Started Feb 09 04:46:24 AM UTC 25
Finished Feb 09 04:46:41 AM UTC 25
Peak memory 251288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290993798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2290993798
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.3873916702
Short name T923
Test name
Test status
Simulation time 432518749 ps
CPU time 5.98 seconds
Started Feb 09 04:46:30 AM UTC 25
Finished Feb 09 04:46:37 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873916702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3873916702
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.138888976
Short name T926
Test name
Test status
Simulation time 458255408 ps
CPU time 9.5 seconds
Started Feb 09 04:46:31 AM UTC 25
Finished Feb 09 04:46:42 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138888976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.138888976
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.2393076534
Short name T202
Test name
Test status
Simulation time 266770401 ps
CPU time 3.41 seconds
Started Feb 09 04:46:32 AM UTC 25
Finished Feb 09 04:46:37 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393076534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2393076534
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.77323583
Short name T927
Test name
Test status
Simulation time 314830509 ps
CPU time 9.04 seconds
Started Feb 09 04:46:34 AM UTC 25
Finished Feb 09 04:46:45 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77323583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.77323583
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.4089689116
Short name T929
Test name
Test status
Simulation time 129313258 ps
CPU time 6.93 seconds
Started Feb 09 04:46:38 AM UTC 25
Finished Feb 09 04:46:46 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089689116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4089689116
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.2068961589
Short name T928
Test name
Test status
Simulation time 156595516 ps
CPU time 4.36 seconds
Started Feb 09 04:46:40 AM UTC 25
Finished Feb 09 04:46:46 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068961589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2068961589
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.3832148557
Short name T930
Test name
Test status
Simulation time 599439535 ps
CPU time 7.34 seconds
Started Feb 09 04:46:43 AM UTC 25
Finished Feb 09 04:46:51 AM UTC 25
Peak memory 250996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832148557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3832148557
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.2807477376
Short name T941
Test name
Test status
Simulation time 640302026 ps
CPU time 23.77 seconds
Started Feb 09 04:46:46 AM UTC 25
Finished Feb 09 04:47:12 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807477376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2807477376
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.2836902254
Short name T931
Test name
Test status
Simulation time 169060948 ps
CPU time 5.81 seconds
Started Feb 09 04:46:46 AM UTC 25
Finished Feb 09 04:46:53 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836902254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2836902254
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.4023588925
Short name T946
Test name
Test status
Simulation time 6937709925 ps
CPU time 27.26 seconds
Started Feb 09 04:46:46 AM UTC 25
Finished Feb 09 04:47:15 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023588925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.4023588925
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.2885984867
Short name T932
Test name
Test status
Simulation time 223043754 ps
CPU time 5.81 seconds
Started Feb 09 04:46:46 AM UTC 25
Finished Feb 09 04:46:53 AM UTC 25
Peak memory 251200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885984867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2885984867
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.136102770
Short name T936
Test name
Test status
Simulation time 500742707 ps
CPU time 5.83 seconds
Started Feb 09 04:46:53 AM UTC 25
Finished Feb 09 04:47:00 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136102770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.136102770
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.4078954195
Short name T935
Test name
Test status
Simulation time 322584847 ps
CPU time 5.08 seconds
Started Feb 09 04:46:53 AM UTC 25
Finished Feb 09 04:46:59 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078954195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.4078954195
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.2663896306
Short name T938
Test name
Test status
Simulation time 456557857 ps
CPU time 6.83 seconds
Started Feb 09 04:46:54 AM UTC 25
Finished Feb 09 04:47:02 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663896306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2663896306
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.335989986
Short name T534
Test name
Test status
Simulation time 1088937068 ps
CPU time 4.87 seconds
Started Feb 09 04:16:11 AM UTC 25
Finished Feb 09 04:16:17 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335989986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.335989986
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.88756068
Short name T71
Test name
Test status
Simulation time 536144087 ps
CPU time 13.8 seconds
Started Feb 09 04:16:01 AM UTC 25
Finished Feb 09 04:16:16 AM UTC 25
Peak memory 251188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88756068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.88756068
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.212439463
Short name T426
Test name
Test status
Simulation time 3116944847 ps
CPU time 28.51 seconds
Started Feb 09 04:15:58 AM UTC 25
Finished Feb 09 04:16:28 AM UTC 25
Peak memory 253248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212439463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.212439463
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.944462635
Short name T540
Test name
Test status
Simulation time 3355216901 ps
CPU time 34.7 seconds
Started Feb 09 04:15:58 AM UTC 25
Finished Feb 09 04:16:35 AM UTC 25
Peak memory 251268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944462635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.944462635
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1378251796
Short name T41
Test name
Test status
Simulation time 355070446 ps
CPU time 6.77 seconds
Started Feb 09 04:15:55 AM UTC 25
Finished Feb 09 04:16:03 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378251796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1378251796
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.2807078891
Short name T189
Test name
Test status
Simulation time 885461229 ps
CPU time 38.56 seconds
Started Feb 09 04:16:02 AM UTC 25
Finished Feb 09 04:16:42 AM UTC 25
Peak memory 255200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807078891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2807078891
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.1025019296
Short name T521
Test name
Test status
Simulation time 108102438 ps
CPU time 5.77 seconds
Started Feb 09 04:15:57 AM UTC 25
Finished Feb 09 04:16:04 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025019296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1025019296
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2893856241
Short name T533
Test name
Test status
Simulation time 649151017 ps
CPU time 16.86 seconds
Started Feb 09 04:15:57 AM UTC 25
Finished Feb 09 04:16:15 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893856241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2893856241
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1432869519
Short name T445
Test name
Test status
Simulation time 311686353 ps
CPU time 14.25 seconds
Started Feb 09 04:16:04 AM UTC 25
Finished Feb 09 04:16:19 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432869519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1432869519
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.2588696956
Short name T531
Test name
Test status
Simulation time 594742751 ps
CPU time 11.12 seconds
Started Feb 09 04:15:53 AM UTC 25
Finished Feb 09 04:16:05 AM UTC 25
Peak memory 257512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588696956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2588696956
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.3681023484
Short name T1189
Test name
Test status
Simulation time 436977220528 ps
CPU time 4167.98 seconds
Started Feb 09 04:16:08 AM UTC 25
Finished Feb 09 05:26:17 AM UTC 25
Peak memory 284064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681023484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.3681023484
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.4000533735
Short name T537
Test name
Test status
Simulation time 13501919243 ps
CPU time 23.81 seconds
Started Feb 09 04:16:05 AM UTC 25
Finished Feb 09 04:16:30 AM UTC 25
Peak memory 253248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000533735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.4000533735
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.2784726466
Short name T937
Test name
Test status
Simulation time 606517777 ps
CPU time 5.57 seconds
Started Feb 09 04:46:54 AM UTC 25
Finished Feb 09 04:47:01 AM UTC 25
Peak memory 253144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784726466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2784726466
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.373520350
Short name T944
Test name
Test status
Simulation time 3502227126 ps
CPU time 9.69 seconds
Started Feb 09 04:47:02 AM UTC 25
Finished Feb 09 04:47:13 AM UTC 25
Peak memory 248944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373520350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.373520350
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.1156116471
Short name T940
Test name
Test status
Simulation time 267558450 ps
CPU time 5.62 seconds
Started Feb 09 04:47:02 AM UTC 25
Finished Feb 09 04:47:09 AM UTC 25
Peak memory 251432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156116471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1156116471
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.2463073181
Short name T942
Test name
Test status
Simulation time 353424581 ps
CPU time 8.79 seconds
Started Feb 09 04:47:02 AM UTC 25
Finished Feb 09 04:47:12 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463073181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2463073181
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.1310374759
Short name T939
Test name
Test status
Simulation time 115958332 ps
CPU time 5.21 seconds
Started Feb 09 04:47:03 AM UTC 25
Finished Feb 09 04:47:09 AM UTC 25
Peak memory 253368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310374759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1310374759
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.8505363
Short name T947
Test name
Test status
Simulation time 2913134235 ps
CPU time 12.19 seconds
Started Feb 09 04:47:03 AM UTC 25
Finished Feb 09 04:47:16 AM UTC 25
Peak memory 251248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8505363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl
_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.8505363
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.1110438932
Short name T943
Test name
Test status
Simulation time 2031861525 ps
CPU time 7.72 seconds
Started Feb 09 04:47:04 AM UTC 25
Finished Feb 09 04:47:13 AM UTC 25
Peak memory 253432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110438932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1110438932
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.2778380783
Short name T955
Test name
Test status
Simulation time 698449657 ps
CPU time 20.53 seconds
Started Feb 09 04:47:08 AM UTC 25
Finished Feb 09 04:47:30 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778380783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2778380783
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.3035244172
Short name T945
Test name
Test status
Simulation time 197307501 ps
CPU time 3.89 seconds
Started Feb 09 04:47:10 AM UTC 25
Finished Feb 09 04:47:15 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035244172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3035244172
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.3792541574
Short name T948
Test name
Test status
Simulation time 229356426 ps
CPU time 5.26 seconds
Started Feb 09 04:47:13 AM UTC 25
Finished Feb 09 04:47:19 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792541574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3792541574
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.726257008
Short name T169
Test name
Test status
Simulation time 1538001393 ps
CPU time 25.66 seconds
Started Feb 09 04:47:14 AM UTC 25
Finished Feb 09 04:47:41 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726257008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.726257008
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.3424029263
Short name T949
Test name
Test status
Simulation time 2460159039 ps
CPU time 7.38 seconds
Started Feb 09 04:47:14 AM UTC 25
Finished Feb 09 04:47:23 AM UTC 25
Peak memory 253412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424029263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3424029263
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.1759984261
Short name T952
Test name
Test status
Simulation time 4310385878 ps
CPU time 10.57 seconds
Started Feb 09 04:47:14 AM UTC 25
Finished Feb 09 04:47:26 AM UTC 25
Peak memory 251188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759984261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1759984261
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.1916648051
Short name T950
Test name
Test status
Simulation time 461802235 ps
CPU time 6.94 seconds
Started Feb 09 04:47:17 AM UTC 25
Finished Feb 09 04:47:25 AM UTC 25
Peak memory 253184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916648051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1916648051
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.476606822
Short name T956
Test name
Test status
Simulation time 424079114 ps
CPU time 12.45 seconds
Started Feb 09 04:47:17 AM UTC 25
Finished Feb 09 04:47:30 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476606822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.476606822
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.2393660345
Short name T951
Test name
Test status
Simulation time 1758832425 ps
CPU time 7.36 seconds
Started Feb 09 04:47:17 AM UTC 25
Finished Feb 09 04:47:25 AM UTC 25
Peak memory 253248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393660345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2393660345
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.333428347
Short name T954
Test name
Test status
Simulation time 239129197 ps
CPU time 8.5 seconds
Started Feb 09 04:47:18 AM UTC 25
Finished Feb 09 04:47:28 AM UTC 25
Peak memory 251032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333428347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.333428347
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.65217641
Short name T953
Test name
Test status
Simulation time 183567587 ps
CPU time 6.02 seconds
Started Feb 09 04:47:20 AM UTC 25
Finished Feb 09 04:47:27 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65217641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.65217641
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.1580669576
Short name T957
Test name
Test status
Simulation time 253455518 ps
CPU time 8.11 seconds
Started Feb 09 04:47:23 AM UTC 25
Finished Feb 09 04:47:33 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580669576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1580669576
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1484190589
Short name T538
Test name
Test status
Simulation time 197079571 ps
CPU time 2.8 seconds
Started Feb 09 04:16:29 AM UTC 25
Finished Feb 09 04:16:33 AM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484190589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1484190589
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.133376509
Short name T542
Test name
Test status
Simulation time 973517297 ps
CPU time 19.83 seconds
Started Feb 09 04:16:20 AM UTC 25
Finished Feb 09 04:16:41 AM UTC 25
Peak memory 251120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133376509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.133376509
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.2073096814
Short name T429
Test name
Test status
Simulation time 4345428056 ps
CPU time 22.47 seconds
Started Feb 09 04:16:18 AM UTC 25
Finished Feb 09 04:16:41 AM UTC 25
Peak memory 251232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073096814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2073096814
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.2338997726
Short name T539
Test name
Test status
Simulation time 1654670027 ps
CPU time 13.87 seconds
Started Feb 09 04:16:18 AM UTC 25
Finished Feb 09 04:16:33 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338997726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2338997726
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.9371992
Short name T224
Test name
Test status
Simulation time 2040361710 ps
CPU time 8.29 seconds
Started Feb 09 04:16:16 AM UTC 25
Finished Feb 09 04:16:26 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9371992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl
_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.9371992
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.3373434919
Short name T280
Test name
Test status
Simulation time 7576195508 ps
CPU time 23.28 seconds
Started Feb 09 04:16:25 AM UTC 25
Finished Feb 09 04:16:49 AM UTC 25
Peak memory 253408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373434919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3373434919
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.3316633559
Short name T536
Test name
Test status
Simulation time 1852401305 ps
CPU time 7.24 seconds
Started Feb 09 04:16:16 AM UTC 25
Finished Feb 09 04:16:25 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316633559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3316633559
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.2051753389
Short name T466
Test name
Test status
Simulation time 491627074 ps
CPU time 14.27 seconds
Started Feb 09 04:16:16 AM UTC 25
Finished Feb 09 04:16:32 AM UTC 25
Peak memory 257436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051753389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2051753389
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.2116375153
Short name T535
Test name
Test status
Simulation time 354384029 ps
CPU time 7.2 seconds
Started Feb 09 04:16:16 AM UTC 25
Finished Feb 09 04:16:25 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116375153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2116375153
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1851318669
Short name T20
Test name
Test status
Simulation time 286243184976 ps
CPU time 591.11 seconds
Started Feb 09 04:16:26 AM UTC 25
Finished Feb 09 04:26:24 AM UTC 25
Peak memory 310776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1851318669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_a
ll_with_rand_reset.1851318669
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.185765678
Short name T91
Test name
Test status
Simulation time 301911384 ps
CPU time 5.06 seconds
Started Feb 09 04:47:26 AM UTC 25
Finished Feb 09 04:47:32 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185765678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.185765678
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2903175476
Short name T961
Test name
Test status
Simulation time 375020931 ps
CPU time 11.89 seconds
Started Feb 09 04:47:27 AM UTC 25
Finished Feb 09 04:47:40 AM UTC 25
Peak memory 251064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903175476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2903175476
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.4061331798
Short name T958
Test name
Test status
Simulation time 307768526 ps
CPU time 6.35 seconds
Started Feb 09 04:47:27 AM UTC 25
Finished Feb 09 04:47:34 AM UTC 25
Peak memory 253368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061331798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.4061331798
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.2906190240
Short name T959
Test name
Test status
Simulation time 450103438 ps
CPU time 6.55 seconds
Started Feb 09 04:47:28 AM UTC 25
Finished Feb 09 04:47:36 AM UTC 25
Peak memory 253144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906190240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.2906190240
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.4073906740
Short name T89
Test name
Test status
Simulation time 708738841 ps
CPU time 7.39 seconds
Started Feb 09 04:47:29 AM UTC 25
Finished Feb 09 04:47:38 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073906740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.4073906740
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.3412221646
Short name T963
Test name
Test status
Simulation time 594140145 ps
CPU time 10.13 seconds
Started Feb 09 04:47:32 AM UTC 25
Finished Feb 09 04:47:43 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412221646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3412221646
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.3148374880
Short name T960
Test name
Test status
Simulation time 449193714 ps
CPU time 6.89 seconds
Started Feb 09 04:47:32 AM UTC 25
Finished Feb 09 04:47:40 AM UTC 25
Peak memory 253368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148374880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3148374880
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.312844854
Short name T964
Test name
Test status
Simulation time 237787170 ps
CPU time 10.25 seconds
Started Feb 09 04:47:33 AM UTC 25
Finished Feb 09 04:47:44 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312844854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.312844854
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.4035110567
Short name T962
Test name
Test status
Simulation time 156450305 ps
CPU time 5.1 seconds
Started Feb 09 04:47:34 AM UTC 25
Finished Feb 09 04:47:40 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035110567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.4035110567
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.2584682192
Short name T933
Test name
Test status
Simulation time 303645126 ps
CPU time 22.06 seconds
Started Feb 09 04:47:35 AM UTC 25
Finished Feb 09 04:47:58 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584682192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2584682192
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.1358997937
Short name T965
Test name
Test status
Simulation time 2523317559 ps
CPU time 7.75 seconds
Started Feb 09 04:47:37 AM UTC 25
Finished Feb 09 04:47:46 AM UTC 25
Peak memory 253252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358997937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1358997937
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.3047749888
Short name T967
Test name
Test status
Simulation time 200490408 ps
CPU time 7.83 seconds
Started Feb 09 04:47:39 AM UTC 25
Finished Feb 09 04:47:48 AM UTC 25
Peak memory 251068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047749888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3047749888
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.744515601
Short name T389
Test name
Test status
Simulation time 304293868 ps
CPU time 10.38 seconds
Started Feb 09 04:47:41 AM UTC 25
Finished Feb 09 04:47:52 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744515601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.744515601
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.181855191
Short name T76
Test name
Test status
Simulation time 269079149 ps
CPU time 5.58 seconds
Started Feb 09 04:47:41 AM UTC 25
Finished Feb 09 04:47:48 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181855191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.181855191
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.2250605328
Short name T979
Test name
Test status
Simulation time 2493268237 ps
CPU time 27.3 seconds
Started Feb 09 04:47:42 AM UTC 25
Finished Feb 09 04:48:11 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250605328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2250605328
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.3464799094
Short name T968
Test name
Test status
Simulation time 1343817744 ps
CPU time 4.99 seconds
Started Feb 09 04:47:44 AM UTC 25
Finished Feb 09 04:47:50 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464799094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3464799094
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.1899105612
Short name T981
Test name
Test status
Simulation time 2525053592 ps
CPU time 26.05 seconds
Started Feb 09 04:47:45 AM UTC 25
Finished Feb 09 04:48:12 AM UTC 25
Peak memory 253172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899105612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1899105612
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.2450095299
Short name T969
Test name
Test status
Simulation time 150364696 ps
CPU time 5.91 seconds
Started Feb 09 04:47:47 AM UTC 25
Finished Feb 09 04:47:54 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450095299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2450095299
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.2014497558
Short name T980
Test name
Test status
Simulation time 894074575 ps
CPU time 22.44 seconds
Started Feb 09 04:47:48 AM UTC 25
Finished Feb 09 04:48:12 AM UTC 25
Peak memory 251316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014497558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2014497558
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.2448341049
Short name T326
Test name
Test status
Simulation time 80410738 ps
CPU time 3.03 seconds
Started Feb 09 04:16:46 AM UTC 25
Finished Feb 09 04:16:51 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448341049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2448341049
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.1189418868
Short name T52
Test name
Test status
Simulation time 4490171311 ps
CPU time 16.13 seconds
Started Feb 09 04:16:36 AM UTC 25
Finished Feb 09 04:16:53 AM UTC 25
Peak memory 253308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189418868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1189418868
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.140818986
Short name T476
Test name
Test status
Simulation time 1653669129 ps
CPU time 43.74 seconds
Started Feb 09 04:16:34 AM UTC 25
Finished Feb 09 04:17:20 AM UTC 25
Peak memory 259320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140818986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.140818986
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.3487453728
Short name T210
Test name
Test status
Simulation time 7187356344 ps
CPU time 22.61 seconds
Started Feb 09 04:16:34 AM UTC 25
Finished Feb 09 04:16:58 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487453728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.3487453728
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.2144915636
Short name T184
Test name
Test status
Simulation time 290764510 ps
CPU time 4.94 seconds
Started Feb 09 04:16:30 AM UTC 25
Finished Feb 09 04:16:36 AM UTC 25
Peak memory 251224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144915636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2144915636
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1776932828
Short name T190
Test name
Test status
Simulation time 3570633815 ps
CPU time 39 seconds
Started Feb 09 04:16:38 AM UTC 25
Finished Feb 09 04:17:18 AM UTC 25
Peak memory 257340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776932828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1776932828
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.2793700294
Short name T495
Test name
Test status
Simulation time 27555480597 ps
CPU time 97.66 seconds
Started Feb 09 04:16:42 AM UTC 25
Finished Feb 09 04:18:22 AM UTC 25
Peak memory 253432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793700294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2793700294
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.4194379545
Short name T303
Test name
Test status
Simulation time 588067423 ps
CPU time 11.23 seconds
Started Feb 09 04:16:34 AM UTC 25
Finished Feb 09 04:16:47 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194379545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.4194379545
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.3038800341
Short name T296
Test name
Test status
Simulation time 2663369615 ps
CPU time 10.86 seconds
Started Feb 09 04:16:34 AM UTC 25
Finished Feb 09 04:16:46 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038800341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3038800341
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.503671082
Short name T327
Test name
Test status
Simulation time 155193794 ps
CPU time 7.43 seconds
Started Feb 09 04:16:42 AM UTC 25
Finished Feb 09 04:16:51 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503671082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.503671082
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.1147130127
Short name T541
Test name
Test status
Simulation time 207903286 ps
CPU time 9.36 seconds
Started Feb 09 04:16:30 AM UTC 25
Finished Feb 09 04:16:41 AM UTC 25
Peak memory 251112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147130127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1147130127
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.650250102
Short name T164
Test name
Test status
Simulation time 21649552248 ps
CPU time 169.86 seconds
Started Feb 09 04:16:45 AM UTC 25
Finished Feb 09 04:19:37 AM UTC 25
Peak memory 257344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650250102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.650250102
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1897301929
Short name T934
Test name
Test status
Simulation time 100576500871 ps
CPU time 1795.15 seconds
Started Feb 09 04:16:45 AM UTC 25
Finished Feb 09 04:46:59 AM UTC 25
Peak memory 284156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1897301929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_a
ll_with_rand_reset.1897301929
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.2179244515
Short name T328
Test name
Test status
Simulation time 3810445060 ps
CPU time 8.51 seconds
Started Feb 09 04:16:42 AM UTC 25
Finished Feb 09 04:16:52 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179244515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2179244515
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.3814459556
Short name T970
Test name
Test status
Simulation time 214594818 ps
CPU time 5.35 seconds
Started Feb 09 04:47:48 AM UTC 25
Finished Feb 09 04:47:55 AM UTC 25
Peak memory 251392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814459556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3814459556
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.2879690578
Short name T971
Test name
Test status
Simulation time 109330802 ps
CPU time 5.46 seconds
Started Feb 09 04:47:50 AM UTC 25
Finished Feb 09 04:47:56 AM UTC 25
Peak memory 251024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879690578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.2879690578
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.3630927955
Short name T79
Test name
Test status
Simulation time 2326610536 ps
CPU time 7.51 seconds
Started Feb 09 04:47:51 AM UTC 25
Finished Feb 09 04:47:59 AM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630927955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3630927955
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.3832157967
Short name T975
Test name
Test status
Simulation time 2388311749 ps
CPU time 12.42 seconds
Started Feb 09 04:47:53 AM UTC 25
Finished Feb 09 04:48:07 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832157967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3832157967
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3713917941
Short name T972
Test name
Test status
Simulation time 228214647 ps
CPU time 5.87 seconds
Started Feb 09 04:47:55 AM UTC 25
Finished Feb 09 04:48:02 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713917941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3713917941
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.2544099105
Short name T973
Test name
Test status
Simulation time 153218516 ps
CPU time 5.27 seconds
Started Feb 09 04:47:56 AM UTC 25
Finished Feb 09 04:48:03 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544099105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2544099105
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.1079191793
Short name T974
Test name
Test status
Simulation time 601212710 ps
CPU time 5.75 seconds
Started Feb 09 04:47:57 AM UTC 25
Finished Feb 09 04:48:04 AM UTC 25
Peak memory 253404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079191793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.1079191793
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.3424516608
Short name T977
Test name
Test status
Simulation time 1786725190 ps
CPU time 6.95 seconds
Started Feb 09 04:48:00 AM UTC 25
Finished Feb 09 04:48:08 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424516608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3424516608
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.3170628018
Short name T976
Test name
Test status
Simulation time 132624702 ps
CPU time 5.57 seconds
Started Feb 09 04:48:00 AM UTC 25
Finished Feb 09 04:48:07 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170628018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3170628018
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.349659641
Short name T987
Test name
Test status
Simulation time 402173948 ps
CPU time 15.02 seconds
Started Feb 09 04:48:03 AM UTC 25
Finished Feb 09 04:48:20 AM UTC 25
Peak memory 250832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349659641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.349659641
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3372351764
Short name T978
Test name
Test status
Simulation time 505948717 ps
CPU time 5.57 seconds
Started Feb 09 04:48:04 AM UTC 25
Finished Feb 09 04:48:10 AM UTC 25
Peak memory 250908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372351764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3372351764
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.1174099284
Short name T983
Test name
Test status
Simulation time 574836302 ps
CPU time 10.11 seconds
Started Feb 09 04:48:06 AM UTC 25
Finished Feb 09 04:48:17 AM UTC 25
Peak memory 253300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174099284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1174099284
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.1165709027
Short name T982
Test name
Test status
Simulation time 126810669 ps
CPU time 4.69 seconds
Started Feb 09 04:48:08 AM UTC 25
Finished Feb 09 04:48:14 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165709027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.1165709027
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.4126271828
Short name T986
Test name
Test status
Simulation time 269872337 ps
CPU time 9.61 seconds
Started Feb 09 04:48:08 AM UTC 25
Finished Feb 09 04:48:19 AM UTC 25
Peak memory 251316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126271828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.4126271828
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1295993575
Short name T984
Test name
Test status
Simulation time 460977622 ps
CPU time 6.6 seconds
Started Feb 09 04:48:09 AM UTC 25
Finished Feb 09 04:48:17 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295993575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1295993575
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.2166663211
Short name T997
Test name
Test status
Simulation time 6641264103 ps
CPU time 22.53 seconds
Started Feb 09 04:48:12 AM UTC 25
Finished Feb 09 04:48:36 AM UTC 25
Peak memory 250924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166663211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2166663211
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.3911847016
Short name T985
Test name
Test status
Simulation time 237542741 ps
CPU time 5 seconds
Started Feb 09 04:48:12 AM UTC 25
Finished Feb 09 04:48:18 AM UTC 25
Peak memory 250856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911847016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3911847016
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.2847177339
Short name T988
Test name
Test status
Simulation time 176581374 ps
CPU time 5.08 seconds
Started Feb 09 04:48:14 AM UTC 25
Finished Feb 09 04:48:20 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847177339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2847177339
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.1396317180
Short name T1000
Test name
Test status
Simulation time 4115738448 ps
CPU time 22.94 seconds
Started Feb 09 04:48:15 AM UTC 25
Finished Feb 09 04:48:39 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396317180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1396317180
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.1472037090
Short name T213
Test name
Test status
Simulation time 52350515 ps
CPU time 2.64 seconds
Started Feb 09 04:17:00 AM UTC 25
Finished Feb 09 04:17:03 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472037090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1472037090
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.618964945
Short name T211
Test name
Test status
Simulation time 341809346 ps
CPU time 6.67 seconds
Started Feb 09 04:16:52 AM UTC 25
Finished Feb 09 04:17:00 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618964945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.618964945
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.2633312867
Short name T212
Test name
Test status
Simulation time 2109693116 ps
CPU time 9.65 seconds
Started Feb 09 04:16:52 AM UTC 25
Finished Feb 09 04:17:03 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633312867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2633312867
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.3073772265
Short name T549
Test name
Test status
Simulation time 12259489307 ps
CPU time 33.54 seconds
Started Feb 09 04:16:51 AM UTC 25
Finished Feb 09 04:17:26 AM UTC 25
Peak memory 253276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073772265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3073772265
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.4258407282
Short name T109
Test name
Test status
Simulation time 368223780 ps
CPU time 5.56 seconds
Started Feb 09 04:16:48 AM UTC 25
Finished Feb 09 04:16:55 AM UTC 25
Peak memory 251152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258407282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.4258407282
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1092078365
Short name T551
Test name
Test status
Simulation time 3873132001 ps
CPU time 34.9 seconds
Started Feb 09 04:16:54 AM UTC 25
Finished Feb 09 04:17:30 AM UTC 25
Peak memory 255260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092078365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1092078365
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.172057606
Short name T505
Test name
Test status
Simulation time 535700400 ps
CPU time 16.26 seconds
Started Feb 09 04:16:54 AM UTC 25
Finished Feb 09 04:17:11 AM UTC 25
Peak memory 257272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172057606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.172057606
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.1958711904
Short name T208
Test name
Test status
Simulation time 161375997 ps
CPU time 3.14 seconds
Started Feb 09 04:16:51 AM UTC 25
Finished Feb 09 04:16:55 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958711904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1958711904
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.1356007683
Short name T548
Test name
Test status
Simulation time 10021902507 ps
CPU time 31.59 seconds
Started Feb 09 04:16:51 AM UTC 25
Finished Feb 09 04:17:24 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356007683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1356007683
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.2319402996
Short name T214
Test name
Test status
Simulation time 619449511 ps
CPU time 9.57 seconds
Started Feb 09 04:16:54 AM UTC 25
Finished Feb 09 04:17:05 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319402996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2319402996
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.350037374
Short name T209
Test name
Test status
Simulation time 3247680186 ps
CPU time 8.97 seconds
Started Feb 09 04:16:48 AM UTC 25
Finished Feb 09 04:16:58 AM UTC 25
Peak memory 251464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350037374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.otp_ctrl_smoke.350037374
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.1176710731
Short name T16
Test name
Test status
Simulation time 21947725836 ps
CPU time 451 seconds
Started Feb 09 04:16:56 AM UTC 25
Finished Feb 09 04:24:33 AM UTC 25
Peak memory 292240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1176710731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_a
ll_with_rand_reset.1176710731
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.4276376644
Short name T215
Test name
Test status
Simulation time 710679927 ps
CPU time 9.83 seconds
Started Feb 09 04:16:56 AM UTC 25
Finished Feb 09 04:17:07 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276376644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.4276376644
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.3798337181
Short name T991
Test name
Test status
Simulation time 192419816 ps
CPU time 6.59 seconds
Started Feb 09 04:48:18 AM UTC 25
Finished Feb 09 04:48:26 AM UTC 25
Peak memory 250868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798337181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3798337181
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.1151722166
Short name T989
Test name
Test status
Simulation time 132966680 ps
CPU time 4.66 seconds
Started Feb 09 04:48:18 AM UTC 25
Finished Feb 09 04:48:24 AM UTC 25
Peak memory 250868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151722166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1151722166
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.3574385386
Short name T992
Test name
Test status
Simulation time 133385560 ps
CPU time 6.49 seconds
Started Feb 09 04:48:20 AM UTC 25
Finished Feb 09 04:48:27 AM UTC 25
Peak memory 253192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574385386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3574385386
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.708442807
Short name T995
Test name
Test status
Simulation time 1420353511 ps
CPU time 12.15 seconds
Started Feb 09 04:48:20 AM UTC 25
Finished Feb 09 04:48:33 AM UTC 25
Peak memory 251232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708442807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.708442807
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.113990752
Short name T990
Test name
Test status
Simulation time 180948367 ps
CPU time 4.62 seconds
Started Feb 09 04:48:20 AM UTC 25
Finished Feb 09 04:48:25 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113990752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.113990752
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.1994787618
Short name T1001
Test name
Test status
Simulation time 6554609526 ps
CPU time 15.3 seconds
Started Feb 09 04:48:23 AM UTC 25
Finished Feb 09 04:48:39 AM UTC 25
Peak memory 253364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994787618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1994787618
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.2127553500
Short name T993
Test name
Test status
Simulation time 114841499 ps
CPU time 6 seconds
Started Feb 09 04:48:23 AM UTC 25
Finished Feb 09 04:48:30 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127553500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2127553500
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.1740726031
Short name T998
Test name
Test status
Simulation time 748285763 ps
CPU time 13.32 seconds
Started Feb 09 04:48:23 AM UTC 25
Finished Feb 09 04:48:37 AM UTC 25
Peak memory 251256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740726031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1740726031
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.1253116824
Short name T994
Test name
Test status
Simulation time 181848971 ps
CPU time 5.69 seconds
Started Feb 09 04:48:25 AM UTC 25
Finished Feb 09 04:48:32 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253116824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1253116824
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.238689301
Short name T999
Test name
Test status
Simulation time 302344199 ps
CPU time 11.31 seconds
Started Feb 09 04:48:26 AM UTC 25
Finished Feb 09 04:48:39 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238689301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.238689301
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.3878541865
Short name T996
Test name
Test status
Simulation time 273269937 ps
CPU time 5.94 seconds
Started Feb 09 04:48:27 AM UTC 25
Finished Feb 09 04:48:35 AM UTC 25
Peak memory 253340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878541865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3878541865
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.3357552929
Short name T1003
Test name
Test status
Simulation time 204841941 ps
CPU time 10.11 seconds
Started Feb 09 04:48:29 AM UTC 25
Finished Feb 09 04:48:40 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357552929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3357552929
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.2854912364
Short name T1004
Test name
Test status
Simulation time 204046288 ps
CPU time 5.38 seconds
Started Feb 09 04:48:34 AM UTC 25
Finished Feb 09 04:48:41 AM UTC 25
Peak memory 253156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854912364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2854912364
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.379868715
Short name T1015
Test name
Test status
Simulation time 2036882540 ps
CPU time 16.12 seconds
Started Feb 09 04:48:34 AM UTC 25
Finished Feb 09 04:48:52 AM UTC 25
Peak memory 251028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379868715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.379868715
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.3053304734
Short name T1002
Test name
Test status
Simulation time 361449759 ps
CPU time 4.68 seconds
Started Feb 09 04:48:34 AM UTC 25
Finished Feb 09 04:48:40 AM UTC 25
Peak memory 253240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053304734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3053304734
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.1470237755
Short name T1012
Test name
Test status
Simulation time 336925622 ps
CPU time 13.99 seconds
Started Feb 09 04:48:34 AM UTC 25
Finished Feb 09 04:48:49 AM UTC 25
Peak memory 251188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470237755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1470237755
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.3744356378
Short name T1005
Test name
Test status
Simulation time 298346481 ps
CPU time 5.05 seconds
Started Feb 09 04:48:38 AM UTC 25
Finished Feb 09 04:48:44 AM UTC 25
Peak memory 251000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744356378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3744356378
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.3830775782
Short name T1006
Test name
Test status
Simulation time 194622957 ps
CPU time 5.6 seconds
Started Feb 09 04:48:38 AM UTC 25
Finished Feb 09 04:48:45 AM UTC 25
Peak memory 253144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830775782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3830775782
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.1493345164
Short name T1007
Test name
Test status
Simulation time 163880232 ps
CPU time 6.19 seconds
Started Feb 09 04:48:38 AM UTC 25
Finished Feb 09 04:48:46 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493345164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1493345164
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.160705057
Short name T546
Test name
Test status
Simulation time 94416647 ps
CPU time 3.47 seconds
Started Feb 09 04:17:17 AM UTC 25
Finished Feb 09 04:17:21 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160705057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.160705057
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.3941832103
Short name T483
Test name
Test status
Simulation time 323548421 ps
CPU time 8.21 seconds
Started Feb 09 04:17:08 AM UTC 25
Finished Feb 09 04:17:17 AM UTC 25
Peak memory 257404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941832103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3941832103
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.3954430511
Short name T547
Test name
Test status
Simulation time 335874788 ps
CPU time 15.84 seconds
Started Feb 09 04:17:05 AM UTC 25
Finished Feb 09 04:17:22 AM UTC 25
Peak memory 251216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954430511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3954430511
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.1624663200
Short name T478
Test name
Test status
Simulation time 10357157862 ps
CPU time 28.14 seconds
Started Feb 09 04:17:04 AM UTC 25
Finished Feb 09 04:17:34 AM UTC 25
Peak memory 253280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624663200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.1624663200
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2477167790
Short name T33
Test name
Test status
Simulation time 320785094 ps
CPU time 4.35 seconds
Started Feb 09 04:17:01 AM UTC 25
Finished Feb 09 04:17:06 AM UTC 25
Peak memory 251352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477167790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2477167790
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.323872388
Short name T197
Test name
Test status
Simulation time 442491738 ps
CPU time 11.51 seconds
Started Feb 09 04:17:08 AM UTC 25
Finished Feb 09 04:17:20 AM UTC 25
Peak memory 257268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323872388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.323872388
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.882106596
Short name T492
Test name
Test status
Simulation time 603235868 ps
CPU time 26.52 seconds
Started Feb 09 04:17:09 AM UTC 25
Finished Feb 09 04:17:37 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882106596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.882106596
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.1779782098
Short name T544
Test name
Test status
Simulation time 547949564 ps
CPU time 6.63 seconds
Started Feb 09 04:17:03 AM UTC 25
Finished Feb 09 04:17:11 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779782098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1779782098
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.3519891999
Short name T545
Test name
Test status
Simulation time 275461595 ps
CPU time 6.24 seconds
Started Feb 09 04:17:09 AM UTC 25
Finished Feb 09 04:17:16 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519891999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3519891999
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.1643202087
Short name T503
Test name
Test status
Simulation time 1283972179 ps
CPU time 16.44 seconds
Started Feb 09 04:17:01 AM UTC 25
Finished Feb 09 04:17:18 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643202087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1643202087
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3705320254
Short name T502
Test name
Test status
Simulation time 107138911782 ps
CPU time 1663.36 seconds
Started Feb 09 04:17:13 AM UTC 25
Finished Feb 09 04:45:14 AM UTC 25
Peak memory 501244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3705320254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_a
ll_with_rand_reset.3705320254
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.2814139169
Short name T220
Test name
Test status
Simulation time 1103740619 ps
CPU time 36.91 seconds
Started Feb 09 04:17:11 AM UTC 25
Finished Feb 09 04:17:50 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814139169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2814139169
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.3726381573
Short name T1008
Test name
Test status
Simulation time 1840399437 ps
CPU time 5.5 seconds
Started Feb 09 04:48:39 AM UTC 25
Finished Feb 09 04:48:46 AM UTC 25
Peak memory 253184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726381573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3726381573
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.195053416
Short name T1020
Test name
Test status
Simulation time 434494143 ps
CPU time 13.75 seconds
Started Feb 09 04:48:42 AM UTC 25
Finished Feb 09 04:48:57 AM UTC 25
Peak memory 253144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195053416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.195053416
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.4267431110
Short name T1010
Test name
Test status
Simulation time 178461471 ps
CPU time 5.27 seconds
Started Feb 09 04:48:42 AM UTC 25
Finished Feb 09 04:48:48 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267431110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.4267431110
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.1816304263
Short name T1019
Test name
Test status
Simulation time 4913486780 ps
CPU time 12.88 seconds
Started Feb 09 04:48:42 AM UTC 25
Finished Feb 09 04:48:56 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816304263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1816304263
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.1440496119
Short name T1011
Test name
Test status
Simulation time 231825134 ps
CPU time 6.26 seconds
Started Feb 09 04:48:42 AM UTC 25
Finished Feb 09 04:48:49 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440496119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1440496119
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.592472191
Short name T1013
Test name
Test status
Simulation time 111238709 ps
CPU time 6.71 seconds
Started Feb 09 04:48:42 AM UTC 25
Finished Feb 09 04:48:50 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592472191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.592472191
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.2945421143
Short name T1016
Test name
Test status
Simulation time 182283906 ps
CPU time 5.98 seconds
Started Feb 09 04:48:45 AM UTC 25
Finished Feb 09 04:48:52 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945421143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2945421143
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.182177241
Short name T1014
Test name
Test status
Simulation time 205505469 ps
CPU time 4.01 seconds
Started Feb 09 04:48:45 AM UTC 25
Finished Feb 09 04:48:50 AM UTC 25
Peak memory 257180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182177241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.182177241
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.3487822134
Short name T1017
Test name
Test status
Simulation time 249294448 ps
CPU time 4.93 seconds
Started Feb 09 04:48:46 AM UTC 25
Finished Feb 09 04:48:52 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487822134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3487822134
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.987684875
Short name T1023
Test name
Test status
Simulation time 294948017 ps
CPU time 12.04 seconds
Started Feb 09 04:48:46 AM UTC 25
Finished Feb 09 04:49:00 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987684875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.987684875
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.970383442
Short name T1018
Test name
Test status
Simulation time 297928586 ps
CPU time 6.44 seconds
Started Feb 09 04:48:48 AM UTC 25
Finished Feb 09 04:48:55 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970383442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.970383442
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.2226960264
Short name T1029
Test name
Test status
Simulation time 684966900 ps
CPU time 12.88 seconds
Started Feb 09 04:48:52 AM UTC 25
Finished Feb 09 04:49:06 AM UTC 25
Peak memory 253168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226960264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2226960264
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.1156919055
Short name T1022
Test name
Test status
Simulation time 256634802 ps
CPU time 5.13 seconds
Started Feb 09 04:48:52 AM UTC 25
Finished Feb 09 04:48:59 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156919055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1156919055
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.3681476685
Short name T1024
Test name
Test status
Simulation time 258851696 ps
CPU time 6.86 seconds
Started Feb 09 04:48:52 AM UTC 25
Finished Feb 09 04:49:00 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681476685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3681476685
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.2312443244
Short name T113
Test name
Test status
Simulation time 2265004285 ps
CPU time 9.92 seconds
Started Feb 09 04:48:52 AM UTC 25
Finished Feb 09 04:49:03 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312443244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2312443244
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.3066120228
Short name T1039
Test name
Test status
Simulation time 4943735385 ps
CPU time 23.18 seconds
Started Feb 09 04:48:52 AM UTC 25
Finished Feb 09 04:49:17 AM UTC 25
Peak memory 253428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066120228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.3066120228
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.2731653218
Short name T1021
Test name
Test status
Simulation time 378701424 ps
CPU time 4.97 seconds
Started Feb 09 04:48:52 AM UTC 25
Finished Feb 09 04:48:59 AM UTC 25
Peak memory 253240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731653218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2731653218
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.1445058859
Short name T1025
Test name
Test status
Simulation time 2156174403 ps
CPU time 7.11 seconds
Started Feb 09 04:48:54 AM UTC 25
Finished Feb 09 04:49:02 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445058859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1445058859
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.1554816394
Short name T1027
Test name
Test status
Simulation time 2215706560 ps
CPU time 9.71 seconds
Started Feb 09 04:48:54 AM UTC 25
Finished Feb 09 04:49:05 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554816394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1554816394
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.1884181259
Short name T1030
Test name
Test status
Simulation time 380909336 ps
CPU time 11.61 seconds
Started Feb 09 04:48:54 AM UTC 25
Finished Feb 09 04:49:07 AM UTC 25
Peak memory 251316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884181259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1884181259
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.2502609734
Short name T554
Test name
Test status
Simulation time 99564985 ps
CPU time 2.42 seconds
Started Feb 09 04:17:35 AM UTC 25
Finished Feb 09 04:17:39 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502609734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2502609734
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.322575060
Short name T49
Test name
Test status
Simulation time 10674141978 ps
CPU time 38.99 seconds
Started Feb 09 04:17:24 AM UTC 25
Finished Feb 09 04:18:04 AM UTC 25
Peak memory 257400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322575060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.322575060
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.3018521893
Short name T216
Test name
Test status
Simulation time 653178348 ps
CPU time 21.98 seconds
Started Feb 09 04:17:22 AM UTC 25
Finished Feb 09 04:17:46 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018521893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3018521893
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.4152378775
Short name T221
Test name
Test status
Simulation time 1198571299 ps
CPU time 27.07 seconds
Started Feb 09 04:17:21 AM UTC 25
Finished Feb 09 04:17:50 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152378775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.4152378775
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1687036817
Short name T55
Test name
Test status
Simulation time 172053685 ps
CPU time 6.31 seconds
Started Feb 09 04:17:19 AM UTC 25
Finished Feb 09 04:17:27 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687036817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1687036817
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.103639227
Short name T179
Test name
Test status
Simulation time 862815974 ps
CPU time 23.35 seconds
Started Feb 09 04:17:25 AM UTC 25
Finished Feb 09 04:17:50 AM UTC 25
Peak memory 253236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103639227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.103639227
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3053483813
Short name T219
Test name
Test status
Simulation time 1644554648 ps
CPU time 20.19 seconds
Started Feb 09 04:17:27 AM UTC 25
Finished Feb 09 04:17:48 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053483813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3053483813
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.1098115754
Short name T550
Test name
Test status
Simulation time 184437127 ps
CPU time 5.96 seconds
Started Feb 09 04:17:19 AM UTC 25
Finished Feb 09 04:17:27 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098115754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1098115754
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.3540758330
Short name T552
Test name
Test status
Simulation time 278111923 ps
CPU time 8.44 seconds
Started Feb 09 04:17:28 AM UTC 25
Finished Feb 09 04:17:38 AM UTC 25
Peak memory 250868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540758330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3540758330
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.774785922
Short name T555
Test name
Test status
Simulation time 6840775270 ps
CPU time 20.33 seconds
Started Feb 09 04:17:18 AM UTC 25
Finished Feb 09 04:17:39 AM UTC 25
Peak memory 251272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774785922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.otp_ctrl_smoke.774785922
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1755626213
Short name T1184
Test name
Test status
Simulation time 493011207301 ps
CPU time 3374.17 seconds
Started Feb 09 04:17:28 AM UTC 25
Finished Feb 09 05:14:18 AM UTC 25
Peak memory 437752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1755626213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_a
ll_with_rand_reset.1755626213
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.2044790977
Short name T1026
Test name
Test status
Simulation time 141864992 ps
CPU time 5.04 seconds
Started Feb 09 04:48:56 AM UTC 25
Finished Feb 09 04:49:02 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044790977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2044790977
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.201151697
Short name T1033
Test name
Test status
Simulation time 1909972544 ps
CPU time 10.88 seconds
Started Feb 09 04:48:58 AM UTC 25
Finished Feb 09 04:49:10 AM UTC 25
Peak memory 251000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201151697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.201151697
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.4056454217
Short name T1028
Test name
Test status
Simulation time 248052401 ps
CPU time 6.42 seconds
Started Feb 09 04:48:58 AM UTC 25
Finished Feb 09 04:49:05 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056454217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.4056454217
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.4124762138
Short name T1046
Test name
Test status
Simulation time 1224152683 ps
CPU time 21.35 seconds
Started Feb 09 04:49:00 AM UTC 25
Finished Feb 09 04:49:23 AM UTC 25
Peak memory 250868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124762138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.4124762138
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.1032054679
Short name T1031
Test name
Test status
Simulation time 108698226 ps
CPU time 5.88 seconds
Started Feb 09 04:49:00 AM UTC 25
Finished Feb 09 04:49:07 AM UTC 25
Peak memory 250900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032054679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1032054679
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1194755958
Short name T1036
Test name
Test status
Simulation time 2396468925 ps
CPU time 12.73 seconds
Started Feb 09 04:49:01 AM UTC 25
Finished Feb 09 04:49:15 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194755958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1194755958
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.4241009761
Short name T66
Test name
Test status
Simulation time 189644946 ps
CPU time 6.76 seconds
Started Feb 09 04:49:01 AM UTC 25
Finished Feb 09 04:49:09 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241009761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.4241009761
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.3762882311
Short name T1040
Test name
Test status
Simulation time 204023151 ps
CPU time 13.12 seconds
Started Feb 09 04:49:03 AM UTC 25
Finished Feb 09 04:49:17 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762882311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3762882311
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.3408036625
Short name T1032
Test name
Test status
Simulation time 688431821 ps
CPU time 4.89 seconds
Started Feb 09 04:49:03 AM UTC 25
Finished Feb 09 04:49:09 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408036625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3408036625
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.1489672722
Short name T1034
Test name
Test status
Simulation time 92907008 ps
CPU time 5.24 seconds
Started Feb 09 04:49:04 AM UTC 25
Finished Feb 09 04:49:10 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489672722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1489672722
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.3813668167
Short name T1035
Test name
Test status
Simulation time 648890253 ps
CPU time 7.05 seconds
Started Feb 09 04:49:06 AM UTC 25
Finished Feb 09 04:49:15 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813668167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3813668167
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.1976756383
Short name T1041
Test name
Test status
Simulation time 297306805 ps
CPU time 10.04 seconds
Started Feb 09 04:49:06 AM UTC 25
Finished Feb 09 04:49:18 AM UTC 25
Peak memory 251120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976756383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.1976756383
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.3620837684
Short name T1037
Test name
Test status
Simulation time 376622768 ps
CPU time 6.56 seconds
Started Feb 09 04:49:08 AM UTC 25
Finished Feb 09 04:49:16 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620837684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3620837684
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.776516060
Short name T1043
Test name
Test status
Simulation time 373943384 ps
CPU time 8.91 seconds
Started Feb 09 04:49:08 AM UTC 25
Finished Feb 09 04:49:18 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776516060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.776516060
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.1697348657
Short name T1038
Test name
Test status
Simulation time 1937054486 ps
CPU time 7.47 seconds
Started Feb 09 04:49:08 AM UTC 25
Finished Feb 09 04:49:17 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697348657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1697348657
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2291621905
Short name T1050
Test name
Test status
Simulation time 1081105975 ps
CPU time 14.87 seconds
Started Feb 09 04:49:09 AM UTC 25
Finished Feb 09 04:49:25 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291621905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2291621905
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.3049625167
Short name T1044
Test name
Test status
Simulation time 1743915807 ps
CPU time 7.56 seconds
Started Feb 09 04:49:10 AM UTC 25
Finished Feb 09 04:49:19 AM UTC 25
Peak memory 251092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049625167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3049625167
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.2731292954
Short name T1045
Test name
Test status
Simulation time 371561954 ps
CPU time 10.29 seconds
Started Feb 09 04:49:11 AM UTC 25
Finished Feb 09 04:49:22 AM UTC 25
Peak memory 251224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731292954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2731292954
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.4165437836
Short name T1042
Test name
Test status
Simulation time 168755709 ps
CPU time 5.24 seconds
Started Feb 09 04:49:12 AM UTC 25
Finished Feb 09 04:49:18 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165437836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4165437836
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.2432491792
Short name T1080
Test name
Test status
Simulation time 3544933709 ps
CPU time 38.04 seconds
Started Feb 09 04:49:16 AM UTC 25
Finished Feb 09 04:49:56 AM UTC 25
Peak memory 251012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432491792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2432491792
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.492736923
Short name T557
Test name
Test status
Simulation time 1073347562 ps
CPU time 4.42 seconds
Started Feb 09 04:17:53 AM UTC 25
Finished Feb 09 04:17:58 AM UTC 25
Peak memory 251056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492736923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.492736923
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.2354953582
Short name T85
Test name
Test status
Simulation time 4634235569 ps
CPU time 15.35 seconds
Started Feb 09 04:17:42 AM UTC 25
Finished Feb 09 04:17:58 AM UTC 25
Peak memory 257200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354953582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2354953582
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.3220661461
Short name T263
Test name
Test status
Simulation time 158999108 ps
CPU time 9.22 seconds
Started Feb 09 04:17:40 AM UTC 25
Finished Feb 09 04:17:50 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220661461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3220661461
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.2134460548
Short name T493
Test name
Test status
Simulation time 1513055292 ps
CPU time 32.86 seconds
Started Feb 09 04:17:40 AM UTC 25
Finished Feb 09 04:18:14 AM UTC 25
Peak memory 251460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134460548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2134460548
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.397130432
Short name T110
Test name
Test status
Simulation time 156910586 ps
CPU time 5.98 seconds
Started Feb 09 04:17:38 AM UTC 25
Finished Feb 09 04:17:46 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397130432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.397130432
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.1828302960
Short name T218
Test name
Test status
Simulation time 645887900 ps
CPU time 8.78 seconds
Started Feb 09 04:17:42 AM UTC 25
Finished Feb 09 04:17:52 AM UTC 25
Peak memory 252924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828302960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1828302960
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.1125878244
Short name T223
Test name
Test status
Simulation time 401887529 ps
CPU time 7.32 seconds
Started Feb 09 04:17:46 AM UTC 25
Finished Feb 09 04:17:55 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125878244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1125878244
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.3247760525
Short name T217
Test name
Test status
Simulation time 1721320549 ps
CPU time 5.89 seconds
Started Feb 09 04:17:40 AM UTC 25
Finished Feb 09 04:17:47 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247760525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3247760525
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.3285920907
Short name T222
Test name
Test status
Simulation time 717434808 ps
CPU time 13.69 seconds
Started Feb 09 04:17:38 AM UTC 25
Finished Feb 09 04:17:53 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285920907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3285920907
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.2050422804
Short name T449
Test name
Test status
Simulation time 2688895600 ps
CPU time 9.11 seconds
Started Feb 09 04:17:46 AM UTC 25
Finished Feb 09 04:17:56 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050422804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2050422804
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.215169832
Short name T556
Test name
Test status
Simulation time 830561650 ps
CPU time 7.07 seconds
Started Feb 09 04:17:37 AM UTC 25
Finished Feb 09 04:17:45 AM UTC 25
Peak memory 257352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215169832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.otp_ctrl_smoke.215169832
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.1700520106
Short name T402
Test name
Test status
Simulation time 27693116695 ps
CPU time 259.58 seconds
Started Feb 09 04:17:49 AM UTC 25
Finished Feb 09 04:22:12 AM UTC 25
Peak memory 273824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700520106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.1700520106
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.92080473
Short name T559
Test name
Test status
Simulation time 241652971 ps
CPU time 9.91 seconds
Started Feb 09 04:17:47 AM UTC 25
Finished Feb 09 04:17:59 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92080473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.92080473
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.134146955
Short name T1047
Test name
Test status
Simulation time 349418001 ps
CPU time 5.47 seconds
Started Feb 09 04:49:16 AM UTC 25
Finished Feb 09 04:49:23 AM UTC 25
Peak memory 252892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134146955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.134146955
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3860247555
Short name T1056
Test name
Test status
Simulation time 3067129291 ps
CPU time 13.97 seconds
Started Feb 09 04:49:16 AM UTC 25
Finished Feb 09 04:49:31 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860247555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3860247555
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.3531181785
Short name T1053
Test name
Test status
Simulation time 2377580835 ps
CPU time 8.04 seconds
Started Feb 09 04:49:18 AM UTC 25
Finished Feb 09 04:49:27 AM UTC 25
Peak memory 251284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531181785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3531181785
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.115935162
Short name T1049
Test name
Test status
Simulation time 162998129 ps
CPU time 5.88 seconds
Started Feb 09 04:49:18 AM UTC 25
Finished Feb 09 04:49:25 AM UTC 25
Peak memory 250928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115935162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.115935162
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.1922688822
Short name T1048
Test name
Test status
Simulation time 470504640 ps
CPU time 4.73 seconds
Started Feb 09 04:49:18 AM UTC 25
Finished Feb 09 04:49:24 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922688822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1922688822
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.2041652777
Short name T1054
Test name
Test status
Simulation time 611089071 ps
CPU time 10.81 seconds
Started Feb 09 04:49:18 AM UTC 25
Finished Feb 09 04:49:30 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041652777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2041652777
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.439078105
Short name T1051
Test name
Test status
Simulation time 450297227 ps
CPU time 5.27 seconds
Started Feb 09 04:49:20 AM UTC 25
Finished Feb 09 04:49:26 AM UTC 25
Peak memory 250912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439078105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.439078105
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.934571802
Short name T1059
Test name
Test status
Simulation time 583758612 ps
CPU time 12.64 seconds
Started Feb 09 04:49:20 AM UTC 25
Finished Feb 09 04:49:34 AM UTC 25
Peak memory 250948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934571802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.934571802
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1384451109
Short name T1052
Test name
Test status
Simulation time 262466174 ps
CPU time 5.95 seconds
Started Feb 09 04:49:20 AM UTC 25
Finished Feb 09 04:49:27 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384451109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1384451109
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.739958630
Short name T157
Test name
Test status
Simulation time 3970038198 ps
CPU time 21.59 seconds
Started Feb 09 04:49:23 AM UTC 25
Finished Feb 09 04:49:46 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739958630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.739958630
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1257333765
Short name T1055
Test name
Test status
Simulation time 2489990068 ps
CPU time 5.82 seconds
Started Feb 09 04:49:23 AM UTC 25
Finished Feb 09 04:49:30 AM UTC 25
Peak memory 251420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257333765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1257333765
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.3507047192
Short name T1058
Test name
Test status
Simulation time 1607287756 ps
CPU time 7.57 seconds
Started Feb 09 04:49:24 AM UTC 25
Finished Feb 09 04:49:32 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507047192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3507047192
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.736784821
Short name T203
Test name
Test status
Simulation time 99847634 ps
CPU time 4.1 seconds
Started Feb 09 04:49:25 AM UTC 25
Finished Feb 09 04:49:30 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736784821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.736784821
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2116098359
Short name T240
Test name
Test status
Simulation time 2895159005 ps
CPU time 8.6 seconds
Started Feb 09 04:49:26 AM UTC 25
Finished Feb 09 04:49:36 AM UTC 25
Peak memory 250876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116098359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2116098359
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1792679032
Short name T1057
Test name
Test status
Simulation time 237038551 ps
CPU time 4.75 seconds
Started Feb 09 04:49:26 AM UTC 25
Finished Feb 09 04:49:32 AM UTC 25
Peak memory 251084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792679032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1792679032
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3284980808
Short name T1063
Test name
Test status
Simulation time 311926740 ps
CPU time 10.86 seconds
Started Feb 09 04:49:28 AM UTC 25
Finished Feb 09 04:49:40 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284980808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3284980808
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.1234453286
Short name T1060
Test name
Test status
Simulation time 129633766 ps
CPU time 6.17 seconds
Started Feb 09 04:49:28 AM UTC 25
Finished Feb 09 04:49:35 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234453286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1234453286
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.749961143
Short name T1067
Test name
Test status
Simulation time 342329296 ps
CPU time 12.42 seconds
Started Feb 09 04:49:28 AM UTC 25
Finished Feb 09 04:49:42 AM UTC 25
Peak memory 253108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749961143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.749961143
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2494364004
Short name T1065
Test name
Test status
Simulation time 151608832 ps
CPU time 7.44 seconds
Started Feb 09 04:49:31 AM UTC 25
Finished Feb 09 04:49:40 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494364004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2494364004
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.1010399028
Short name T561
Test name
Test status
Simulation time 68345872 ps
CPU time 2.74 seconds
Started Feb 09 04:18:02 AM UTC 25
Finished Feb 09 04:18:06 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010399028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.1010399028
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.211378128
Short name T564
Test name
Test status
Simulation time 11030308293 ps
CPU time 33.62 seconds
Started Feb 09 04:17:55 AM UTC 25
Finished Feb 09 04:18:30 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211378128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.211378128
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.4060439363
Short name T570
Test name
Test status
Simulation time 1431596089 ps
CPU time 44.28 seconds
Started Feb 09 04:17:54 AM UTC 25
Finished Feb 09 04:18:40 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060439363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.4060439363
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.1012131284
Short name T558
Test name
Test status
Simulation time 257040011 ps
CPU time 4.41 seconds
Started Feb 09 04:17:53 AM UTC 25
Finished Feb 09 04:17:58 AM UTC 25
Peak memory 251288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012131284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1012131284
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.299479262
Short name T225
Test name
Test status
Simulation time 9313299414 ps
CPU time 24.68 seconds
Started Feb 09 04:17:58 AM UTC 25
Finished Feb 09 04:18:24 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299479262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.299479262
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.104733476
Short name T472
Test name
Test status
Simulation time 12124002828 ps
CPU time 41.51 seconds
Started Feb 09 04:17:59 AM UTC 25
Finished Feb 09 04:18:42 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104733476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.104733476
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.2364364937
Short name T560
Test name
Test status
Simulation time 195847385 ps
CPU time 7.19 seconds
Started Feb 09 04:17:53 AM UTC 25
Finished Feb 09 04:18:01 AM UTC 25
Peak memory 251072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364364937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2364364937
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.4161383388
Short name T499
Test name
Test status
Simulation time 2278265122 ps
CPU time 24.36 seconds
Started Feb 09 04:17:53 AM UTC 25
Finished Feb 09 04:18:18 AM UTC 25
Peak memory 257312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161383388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.4161383388
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.203339797
Short name T553
Test name
Test status
Simulation time 556669031 ps
CPU time 6.68 seconds
Started Feb 09 04:17:53 AM UTC 25
Finished Feb 09 04:18:01 AM UTC 25
Peak memory 251204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203339797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.otp_ctrl_smoke.203339797
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.1899567303
Short name T441
Test name
Test status
Simulation time 33770385098 ps
CPU time 217.11 seconds
Started Feb 09 04:18:01 AM UTC 25
Finished Feb 09 04:21:42 AM UTC 25
Peak memory 267680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899567303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.1899567303
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.159645728
Short name T338
Test name
Test status
Simulation time 4683828614 ps
CPU time 24.83 seconds
Started Feb 09 04:17:59 AM UTC 25
Finished Feb 09 04:18:25 AM UTC 25
Peak memory 253216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159645728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.159645728
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.1837839312
Short name T1062
Test name
Test status
Simulation time 263875397 ps
CPU time 5.37 seconds
Started Feb 09 04:49:31 AM UTC 25
Finished Feb 09 04:49:38 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837839312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1837839312
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3519860391
Short name T1072
Test name
Test status
Simulation time 3451920146 ps
CPU time 14.56 seconds
Started Feb 09 04:49:32 AM UTC 25
Finished Feb 09 04:49:47 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519860391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3519860391
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3196262441
Short name T1064
Test name
Test status
Simulation time 229821956 ps
CPU time 5.71 seconds
Started Feb 09 04:49:33 AM UTC 25
Finished Feb 09 04:49:40 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196262441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3196262441
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.1231368447
Short name T1070
Test name
Test status
Simulation time 3480359075 ps
CPU time 9.01 seconds
Started Feb 09 04:49:33 AM UTC 25
Finished Feb 09 04:49:43 AM UTC 25
Peak memory 253236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231368447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1231368447
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.2482963328
Short name T1066
Test name
Test status
Simulation time 148055207 ps
CPU time 6.2 seconds
Started Feb 09 04:49:33 AM UTC 25
Finished Feb 09 04:49:41 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482963328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2482963328
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3375785193
Short name T1077
Test name
Test status
Simulation time 3940927307 ps
CPU time 17.38 seconds
Started Feb 09 04:49:34 AM UTC 25
Finished Feb 09 04:49:53 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375785193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3375785193
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.378553650
Short name T1069
Test name
Test status
Simulation time 90955328 ps
CPU time 4.37 seconds
Started Feb 09 04:49:37 AM UTC 25
Finished Feb 09 04:49:43 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378553650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.378553650
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.2859255321
Short name T1068
Test name
Test status
Simulation time 113348209 ps
CPU time 4.06 seconds
Started Feb 09 04:49:37 AM UTC 25
Finished Feb 09 04:49:42 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859255321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2859255321
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.1589089138
Short name T67
Test name
Test status
Simulation time 449255243 ps
CPU time 5.85 seconds
Started Feb 09 04:49:37 AM UTC 25
Finished Feb 09 04:49:44 AM UTC 25
Peak memory 253376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589089138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1589089138
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.453731228
Short name T1093
Test name
Test status
Simulation time 3242974895 ps
CPU time 21.6 seconds
Started Feb 09 04:49:40 AM UTC 25
Finished Feb 09 04:50:03 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453731228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.453731228
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2633285850
Short name T1071
Test name
Test status
Simulation time 334276541 ps
CPU time 4.28 seconds
Started Feb 09 04:49:40 AM UTC 25
Finished Feb 09 04:49:46 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633285850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2633285850
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2552775541
Short name T1084
Test name
Test status
Simulation time 448313134 ps
CPU time 14.44 seconds
Started Feb 09 04:49:42 AM UTC 25
Finished Feb 09 04:49:58 AM UTC 25
Peak memory 251252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552775541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2552775541
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2532096799
Short name T204
Test name
Test status
Simulation time 334811194 ps
CPU time 5.06 seconds
Started Feb 09 04:49:42 AM UTC 25
Finished Feb 09 04:49:48 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532096799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2532096799
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3515984915
Short name T1091
Test name
Test status
Simulation time 484759022 ps
CPU time 17.26 seconds
Started Feb 09 04:49:42 AM UTC 25
Finished Feb 09 04:50:01 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515984915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3515984915
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.3984073846
Short name T1074
Test name
Test status
Simulation time 411291604 ps
CPU time 5.82 seconds
Started Feb 09 04:49:42 AM UTC 25
Finished Feb 09 04:49:49 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984073846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3984073846
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.3257207073
Short name T1092
Test name
Test status
Simulation time 494088441 ps
CPU time 18.22 seconds
Started Feb 09 04:49:44 AM UTC 25
Finished Feb 09 04:50:03 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257207073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3257207073
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.3061204176
Short name T1073
Test name
Test status
Simulation time 123112765 ps
CPU time 4.34 seconds
Started Feb 09 04:49:44 AM UTC 25
Finished Feb 09 04:49:49 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061204176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3061204176
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.3445760651
Short name T1079
Test name
Test status
Simulation time 1107607428 ps
CPU time 10.86 seconds
Started Feb 09 04:49:44 AM UTC 25
Finished Feb 09 04:49:56 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445760651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3445760651
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.927572615
Short name T1075
Test name
Test status
Simulation time 580823532 ps
CPU time 7.06 seconds
Started Feb 09 04:49:45 AM UTC 25
Finished Feb 09 04:49:53 AM UTC 25
Peak memory 253340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927572615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.927572615
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1974510166
Short name T1098
Test name
Test status
Simulation time 1085640288 ps
CPU time 20.89 seconds
Started Feb 09 04:49:45 AM UTC 25
Finished Feb 09 04:50:07 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974510166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1974510166
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2716388121
Short name T230
Test name
Test status
Simulation time 191519229 ps
CPU time 3.58 seconds
Started Feb 09 04:12:25 AM UTC 25
Finished Feb 09 04:12:30 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716388121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2716388121
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.612966852
Short name T104
Test name
Test status
Simulation time 201020962 ps
CPU time 6.22 seconds
Started Feb 09 04:12:10 AM UTC 25
Finished Feb 09 04:12:18 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612966852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.612966852
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.4148231948
Short name T98
Test name
Test status
Simulation time 376113207 ps
CPU time 4.29 seconds
Started Feb 09 04:12:19 AM UTC 25
Finished Feb 09 04:12:24 AM UTC 25
Peak memory 257128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148231948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.4148231948
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.3121896771
Short name T152
Test name
Test status
Simulation time 561718797 ps
CPU time 13.66 seconds
Started Feb 09 04:12:19 AM UTC 25
Finished Feb 09 04:12:33 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121896771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3121896771
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1360043595
Short name T128
Test name
Test status
Simulation time 1481907137 ps
CPU time 45.11 seconds
Started Feb 09 04:12:16 AM UTC 25
Finished Feb 09 04:13:03 AM UTC 25
Peak memory 253224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360043595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1360043595
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3162399300
Short name T180
Test name
Test status
Simulation time 1675168924 ps
CPU time 20.72 seconds
Started Feb 09 04:12:19 AM UTC 25
Finished Feb 09 04:12:41 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162399300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3162399300
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.966567859
Short name T126
Test name
Test status
Simulation time 1780792859 ps
CPU time 25.83 seconds
Started Feb 09 04:12:19 AM UTC 25
Finished Feb 09 04:12:46 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966567859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.966567859
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.1146075033
Short name T265
Test name
Test status
Simulation time 1710279924 ps
CPU time 40.59 seconds
Started Feb 09 04:12:13 AM UTC 25
Finished Feb 09 04:12:55 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146075033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1146075033
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.1751850113
Short name T231
Test name
Test status
Simulation time 691743397 ps
CPU time 11.38 seconds
Started Feb 09 04:12:19 AM UTC 25
Finished Feb 09 04:12:31 AM UTC 25
Peak memory 251300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751850113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1751850113
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.963577372
Short name T29
Test name
Test status
Simulation time 24088508563 ps
CPU time 232.45 seconds
Started Feb 09 04:12:24 AM UTC 25
Finished Feb 09 04:16:20 AM UTC 25
Peak memory 297572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963577372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.963577372
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.3704639778
Short name T19
Test name
Test status
Simulation time 5006173751 ps
CPU time 45.05 seconds
Started Feb 09 04:12:19 AM UTC 25
Finished Feb 09 04:13:05 AM UTC 25
Peak memory 253236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704639778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3704639778
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.210287622
Short name T567
Test name
Test status
Simulation time 91175870 ps
CPU time 2.49 seconds
Started Feb 09 04:18:34 AM UTC 25
Finished Feb 09 04:18:38 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210287622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.210287622
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.1330150082
Short name T569
Test name
Test status
Simulation time 364132701 ps
CPU time 21.72 seconds
Started Feb 09 04:18:17 AM UTC 25
Finished Feb 09 04:18:40 AM UTC 25
Peak memory 253236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330150082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1330150082
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.629565052
Short name T563
Test name
Test status
Simulation time 758228489 ps
CPU time 12.05 seconds
Started Feb 09 04:18:15 AM UTC 25
Finished Feb 09 04:18:28 AM UTC 25
Peak memory 251460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629565052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.629565052
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.2037459047
Short name T192
Test name
Test status
Simulation time 152520904 ps
CPU time 5.77 seconds
Started Feb 09 04:18:07 AM UTC 25
Finished Feb 09 04:18:14 AM UTC 25
Peak memory 251416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037459047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2037459047
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.2136864252
Short name T565
Test name
Test status
Simulation time 788323026 ps
CPU time 7 seconds
Started Feb 09 04:18:24 AM UTC 25
Finished Feb 09 04:18:32 AM UTC 25
Peak memory 251452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136864252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2136864252
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.1575932476
Short name T566
Test name
Test status
Simulation time 257684387 ps
CPU time 7.84 seconds
Started Feb 09 04:18:24 AM UTC 25
Finished Feb 09 04:18:33 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575932476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1575932476
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.774913056
Short name T116
Test name
Test status
Simulation time 7160216010 ps
CPU time 32.03 seconds
Started Feb 09 04:18:15 AM UTC 25
Finished Feb 09 04:18:49 AM UTC 25
Peak memory 251088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774913056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.774913056
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.502638964
Short name T277
Test name
Test status
Simulation time 760310896 ps
CPU time 25.31 seconds
Started Feb 09 04:18:15 AM UTC 25
Finished Feb 09 04:18:42 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502638964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.502638964
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.3493051636
Short name T568
Test name
Test status
Simulation time 361329370 ps
CPU time 11.78 seconds
Started Feb 09 04:18:26 AM UTC 25
Finished Feb 09 04:18:39 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493051636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3493051636
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.3561263619
Short name T562
Test name
Test status
Simulation time 381737693 ps
CPU time 14.65 seconds
Started Feb 09 04:18:06 AM UTC 25
Finished Feb 09 04:18:22 AM UTC 25
Peak memory 251112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561263619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3561263619
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.2405848249
Short name T587
Test name
Test status
Simulation time 12833250488 ps
CPU time 56.88 seconds
Started Feb 09 04:18:30 AM UTC 25
Finished Feb 09 04:19:28 AM UTC 25
Peak memory 251144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405848249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.2405848249
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2560461569
Short name T120
Test name
Test status
Simulation time 1262772816 ps
CPU time 26.37 seconds
Started Feb 09 04:18:26 AM UTC 25
Finished Feb 09 04:18:53 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560461569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2560461569
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.2475930438
Short name T1076
Test name
Test status
Simulation time 1668284849 ps
CPU time 5.93 seconds
Started Feb 09 04:49:46 AM UTC 25
Finished Feb 09 04:49:53 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475930438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2475930438
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2611774147
Short name T1082
Test name
Test status
Simulation time 1890090240 ps
CPU time 7.86 seconds
Started Feb 09 04:49:48 AM UTC 25
Finished Feb 09 04:49:57 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611774147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2611774147
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.777383083
Short name T1078
Test name
Test status
Simulation time 103427686 ps
CPU time 4.98 seconds
Started Feb 09 04:49:49 AM UTC 25
Finished Feb 09 04:49:55 AM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777383083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.777383083
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.323589751
Short name T1081
Test name
Test status
Simulation time 506078852 ps
CPU time 5.86 seconds
Started Feb 09 04:49:49 AM UTC 25
Finished Feb 09 04:49:56 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323589751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.323589751
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2535494748
Short name T205
Test name
Test status
Simulation time 2032881359 ps
CPU time 8.45 seconds
Started Feb 09 04:49:50 AM UTC 25
Finished Feb 09 04:50:00 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535494748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2535494748
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.1738845787
Short name T1085
Test name
Test status
Simulation time 438088139 ps
CPU time 6.03 seconds
Started Feb 09 04:49:51 AM UTC 25
Finished Feb 09 04:49:58 AM UTC 25
Peak memory 251256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738845787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1738845787
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.2345730175
Short name T1090
Test name
Test status
Simulation time 205723958 ps
CPU time 4.69 seconds
Started Feb 09 04:49:54 AM UTC 25
Finished Feb 09 04:50:00 AM UTC 25
Peak memory 251144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345730175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2345730175
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4176053172
Short name T1086
Test name
Test status
Simulation time 163544768 ps
CPU time 3.96 seconds
Started Feb 09 04:49:54 AM UTC 25
Finished Feb 09 04:49:59 AM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176053172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4176053172
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.2303004704
Short name T1089
Test name
Test status
Simulation time 229959067 ps
CPU time 4.4 seconds
Started Feb 09 04:49:54 AM UTC 25
Finished Feb 09 04:50:00 AM UTC 25
Peak memory 253324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303004704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2303004704
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2612333433
Short name T1097
Test name
Test status
Simulation time 2667931278 ps
CPU time 8.11 seconds
Started Feb 09 04:49:57 AM UTC 25
Finished Feb 09 04:50:07 AM UTC 25
Peak memory 253240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612333433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2612333433
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.2161274609
Short name T119
Test name
Test status
Simulation time 45854524 ps
CPU time 2.17 seconds
Started Feb 09 04:18:49 AM UTC 25
Finished Feb 09 04:18:53 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161274609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2161274609
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.109888695
Short name T573
Test name
Test status
Simulation time 1595034716 ps
CPU time 19.84 seconds
Started Feb 09 04:18:43 AM UTC 25
Finished Feb 09 04:19:04 AM UTC 25
Peak memory 257460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109888695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.109888695
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.907844204
Short name T578
Test name
Test status
Simulation time 308852294 ps
CPU time 22.37 seconds
Started Feb 09 04:18:43 AM UTC 25
Finished Feb 09 04:19:07 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907844204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.907844204
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.2397779651
Short name T118
Test name
Test status
Simulation time 1427292706 ps
CPU time 11.14 seconds
Started Feb 09 04:18:40 AM UTC 25
Finished Feb 09 04:18:52 AM UTC 25
Peak memory 257312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397779651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2397779651
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.1073747712
Short name T123
Test name
Test status
Simulation time 782361548 ps
CPU time 10.53 seconds
Started Feb 09 04:18:43 AM UTC 25
Finished Feb 09 04:18:55 AM UTC 25
Peak memory 257276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073747712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1073747712
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.1577754266
Short name T117
Test name
Test status
Simulation time 139160677 ps
CPU time 6.6 seconds
Started Feb 09 04:18:43 AM UTC 25
Finished Feb 09 04:18:51 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577754266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1577754266
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.3571452633
Short name T286
Test name
Test status
Simulation time 2211798949 ps
CPU time 33.01 seconds
Started Feb 09 04:18:38 AM UTC 25
Finished Feb 09 04:19:13 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571452633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3571452633
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.2071347012
Short name T572
Test name
Test status
Simulation time 332831232 ps
CPU time 11.87 seconds
Started Feb 09 04:18:34 AM UTC 25
Finished Feb 09 04:18:47 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071347012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2071347012
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.2816553999
Short name T121
Test name
Test status
Simulation time 228058297 ps
CPU time 10.04 seconds
Started Feb 09 04:18:43 AM UTC 25
Finished Feb 09 04:18:55 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816553999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2816553999
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.2611361270
Short name T571
Test name
Test status
Simulation time 689812779 ps
CPU time 10.02 seconds
Started Feb 09 04:18:34 AM UTC 25
Finished Feb 09 04:18:45 AM UTC 25
Peak memory 257320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611361270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2611361270
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.1429635232
Short name T586
Test name
Test status
Simulation time 4039183533 ps
CPU time 38.91 seconds
Started Feb 09 04:18:48 AM UTC 25
Finished Feb 09 04:19:28 AM UTC 25
Peak memory 251208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429635232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.1429635232
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.2955536568
Short name T579
Test name
Test status
Simulation time 9057765856 ps
CPU time 25.42 seconds
Started Feb 09 04:18:44 AM UTC 25
Finished Feb 09 04:19:10 AM UTC 25
Peak memory 253248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955536568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2955536568
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.2130696297
Short name T1094
Test name
Test status
Simulation time 344410534 ps
CPU time 4.52 seconds
Started Feb 09 04:49:57 AM UTC 25
Finished Feb 09 04:50:03 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130696297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2130696297
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1257103068
Short name T58
Test name
Test status
Simulation time 1491135976 ps
CPU time 6.98 seconds
Started Feb 09 04:49:57 AM UTC 25
Finished Feb 09 04:50:06 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257103068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1257103068
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.89358255
Short name T1096
Test name
Test status
Simulation time 186686087 ps
CPU time 5.49 seconds
Started Feb 09 04:49:57 AM UTC 25
Finished Feb 09 04:50:04 AM UTC 25
Peak memory 253372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89358255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.89358255
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1950224320
Short name T1095
Test name
Test status
Simulation time 649548456 ps
CPU time 5.31 seconds
Started Feb 09 04:49:57 AM UTC 25
Finished Feb 09 04:50:04 AM UTC 25
Peak memory 253144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950224320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1950224320
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3850087725
Short name T1101
Test name
Test status
Simulation time 563983624 ps
CPU time 5.8 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:09 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850087725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3850087725
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2393915177
Short name T1103
Test name
Test status
Simulation time 362047839 ps
CPU time 6.21 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:09 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393915177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2393915177
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.4047630315
Short name T1100
Test name
Test status
Simulation time 514420617 ps
CPU time 5.51 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:08 AM UTC 25
Peak memory 253368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047630315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.4047630315
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.4019007532
Short name T1105
Test name
Test status
Simulation time 2183025945 ps
CPU time 6.71 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:10 AM UTC 25
Peak memory 253308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019007532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.4019007532
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3753091588
Short name T1104
Test name
Test status
Simulation time 187740629 ps
CPU time 6.4 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:09 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753091588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3753091588
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2187060606
Short name T1099
Test name
Test status
Simulation time 241067728 ps
CPU time 4.14 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:07 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187060606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2187060606
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.2825708359
Short name T580
Test name
Test status
Simulation time 57259813 ps
CPU time 2.79 seconds
Started Feb 09 04:19:07 AM UTC 25
Finished Feb 09 04:19:11 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825708359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2825708359
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.3473976873
Short name T467
Test name
Test status
Simulation time 8342580880 ps
CPU time 26.17 seconds
Started Feb 09 04:18:56 AM UTC 25
Finished Feb 09 04:19:24 AM UTC 25
Peak memory 257408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473976873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3473976873
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.1421970590
Short name T423
Test name
Test status
Simulation time 1394860403 ps
CPU time 34.44 seconds
Started Feb 09 04:18:56 AM UTC 25
Finished Feb 09 04:19:32 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421970590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1421970590
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.2485531845
Short name T575
Test name
Test status
Simulation time 264925849 ps
CPU time 9.53 seconds
Started Feb 09 04:18:55 AM UTC 25
Finished Feb 09 04:19:05 AM UTC 25
Peak memory 251364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485531845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2485531845
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.429480436
Short name T34
Test name
Test status
Simulation time 148208640 ps
CPU time 4.55 seconds
Started Feb 09 04:18:52 AM UTC 25
Finished Feb 09 04:18:58 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429480436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.429480436
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2239729326
Short name T577
Test name
Test status
Simulation time 879459029 ps
CPU time 7.78 seconds
Started Feb 09 04:18:58 AM UTC 25
Finished Feb 09 04:19:07 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239729326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2239729326
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.13404865
Short name T507
Test name
Test status
Simulation time 379098481 ps
CPU time 8.63 seconds
Started Feb 09 04:19:04 AM UTC 25
Finished Feb 09 04:19:14 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13404865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.13404865
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.3376674969
Short name T419
Test name
Test status
Simulation time 357506378 ps
CPU time 10.85 seconds
Started Feb 09 04:18:53 AM UTC 25
Finished Feb 09 04:19:05 AM UTC 25
Peak memory 251068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376674969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3376674969
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.1528460725
Short name T576
Test name
Test status
Simulation time 694179903 ps
CPU time 12.25 seconds
Started Feb 09 04:18:53 AM UTC 25
Finished Feb 09 04:19:07 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528460725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1528460725
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.3561860511
Short name T582
Test name
Test status
Simulation time 385116344 ps
CPU time 11.12 seconds
Started Feb 09 04:19:06 AM UTC 25
Finished Feb 09 04:19:18 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561860511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3561860511
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.3853000611
Short name T574
Test name
Test status
Simulation time 401962405 ps
CPU time 13.16 seconds
Started Feb 09 04:18:51 AM UTC 25
Finished Feb 09 04:19:05 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853000611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3853000611
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.1132831151
Short name T581
Test name
Test status
Simulation time 368322606 ps
CPU time 6.68 seconds
Started Feb 09 04:19:06 AM UTC 25
Finished Feb 09 04:19:14 AM UTC 25
Peak memory 251244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132831151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.1132831151
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2378766540
Short name T15
Test name
Test status
Simulation time 62727556239 ps
CPU time 241.67 seconds
Started Feb 09 04:19:06 AM UTC 25
Finished Feb 09 04:23:11 AM UTC 25
Peak memory 267936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2378766540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_a
ll_with_rand_reset.2378766540
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.3665625251
Short name T591
Test name
Test status
Simulation time 2088623770 ps
CPU time 30.11 seconds
Started Feb 09 04:19:06 AM UTC 25
Finished Feb 09 04:19:38 AM UTC 25
Peak memory 257468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665625251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3665625251
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.458186133
Short name T1102
Test name
Test status
Simulation time 118499947 ps
CPU time 5.86 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:09 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458186133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.458186133
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3692036195
Short name T112
Test name
Test status
Simulation time 283713539 ps
CPU time 5.34 seconds
Started Feb 09 04:50:02 AM UTC 25
Finished Feb 09 04:50:09 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692036195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3692036195
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.4165784224
Short name T1107
Test name
Test status
Simulation time 167677508 ps
CPU time 4.93 seconds
Started Feb 09 04:50:05 AM UTC 25
Finished Feb 09 04:50:11 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165784224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.4165784224
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3452951149
Short name T1087
Test name
Test status
Simulation time 118023361 ps
CPU time 4.84 seconds
Started Feb 09 04:50:05 AM UTC 25
Finished Feb 09 04:50:11 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452951149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3452951149
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2851203179
Short name T1106
Test name
Test status
Simulation time 127483293 ps
CPU time 4.78 seconds
Started Feb 09 04:50:05 AM UTC 25
Finished Feb 09 04:50:11 AM UTC 25
Peak memory 251084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851203179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2851203179
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.983232560
Short name T1083
Test name
Test status
Simulation time 182371275 ps
CPU time 4.93 seconds
Started Feb 09 04:50:05 AM UTC 25
Finished Feb 09 04:50:11 AM UTC 25
Peak memory 251316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983232560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.983232560
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.3531085794
Short name T1061
Test name
Test status
Simulation time 259392592 ps
CPU time 5.55 seconds
Started Feb 09 04:50:07 AM UTC 25
Finished Feb 09 04:50:14 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531085794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3531085794
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1220587301
Short name T1108
Test name
Test status
Simulation time 136671567 ps
CPU time 3.94 seconds
Started Feb 09 04:50:09 AM UTC 25
Finished Feb 09 04:50:14 AM UTC 25
Peak memory 250852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220587301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1220587301
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3903581153
Short name T1117
Test name
Test status
Simulation time 2078918265 ps
CPU time 9.7 seconds
Started Feb 09 04:50:09 AM UTC 25
Finished Feb 09 04:50:20 AM UTC 25
Peak memory 250952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903581153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3903581153
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.626251460
Short name T589
Test name
Test status
Simulation time 103437947 ps
CPU time 2.45 seconds
Started Feb 09 04:19:30 AM UTC 25
Finished Feb 09 04:19:33 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626251460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.626251460
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.294683933
Short name T598
Test name
Test status
Simulation time 2608378409 ps
CPU time 39.79 seconds
Started Feb 09 04:19:14 AM UTC 25
Finished Feb 09 04:19:55 AM UTC 25
Peak memory 257536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294683933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.294683933
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.4124484263
Short name T597
Test name
Test status
Simulation time 3720933194 ps
CPU time 37.76 seconds
Started Feb 09 04:19:14 AM UTC 25
Finished Feb 09 04:19:53 AM UTC 25
Peak memory 257376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124484263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.4124484263
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.2908681802
Short name T35
Test name
Test status
Simulation time 1542980551 ps
CPU time 3.61 seconds
Started Feb 09 04:19:09 AM UTC 25
Finished Feb 09 04:19:14 AM UTC 25
Peak memory 251224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908681802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2908681802
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.870700455
Short name T227
Test name
Test status
Simulation time 26973862917 ps
CPU time 63.96 seconds
Started Feb 09 04:19:15 AM UTC 25
Finished Feb 09 04:20:21 AM UTC 25
Peak memory 267572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870700455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.870700455
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.1524632989
Short name T592
Test name
Test status
Simulation time 4612520679 ps
CPU time 18.78 seconds
Started Feb 09 04:19:20 AM UTC 25
Finished Feb 09 04:19:40 AM UTC 25
Peak memory 257324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524632989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1524632989
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.1154297144
Short name T585
Test name
Test status
Simulation time 295188167 ps
CPU time 9.98 seconds
Started Feb 09 04:19:12 AM UTC 25
Finished Feb 09 04:19:24 AM UTC 25
Peak memory 251328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154297144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1154297144
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.1030504191
Short name T583
Test name
Test status
Simulation time 454143738 ps
CPU time 6.62 seconds
Started Feb 09 04:19:11 AM UTC 25
Finished Feb 09 04:19:19 AM UTC 25
Peak memory 257184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030504191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1030504191
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.4203584256
Short name T588
Test name
Test status
Simulation time 232770319 ps
CPU time 7.17 seconds
Started Feb 09 04:19:20 AM UTC 25
Finished Feb 09 04:19:29 AM UTC 25
Peak memory 251008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203584256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.4203584256
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.2284226326
Short name T584
Test name
Test status
Simulation time 352991003 ps
CPU time 9.03 seconds
Started Feb 09 04:19:09 AM UTC 25
Finished Feb 09 04:19:19 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284226326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2284226326
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.1345322864
Short name T339
Test name
Test status
Simulation time 11473122398 ps
CPU time 118.87 seconds
Started Feb 09 04:19:25 AM UTC 25
Finished Feb 09 04:21:26 AM UTC 25
Peak memory 257252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345322864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.1345322864
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.516201353
Short name T347
Test name
Test status
Simulation time 1498641692895 ps
CPU time 2254.27 seconds
Started Feb 09 04:19:25 AM UTC 25
Finished Feb 09 04:57:23 AM UTC 25
Peak memory 347548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=516201353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_al
l_with_rand_reset.516201353
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.3719451525
Short name T590
Test name
Test status
Simulation time 7472941625 ps
CPU time 14.83 seconds
Started Feb 09 04:19:20 AM UTC 25
Finished Feb 09 04:19:36 AM UTC 25
Peak memory 253440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719451525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3719451525
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.2892994224
Short name T1088
Test name
Test status
Simulation time 284003342 ps
CPU time 3.26 seconds
Started Feb 09 04:50:09 AM UTC 25
Finished Feb 09 04:50:14 AM UTC 25
Peak memory 251272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892994224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2892994224
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.534471839
Short name T1109
Test name
Test status
Simulation time 336248638 ps
CPU time 5.07 seconds
Started Feb 09 04:50:09 AM UTC 25
Finished Feb 09 04:50:16 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534471839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.534471839
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.1628565015
Short name T1111
Test name
Test status
Simulation time 2066560105 ps
CPU time 7.19 seconds
Started Feb 09 04:50:09 AM UTC 25
Finished Feb 09 04:50:18 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628565015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1628565015
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.1793120871
Short name T114
Test name
Test status
Simulation time 149603192 ps
CPU time 5.13 seconds
Started Feb 09 04:50:11 AM UTC 25
Finished Feb 09 04:50:17 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793120871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1793120871
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3416273751
Short name T1112
Test name
Test status
Simulation time 257071747 ps
CPU time 5.96 seconds
Started Feb 09 04:50:11 AM UTC 25
Finished Feb 09 04:50:18 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416273751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3416273751
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.2435062534
Short name T1113
Test name
Test status
Simulation time 253236893 ps
CPU time 6.03 seconds
Started Feb 09 04:50:11 AM UTC 25
Finished Feb 09 04:50:18 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435062534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2435062534
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2342076495
Short name T1110
Test name
Test status
Simulation time 177082512 ps
CPU time 4.39 seconds
Started Feb 09 04:50:11 AM UTC 25
Finished Feb 09 04:50:16 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342076495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2342076495
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.1428593875
Short name T1114
Test name
Test status
Simulation time 196559814 ps
CPU time 6.21 seconds
Started Feb 09 04:50:11 AM UTC 25
Finished Feb 09 04:50:18 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428593875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1428593875
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.3226225944
Short name T1116
Test name
Test status
Simulation time 113469504 ps
CPU time 5.81 seconds
Started Feb 09 04:50:12 AM UTC 25
Finished Feb 09 04:50:20 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226225944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3226225944
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.3448208490
Short name T596
Test name
Test status
Simulation time 111166797 ps
CPU time 2.47 seconds
Started Feb 09 04:19:49 AM UTC 25
Finished Feb 09 04:19:52 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448208490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3448208490
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.779315687
Short name T594
Test name
Test status
Simulation time 382108334 ps
CPU time 4.61 seconds
Started Feb 09 04:19:37 AM UTC 25
Finished Feb 09 04:19:43 AM UTC 25
Peak memory 257332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779315687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.779315687
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.912384075
Short name T320
Test name
Test status
Simulation time 5213602809 ps
CPU time 21.52 seconds
Started Feb 09 04:19:37 AM UTC 25
Finished Feb 09 04:20:01 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912384075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.912384075
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.3593270159
Short name T606
Test name
Test status
Simulation time 4454611776 ps
CPU time 52.24 seconds
Started Feb 09 04:19:34 AM UTC 25
Finished Feb 09 04:20:28 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593270159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3593270159
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3113529299
Short name T193
Test name
Test status
Simulation time 1400733683 ps
CPU time 5.63 seconds
Started Feb 09 04:19:30 AM UTC 25
Finished Feb 09 04:19:36 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113529299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3113529299
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.987276800
Short name T226
Test name
Test status
Simulation time 2316455480 ps
CPU time 34.49 seconds
Started Feb 09 04:19:43 AM UTC 25
Finished Feb 09 04:20:19 AM UTC 25
Peak memory 257332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987276800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.987276800
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.2629274216
Short name T599
Test name
Test status
Simulation time 1392800782 ps
CPU time 34.94 seconds
Started Feb 09 04:19:43 AM UTC 25
Finished Feb 09 04:20:20 AM UTC 25
Peak memory 253156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629274216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2629274216
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.536265013
Short name T420
Test name
Test status
Simulation time 92977704 ps
CPU time 4.47 seconds
Started Feb 09 04:19:34 AM UTC 25
Finished Feb 09 04:19:40 AM UTC 25
Peak memory 251232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536265013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.536265013
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2407072027
Short name T122
Test name
Test status
Simulation time 987092834 ps
CPU time 18.6 seconds
Started Feb 09 04:19:34 AM UTC 25
Finished Feb 09 04:19:54 AM UTC 25
Peak memory 257372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407072027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2407072027
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.3759652013
Short name T595
Test name
Test status
Simulation time 194268136 ps
CPU time 3.2 seconds
Started Feb 09 04:19:43 AM UTC 25
Finished Feb 09 04:19:48 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759652013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3759652013
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.1624494706
Short name T593
Test name
Test status
Simulation time 3344751237 ps
CPU time 12.28 seconds
Started Feb 09 04:19:30 AM UTC 25
Finished Feb 09 04:19:43 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624494706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1624494706
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.2488549110
Short name T324
Test name
Test status
Simulation time 8015911418 ps
CPU time 30.66 seconds
Started Feb 09 04:19:44 AM UTC 25
Finished Feb 09 04:20:17 AM UTC 25
Peak memory 253192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488549110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.2488549110
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.3512596379
Short name T321
Test name
Test status
Simulation time 697868229 ps
CPU time 16.03 seconds
Started Feb 09 04:19:43 AM UTC 25
Finished Feb 09 04:20:01 AM UTC 25
Peak memory 257280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512596379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3512596379
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.718903561
Short name T1118
Test name
Test status
Simulation time 349142391 ps
CPU time 6.33 seconds
Started Feb 09 04:50:13 AM UTC 25
Finished Feb 09 04:50:20 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718903561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.718903561
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1084305223
Short name T1115
Test name
Test status
Simulation time 115785342 ps
CPU time 5.67 seconds
Started Feb 09 04:50:13 AM UTC 25
Finished Feb 09 04:50:20 AM UTC 25
Peak memory 253240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084305223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1084305223
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.4273090546
Short name T1119
Test name
Test status
Simulation time 165454560 ps
CPU time 6.32 seconds
Started Feb 09 04:50:14 AM UTC 25
Finished Feb 09 04:50:21 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273090546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.4273090546
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1119763927
Short name T206
Test name
Test status
Simulation time 167419428 ps
CPU time 4.32 seconds
Started Feb 09 04:50:15 AM UTC 25
Finished Feb 09 04:50:21 AM UTC 25
Peak memory 250952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119763927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1119763927
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1478620161
Short name T1121
Test name
Test status
Simulation time 492034594 ps
CPU time 5.76 seconds
Started Feb 09 04:50:15 AM UTC 25
Finished Feb 09 04:50:22 AM UTC 25
Peak memory 251300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478620161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1478620161
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3840101331
Short name T1122
Test name
Test status
Simulation time 190368194 ps
CPU time 5.74 seconds
Started Feb 09 04:50:15 AM UTC 25
Finished Feb 09 04:50:22 AM UTC 25
Peak memory 251012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840101331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3840101331
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.468008232
Short name T1120
Test name
Test status
Simulation time 175272187 ps
CPU time 4.04 seconds
Started Feb 09 04:50:16 AM UTC 25
Finished Feb 09 04:50:22 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468008232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.468008232
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.2442976383
Short name T1124
Test name
Test status
Simulation time 153352060 ps
CPU time 6.59 seconds
Started Feb 09 04:50:17 AM UTC 25
Finished Feb 09 04:50:25 AM UTC 25
Peak memory 253240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442976383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2442976383
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3300009507
Short name T1127
Test name
Test status
Simulation time 171790660 ps
CPU time 6.39 seconds
Started Feb 09 04:50:19 AM UTC 25
Finished Feb 09 04:50:27 AM UTC 25
Peak memory 253072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300009507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3300009507
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.3601696664
Short name T1123
Test name
Test status
Simulation time 92420008 ps
CPU time 5 seconds
Started Feb 09 04:50:19 AM UTC 25
Finished Feb 09 04:50:25 AM UTC 25
Peak memory 250984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601696664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3601696664
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.839875447
Short name T601
Test name
Test status
Simulation time 190021207 ps
CPU time 3.12 seconds
Started Feb 09 04:20:18 AM UTC 25
Finished Feb 09 04:20:22 AM UTC 25
Peak memory 251064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839875447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.839875447
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.3755686984
Short name T605
Test name
Test status
Simulation time 1327145136 ps
CPU time 27.29 seconds
Started Feb 09 04:19:58 AM UTC 25
Finished Feb 09 04:20:26 AM UTC 25
Peak memory 257272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755686984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3755686984
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.2156841934
Short name T424
Test name
Test status
Simulation time 2294125393 ps
CPU time 35.41 seconds
Started Feb 09 04:19:58 AM UTC 25
Finished Feb 09 04:20:34 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156841934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2156841934
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.3296221953
Short name T602
Test name
Test status
Simulation time 12921557698 ps
CPU time 23.95 seconds
Started Feb 09 04:19:58 AM UTC 25
Finished Feb 09 04:20:23 AM UTC 25
Peak memory 251232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296221953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3296221953
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.2970188742
Short name T63
Test name
Test status
Simulation time 173374921 ps
CPU time 6.86 seconds
Started Feb 09 04:19:53 AM UTC 25
Finished Feb 09 04:20:01 AM UTC 25
Peak memory 251260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970188742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2970188742
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.1558309335
Short name T228
Test name
Test status
Simulation time 1655321130 ps
CPU time 31.43 seconds
Started Feb 09 04:20:02 AM UTC 25
Finished Feb 09 04:20:35 AM UTC 25
Peak memory 255264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558309335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1558309335
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.3778694245
Short name T600
Test name
Test status
Simulation time 4216591340 ps
CPU time 16.98 seconds
Started Feb 09 04:20:02 AM UTC 25
Finished Feb 09 04:20:21 AM UTC 25
Peak memory 253224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778694245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3778694245
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.2171109189
Short name T322
Test name
Test status
Simulation time 400394370 ps
CPU time 15.95 seconds
Started Feb 09 04:19:56 AM UTC 25
Finished Feb 09 04:20:13 AM UTC 25
Peak memory 257124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171109189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2171109189
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.3527179075
Short name T323
Test name
Test status
Simulation time 2023934531 ps
CPU time 21.19 seconds
Started Feb 09 04:19:54 AM UTC 25
Finished Feb 09 04:20:17 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527179075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3527179075
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.4192622762
Short name T452
Test name
Test status
Simulation time 4581653445 ps
CPU time 20.38 seconds
Started Feb 09 04:20:03 AM UTC 25
Finished Feb 09 04:20:24 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192622762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.4192622762
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.1711318392
Short name T319
Test name
Test status
Simulation time 333193978 ps
CPU time 5.33 seconds
Started Feb 09 04:19:50 AM UTC 25
Finished Feb 09 04:19:56 AM UTC 25
Peak memory 257512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711318392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1711318392
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.4129756425
Short name T474
Test name
Test status
Simulation time 41537368006 ps
CPU time 285.2 seconds
Started Feb 09 04:20:14 AM UTC 25
Finished Feb 09 04:25:03 AM UTC 25
Peak memory 269692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129756425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.4129756425
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2732002328
Short name T608
Test name
Test status
Simulation time 5532052769 ps
CPU time 21.37 seconds
Started Feb 09 04:20:10 AM UTC 25
Finished Feb 09 04:20:32 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732002328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2732002328
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.1088175558
Short name T1130
Test name
Test status
Simulation time 2182855652 ps
CPU time 6.83 seconds
Started Feb 09 04:50:19 AM UTC 25
Finished Feb 09 04:50:27 AM UTC 25
Peak memory 253300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088175558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1088175558
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.157955012
Short name T1125
Test name
Test status
Simulation time 524474303 ps
CPU time 5.04 seconds
Started Feb 09 04:50:19 AM UTC 25
Finished Feb 09 04:50:26 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157955012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.157955012
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.21668471
Short name T1129
Test name
Test status
Simulation time 345999260 ps
CPU time 6.61 seconds
Started Feb 09 04:50:19 AM UTC 25
Finished Feb 09 04:50:27 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21668471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.21668471
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.90801097
Short name T1126
Test name
Test status
Simulation time 222240139 ps
CPU time 5.59 seconds
Started Feb 09 04:50:19 AM UTC 25
Finished Feb 09 04:50:26 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90801097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.90801097
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.782112313
Short name T1138
Test name
Test status
Simulation time 2243004448 ps
CPU time 10.16 seconds
Started Feb 09 04:50:20 AM UTC 25
Finished Feb 09 04:50:32 AM UTC 25
Peak memory 251360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782112313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.782112313
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.2438148851
Short name T1128
Test name
Test status
Simulation time 241623877 ps
CPU time 5.56 seconds
Started Feb 09 04:50:20 AM UTC 25
Finished Feb 09 04:50:27 AM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438148851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2438148851
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1248064778
Short name T1131
Test name
Test status
Simulation time 138951858 ps
CPU time 4.99 seconds
Started Feb 09 04:50:22 AM UTC 25
Finished Feb 09 04:50:28 AM UTC 25
Peak memory 253220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248064778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1248064778
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.4258781512
Short name T1133
Test name
Test status
Simulation time 177788952 ps
CPU time 5.6 seconds
Started Feb 09 04:50:22 AM UTC 25
Finished Feb 09 04:50:29 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258781512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.4258781512
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.4293229424
Short name T1132
Test name
Test status
Simulation time 230801514 ps
CPU time 5.3 seconds
Started Feb 09 04:50:22 AM UTC 25
Finished Feb 09 04:50:28 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293229424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.4293229424
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.197093338
Short name T1136
Test name
Test status
Simulation time 324511618 ps
CPU time 6.6 seconds
Started Feb 09 04:50:22 AM UTC 25
Finished Feb 09 04:50:30 AM UTC 25
Peak memory 253172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197093338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.197093338
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.4187527181
Short name T609
Test name
Test status
Simulation time 188896416 ps
CPU time 2.9 seconds
Started Feb 09 04:20:35 AM UTC 25
Finished Feb 09 04:20:39 AM UTC 25
Peak memory 250956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187527181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.4187527181
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.3887497724
Short name T73
Test name
Test status
Simulation time 430514185 ps
CPU time 18.31 seconds
Started Feb 09 04:20:23 AM UTC 25
Finished Feb 09 04:20:42 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887497724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3887497724
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.525295956
Short name T261
Test name
Test status
Simulation time 502509395 ps
CPU time 12.07 seconds
Started Feb 09 04:20:23 AM UTC 25
Finished Feb 09 04:20:36 AM UTC 25
Peak memory 251072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525295956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.525295956
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.2456881243
Short name T614
Test name
Test status
Simulation time 1410994029 ps
CPU time 25.42 seconds
Started Feb 09 04:20:21 AM UTC 25
Finished Feb 09 04:20:48 AM UTC 25
Peak memory 251360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456881243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2456881243
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.2738881830
Short name T42
Test name
Test status
Simulation time 1928701474 ps
CPU time 10.66 seconds
Started Feb 09 04:20:21 AM UTC 25
Finished Feb 09 04:20:33 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738881830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2738881830
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.810728859
Short name T252
Test name
Test status
Simulation time 946994491 ps
CPU time 35.79 seconds
Started Feb 09 04:20:24 AM UTC 25
Finished Feb 09 04:21:02 AM UTC 25
Peak memory 253336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810728859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.810728859
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.1999945231
Short name T615
Test name
Test status
Simulation time 1043243212 ps
CPU time 23.24 seconds
Started Feb 09 04:20:26 AM UTC 25
Finished Feb 09 04:20:50 AM UTC 25
Peak memory 257272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999945231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1999945231
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.397969682
Short name T607
Test name
Test status
Simulation time 139756111 ps
CPU time 7.12 seconds
Started Feb 09 04:20:21 AM UTC 25
Finished Feb 09 04:20:30 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397969682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.397969682
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.562618868
Short name T616
Test name
Test status
Simulation time 1351154649 ps
CPU time 28.5 seconds
Started Feb 09 04:20:21 AM UTC 25
Finished Feb 09 04:20:51 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562618868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.562618868
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.2273143356
Short name T613
Test name
Test status
Simulation time 3206008573 ps
CPU time 16.61 seconds
Started Feb 09 04:20:27 AM UTC 25
Finished Feb 09 04:20:45 AM UTC 25
Peak memory 257252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273143356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2273143356
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.2238310040
Short name T604
Test name
Test status
Simulation time 132857910 ps
CPU time 6.88 seconds
Started Feb 09 04:20:18 AM UTC 25
Finished Feb 09 04:20:26 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238310040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2238310040
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.662700045
Short name T111
Test name
Test status
Simulation time 30212803161 ps
CPU time 260.22 seconds
Started Feb 09 04:20:35 AM UTC 25
Finished Feb 09 04:24:58 AM UTC 25
Peak memory 273448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662700045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.662700045
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.2513080316
Short name T484
Test name
Test status
Simulation time 2004600933 ps
CPU time 31.31 seconds
Started Feb 09 04:20:27 AM UTC 25
Finished Feb 09 04:21:00 AM UTC 25
Peak memory 257276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513080316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2513080316
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1584001077
Short name T1134
Test name
Test status
Simulation time 155837827 ps
CPU time 4.09 seconds
Started Feb 09 04:50:23 AM UTC 25
Finished Feb 09 04:50:29 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584001077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1584001077
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.1817329344
Short name T1135
Test name
Test status
Simulation time 118857388 ps
CPU time 4.45 seconds
Started Feb 09 04:50:23 AM UTC 25
Finished Feb 09 04:50:29 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817329344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1817329344
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1550797070
Short name T1137
Test name
Test status
Simulation time 153680028 ps
CPU time 4.96 seconds
Started Feb 09 04:50:23 AM UTC 25
Finished Feb 09 04:50:30 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550797070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1550797070
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3694896019
Short name T1139
Test name
Test status
Simulation time 306935092 ps
CPU time 3.91 seconds
Started Feb 09 04:50:27 AM UTC 25
Finished Feb 09 04:50:33 AM UTC 25
Peak memory 250804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694896019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3694896019
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.4011502955
Short name T1141
Test name
Test status
Simulation time 292681213 ps
CPU time 6.07 seconds
Started Feb 09 04:50:27 AM UTC 25
Finished Feb 09 04:50:35 AM UTC 25
Peak memory 250836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011502955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.4011502955
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.1444845634
Short name T1140
Test name
Test status
Simulation time 1474710044 ps
CPU time 5.25 seconds
Started Feb 09 04:50:27 AM UTC 25
Finished Feb 09 04:50:34 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444845634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1444845634
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.4239495051
Short name T1142
Test name
Test status
Simulation time 177294274 ps
CPU time 6.16 seconds
Started Feb 09 04:50:27 AM UTC 25
Finished Feb 09 04:50:35 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239495051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.4239495051
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.2107841016
Short name T1143
Test name
Test status
Simulation time 446576497 ps
CPU time 5.19 seconds
Started Feb 09 04:50:29 AM UTC 25
Finished Feb 09 04:50:35 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107841016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2107841016
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.2821371660
Short name T1145
Test name
Test status
Simulation time 156914235 ps
CPU time 5.44 seconds
Started Feb 09 04:50:29 AM UTC 25
Finished Feb 09 04:50:36 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821371660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2821371660
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.264191440
Short name T1146
Test name
Test status
Simulation time 1568474507 ps
CPU time 5.49 seconds
Started Feb 09 04:50:29 AM UTC 25
Finished Feb 09 04:50:36 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264191440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.264191440
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2157555783
Short name T617
Test name
Test status
Simulation time 198027479 ps
CPU time 2.69 seconds
Started Feb 09 04:20:47 AM UTC 25
Finished Feb 09 04:20:51 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157555783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2157555783
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.372232568
Short name T619
Test name
Test status
Simulation time 1574855422 ps
CPU time 15.22 seconds
Started Feb 09 04:20:37 AM UTC 25
Finished Feb 09 04:20:53 AM UTC 25
Peak memory 251188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372232568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.372232568
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.3260888763
Short name T618
Test name
Test status
Simulation time 3387076314 ps
CPU time 13.45 seconds
Started Feb 09 04:20:37 AM UTC 25
Finished Feb 09 04:20:52 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260888763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3260888763
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.565439238
Short name T627
Test name
Test status
Simulation time 3331523932 ps
CPU time 38.09 seconds
Started Feb 09 04:20:37 AM UTC 25
Finished Feb 09 04:21:16 AM UTC 25
Peak memory 253316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565439238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.565439238
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.1754161613
Short name T610
Test name
Test status
Simulation time 107939274 ps
CPU time 3.33 seconds
Started Feb 09 04:20:35 AM UTC 25
Finished Feb 09 04:20:39 AM UTC 25
Peak memory 253372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754161613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1754161613
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.3670408826
Short name T229
Test name
Test status
Simulation time 16472757700 ps
CPU time 27.9 seconds
Started Feb 09 04:20:39 AM UTC 25
Finished Feb 09 04:21:08 AM UTC 25
Peak memory 255524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670408826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3670408826
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.2653609343
Short name T506
Test name
Test status
Simulation time 3593602413 ps
CPU time 93.11 seconds
Started Feb 09 04:20:40 AM UTC 25
Finished Feb 09 04:22:15 AM UTC 25
Peak memory 253432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653609343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2653609343
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.3483719923
Short name T176
Test name
Test status
Simulation time 12191552427 ps
CPU time 32.19 seconds
Started Feb 09 04:20:37 AM UTC 25
Finished Feb 09 04:21:10 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483719923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3483719923
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.2031131659
Short name T612
Test name
Test status
Simulation time 170181682 ps
CPU time 6.55 seconds
Started Feb 09 04:20:35 AM UTC 25
Finished Feb 09 04:20:42 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031131659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2031131659
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.4112312891
Short name T620
Test name
Test status
Simulation time 405175717 ps
CPU time 8.83 seconds
Started Feb 09 04:20:44 AM UTC 25
Finished Feb 09 04:20:54 AM UTC 25
Peak memory 251300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112312891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.4112312891
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.2296151361
Short name T611
Test name
Test status
Simulation time 139240574 ps
CPU time 6.41 seconds
Started Feb 09 04:20:35 AM UTC 25
Finished Feb 09 04:20:42 AM UTC 25
Peak memory 257316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296151361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2296151361
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.611957810
Short name T469
Test name
Test status
Simulation time 27243148895 ps
CPU time 169.31 seconds
Started Feb 09 04:20:46 AM UTC 25
Finished Feb 09 04:23:38 AM UTC 25
Peak memory 273748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611957810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.611957810
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.1525020477
Short name T508
Test name
Test status
Simulation time 125405155174 ps
CPU time 1912.5 seconds
Started Feb 09 04:20:44 AM UTC 25
Finished Feb 09 04:52:58 AM UTC 25
Peak memory 339580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1525020477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_a
ll_with_rand_reset.1525020477
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1264465716
Short name T622
Test name
Test status
Simulation time 461489231 ps
CPU time 14.55 seconds
Started Feb 09 04:20:44 AM UTC 25
Finished Feb 09 04:21:00 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264465716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1264465716
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.521900350
Short name T1147
Test name
Test status
Simulation time 511214629 ps
CPU time 6 seconds
Started Feb 09 04:50:29 AM UTC 25
Finished Feb 09 04:50:36 AM UTC 25
Peak memory 253144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521900350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.521900350
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2860646846
Short name T1144
Test name
Test status
Simulation time 210990453 ps
CPU time 3.93 seconds
Started Feb 09 04:50:30 AM UTC 25
Finished Feb 09 04:50:36 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860646846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2860646846
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.1730354589
Short name T1151
Test name
Test status
Simulation time 2288454352 ps
CPU time 7.82 seconds
Started Feb 09 04:50:30 AM UTC 25
Finished Feb 09 04:50:40 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730354589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1730354589
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.1519696214
Short name T1148
Test name
Test status
Simulation time 2359724439 ps
CPU time 5.36 seconds
Started Feb 09 04:50:30 AM UTC 25
Finished Feb 09 04:50:37 AM UTC 25
Peak memory 251448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519696214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1519696214
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.424306928
Short name T1154
Test name
Test status
Simulation time 2452518707 ps
CPU time 9.58 seconds
Started Feb 09 04:50:30 AM UTC 25
Finished Feb 09 04:50:42 AM UTC 25
Peak memory 251260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424306928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.424306928
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3785832146
Short name T1149
Test name
Test status
Simulation time 237014497 ps
CPU time 5.15 seconds
Started Feb 09 04:50:32 AM UTC 25
Finished Feb 09 04:50:39 AM UTC 25
Peak memory 252904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785832146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3785832146
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.4171833492
Short name T1150
Test name
Test status
Simulation time 276292617 ps
CPU time 6.23 seconds
Started Feb 09 04:50:32 AM UTC 25
Finished Feb 09 04:50:40 AM UTC 25
Peak memory 250852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171833492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.4171833492
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.1366458317
Short name T1153
Test name
Test status
Simulation time 2674638070 ps
CPU time 7.17 seconds
Started Feb 09 04:50:33 AM UTC 25
Finished Feb 09 04:50:42 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366458317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1366458317
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.1926920585
Short name T1152
Test name
Test status
Simulation time 94580497 ps
CPU time 5.2 seconds
Started Feb 09 04:50:34 AM UTC 25
Finished Feb 09 04:50:41 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926920585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1926920585
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.3879408401
Short name T625
Test name
Test status
Simulation time 64198998 ps
CPU time 2.77 seconds
Started Feb 09 04:21:10 AM UTC 25
Finished Feb 09 04:21:14 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879408401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3879408401
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.2677830806
Short name T477
Test name
Test status
Simulation time 16139415146 ps
CPU time 50.94 seconds
Started Feb 09 04:20:54 AM UTC 25
Finished Feb 09 04:21:47 AM UTC 25
Peak memory 257344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677830806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2677830806
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.1208996917
Short name T636
Test name
Test status
Simulation time 2350454486 ps
CPU time 46.86 seconds
Started Feb 09 04:20:54 AM UTC 25
Finished Feb 09 04:21:43 AM UTC 25
Peak memory 257244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208996917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1208996917
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2504337630
Short name T623
Test name
Test status
Simulation time 885210742 ps
CPU time 11.9 seconds
Started Feb 09 04:20:53 AM UTC 25
Finished Feb 09 04:21:06 AM UTC 25
Peak memory 251360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504337630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2504337630
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.2691849511
Short name T144
Test name
Test status
Simulation time 155169270 ps
CPU time 5.83 seconds
Started Feb 09 04:20:51 AM UTC 25
Finished Feb 09 04:20:58 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691849511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2691849511
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.648451407
Short name T640
Test name
Test status
Simulation time 4543540340 ps
CPU time 53.09 seconds
Started Feb 09 04:20:57 AM UTC 25
Finished Feb 09 04:21:51 AM UTC 25
Peak memory 269656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648451407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.648451407
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.1454494271
Short name T629
Test name
Test status
Simulation time 1539205907 ps
CPU time 29.23 seconds
Started Feb 09 04:20:59 AM UTC 25
Finished Feb 09 04:21:29 AM UTC 25
Peak memory 257244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454494271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1454494271
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.570446228
Short name T421
Test name
Test status
Simulation time 488393564 ps
CPU time 16.62 seconds
Started Feb 09 04:20:53 AM UTC 25
Finished Feb 09 04:21:11 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570446228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.570446228
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.4047962998
Short name T626
Test name
Test status
Simulation time 1728212891 ps
CPU time 20.18 seconds
Started Feb 09 04:20:53 AM UTC 25
Finished Feb 09 04:21:14 AM UTC 25
Peak memory 257524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047962998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.4047962998
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.1083032457
Short name T624
Test name
Test status
Simulation time 306036344 ps
CPU time 10.23 seconds
Started Feb 09 04:21:01 AM UTC 25
Finished Feb 09 04:21:13 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083032457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1083032457
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.1579025270
Short name T621
Test name
Test status
Simulation time 148917903 ps
CPU time 5.01 seconds
Started Feb 09 04:20:50 AM UTC 25
Finished Feb 09 04:20:56 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579025270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1579025270
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.429956022
Short name T380
Test name
Test status
Simulation time 105648406521 ps
CPU time 210.55 seconds
Started Feb 09 04:21:07 AM UTC 25
Finished Feb 09 04:24:41 AM UTC 25
Peak memory 273816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429956022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.429956022
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.4028706006
Short name T682
Test name
Test status
Simulation time 7318425760 ps
CPU time 140.82 seconds
Started Feb 09 04:21:01 AM UTC 25
Finished Feb 09 04:23:25 AM UTC 25
Peak memory 251392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028706006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.4028706006
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.3708508013
Short name T1157
Test name
Test status
Simulation time 457110962 ps
CPU time 6.79 seconds
Started Feb 09 04:50:35 AM UTC 25
Finished Feb 09 04:50:43 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708508013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3708508013
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.1076320360
Short name T1163
Test name
Test status
Simulation time 348809698 ps
CPU time 7.26 seconds
Started Feb 09 04:50:37 AM UTC 25
Finished Feb 09 04:50:45 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076320360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1076320360
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2552394019
Short name T1159
Test name
Test status
Simulation time 218034984 ps
CPU time 6.06 seconds
Started Feb 09 04:50:37 AM UTC 25
Finished Feb 09 04:50:44 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552394019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2552394019
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1911381507
Short name T1156
Test name
Test status
Simulation time 269332282 ps
CPU time 5.12 seconds
Started Feb 09 04:50:37 AM UTC 25
Finished Feb 09 04:50:43 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911381507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1911381507
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.480695997
Short name T1165
Test name
Test status
Simulation time 654725408 ps
CPU time 7.49 seconds
Started Feb 09 04:50:37 AM UTC 25
Finished Feb 09 04:50:46 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480695997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.480695997
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.870034186
Short name T1158
Test name
Test status
Simulation time 114326471 ps
CPU time 5.76 seconds
Started Feb 09 04:50:37 AM UTC 25
Finished Feb 09 04:50:44 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870034186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.870034186
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3934291557
Short name T1164
Test name
Test status
Simulation time 2094729161 ps
CPU time 7.24 seconds
Started Feb 09 04:50:37 AM UTC 25
Finished Feb 09 04:50:45 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934291557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3934291557
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1825687257
Short name T1160
Test name
Test status
Simulation time 1683641860 ps
CPU time 5.21 seconds
Started Feb 09 04:50:38 AM UTC 25
Finished Feb 09 04:50:44 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825687257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1825687257
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2793689525
Short name T1161
Test name
Test status
Simulation time 119970218 ps
CPU time 5.47 seconds
Started Feb 09 04:50:38 AM UTC 25
Finished Feb 09 04:50:45 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793689525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2793689525
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.3830453637
Short name T1166
Test name
Test status
Simulation time 181020731 ps
CPU time 6.64 seconds
Started Feb 09 04:50:39 AM UTC 25
Finished Feb 09 04:50:47 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830453637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.3830453637
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.465920321
Short name T634
Test name
Test status
Simulation time 213636634 ps
CPU time 2.96 seconds
Started Feb 09 04:21:32 AM UTC 25
Finished Feb 09 04:21:36 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465920321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.465920321
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.53548713
Short name T631
Test name
Test status
Simulation time 571724811 ps
CPU time 14.23 seconds
Started Feb 09 04:21:15 AM UTC 25
Finished Feb 09 04:21:31 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53548713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.53548713
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.2918854839
Short name T603
Test name
Test status
Simulation time 2483416697 ps
CPU time 42.61 seconds
Started Feb 09 04:21:15 AM UTC 25
Finished Feb 09 04:21:59 AM UTC 25
Peak memory 257368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918854839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2918854839
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.2929511350
Short name T632
Test name
Test status
Simulation time 729330614 ps
CPU time 17.79 seconds
Started Feb 09 04:21:14 AM UTC 25
Finished Feb 09 04:21:33 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929511350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2929511350
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.1703620081
Short name T59
Test name
Test status
Simulation time 1994367154 ps
CPU time 8.76 seconds
Started Feb 09 04:21:12 AM UTC 25
Finished Feb 09 04:21:22 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703620081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1703620081
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3507757269
Short name T635
Test name
Test status
Simulation time 1131384724 ps
CPU time 22.21 seconds
Started Feb 09 04:21:18 AM UTC 25
Finished Feb 09 04:21:41 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507757269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3507757269
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.1086364114
Short name T639
Test name
Test status
Simulation time 1258430265 ps
CPU time 25.1 seconds
Started Feb 09 04:21:21 AM UTC 25
Finished Feb 09 04:21:47 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086364114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1086364114
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.3452901051
Short name T159
Test name
Test status
Simulation time 562360383 ps
CPU time 5.57 seconds
Started Feb 09 04:21:14 AM UTC 25
Finished Feb 09 04:21:20 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452901051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.3452901051
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.528597393
Short name T633
Test name
Test status
Simulation time 1774832174 ps
CPU time 22.33 seconds
Started Feb 09 04:21:12 AM UTC 25
Finished Feb 09 04:21:36 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528597393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.528597393
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.120762130
Short name T630
Test name
Test status
Simulation time 127410365 ps
CPU time 6.14 seconds
Started Feb 09 04:21:22 AM UTC 25
Finished Feb 09 04:21:29 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120762130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.120762130
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.2062488865
Short name T628
Test name
Test status
Simulation time 344841093 ps
CPU time 7.52 seconds
Started Feb 09 04:21:12 AM UTC 25
Finished Feb 09 04:21:21 AM UTC 25
Peak memory 251112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062488865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2062488865
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.2437422447
Short name T404
Test name
Test status
Simulation time 18719022200 ps
CPU time 235.49 seconds
Started Feb 09 04:21:32 AM UTC 25
Finished Feb 09 04:25:31 AM UTC 25
Peak memory 323196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437422447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.2437422447
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.693308106
Short name T637
Test name
Test status
Simulation time 2136656649 ps
CPU time 19.23 seconds
Started Feb 09 04:21:24 AM UTC 25
Finished Feb 09 04:21:45 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693308106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.693308106
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3869171798
Short name T1162
Test name
Test status
Simulation time 120653001 ps
CPU time 4.42 seconds
Started Feb 09 04:50:39 AM UTC 25
Finished Feb 09 04:50:45 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869171798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3869171798
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.104845337
Short name T1168
Test name
Test status
Simulation time 542587826 ps
CPU time 6.06 seconds
Started Feb 09 04:50:40 AM UTC 25
Finished Feb 09 04:50:48 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104845337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.104845337
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.1977413576
Short name T1167
Test name
Test status
Simulation time 409413856 ps
CPU time 4.62 seconds
Started Feb 09 04:50:42 AM UTC 25
Finished Feb 09 04:50:47 AM UTC 25
Peak memory 251032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977413576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1977413576
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3095887578
Short name T1170
Test name
Test status
Simulation time 578048013 ps
CPU time 6.2 seconds
Started Feb 09 04:50:42 AM UTC 25
Finished Feb 09 04:50:49 AM UTC 25
Peak memory 250812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095887578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3095887578
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.17504710
Short name T1172
Test name
Test status
Simulation time 182898297 ps
CPU time 4.43 seconds
Started Feb 09 04:50:44 AM UTC 25
Finished Feb 09 04:50:50 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17504710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.17504710
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.2091039809
Short name T1171
Test name
Test status
Simulation time 158696739 ps
CPU time 4.23 seconds
Started Feb 09 04:50:44 AM UTC 25
Finished Feb 09 04:50:49 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091039809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.2091039809
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3099021195
Short name T1173
Test name
Test status
Simulation time 163007562 ps
CPU time 5.85 seconds
Started Feb 09 04:50:44 AM UTC 25
Finished Feb 09 04:50:51 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099021195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3099021195
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.567461569
Short name T1169
Test name
Test status
Simulation time 124704653 ps
CPU time 3.87 seconds
Started Feb 09 04:50:44 AM UTC 25
Finished Feb 09 04:50:49 AM UTC 25
Peak memory 253404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567461569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.567461569
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1489740666
Short name T1174
Test name
Test status
Simulation time 1657970313 ps
CPU time 7.13 seconds
Started Feb 09 04:50:44 AM UTC 25
Finished Feb 09 04:50:52 AM UTC 25
Peak memory 253240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489740666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1489740666
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3712808546
Short name T207
Test name
Test status
Simulation time 232012009 ps
CPU time 3.92 seconds
Started Feb 09 04:50:46 AM UTC 25
Finished Feb 09 04:50:51 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712808546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3712808546
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.4116754665
Short name T510
Test name
Test status
Simulation time 145301197 ps
CPU time 2.79 seconds
Started Feb 09 04:12:57 AM UTC 25
Finished Feb 09 04:13:01 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116754665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.4116754665
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.1432497022
Short name T142
Test name
Test status
Simulation time 2119802561 ps
CPU time 40.27 seconds
Started Feb 09 04:12:34 AM UTC 25
Finished Feb 09 04:13:16 AM UTC 25
Peak memory 251392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432497022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1432497022
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.2767792686
Short name T141
Test name
Test status
Simulation time 331724001 ps
CPU time 11.38 seconds
Started Feb 09 04:12:42 AM UTC 25
Finished Feb 09 04:12:55 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767792686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2767792686
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.1461328009
Short name T8
Test name
Test status
Simulation time 4837256088 ps
CPU time 47.77 seconds
Started Feb 09 04:12:41 AM UTC 25
Finished Feb 09 04:13:30 AM UTC 25
Peak memory 259460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461328009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1461328009
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.2226661064
Short name T238
Test name
Test status
Simulation time 3706584829 ps
CPU time 7.53 seconds
Started Feb 09 04:12:40 AM UTC 25
Finished Feb 09 04:12:48 AM UTC 25
Peak memory 251432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226661064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2226661064
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3182610151
Short name T53
Test name
Test status
Simulation time 120044980 ps
CPU time 6.74 seconds
Started Feb 09 04:12:32 AM UTC 25
Finished Feb 09 04:12:40 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182610151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3182610151
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.760905444
Short name T509
Test name
Test status
Simulation time 245879904 ps
CPU time 6.58 seconds
Started Feb 09 04:12:35 AM UTC 25
Finished Feb 09 04:12:43 AM UTC 25
Peak memory 250736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760905444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.760905444
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.4078816930
Short name T129
Test name
Test status
Simulation time 1522482133 ps
CPU time 26.65 seconds
Started Feb 09 04:12:35 AM UTC 25
Finished Feb 09 04:13:03 AM UTC 25
Peak memory 250752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078816930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.4078816930
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.4131488780
Short name T232
Test name
Test status
Simulation time 4476146289 ps
CPU time 22.94 seconds
Started Feb 09 04:12:49 AM UTC 25
Finished Feb 09 04:13:13 AM UTC 25
Peak memory 251240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131488780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.4131488780
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.2351369206
Short name T267
Test name
Test status
Simulation time 173708760611 ps
CPU time 248.1 seconds
Started Feb 09 04:12:55 AM UTC 25
Finished Feb 09 04:17:07 AM UTC 25
Peak memory 297704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351369206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2351369206
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2863889449
Short name T301
Test name
Test status
Simulation time 6528072227 ps
CPU time 24.66 seconds
Started Feb 09 04:12:30 AM UTC 25
Finished Feb 09 04:12:56 AM UTC 25
Peak memory 251436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863889449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2863889449
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.1863170057
Short name T255
Test name
Test status
Simulation time 7048429632 ps
CPU time 33.86 seconds
Started Feb 09 04:12:54 AM UTC 25
Finished Feb 09 04:13:29 AM UTC 25
Peak memory 251220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863170057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.1863170057
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3807770887
Short name T340
Test name
Test status
Simulation time 77256976733 ps
CPU time 1934 seconds
Started Feb 09 04:12:49 AM UTC 25
Finished Feb 09 04:45:24 AM UTC 25
Peak memory 446116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3807770887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_al
l_with_rand_reset.3807770887
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.216437664
Short name T642
Test name
Test status
Simulation time 100684674 ps
CPU time 2.53 seconds
Started Feb 09 04:21:50 AM UTC 25
Finished Feb 09 04:21:53 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216437664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.216437664
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1829354711
Short name T486
Test name
Test status
Simulation time 477231248 ps
CPU time 8.7 seconds
Started Feb 09 04:21:42 AM UTC 25
Finished Feb 09 04:21:52 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829354711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1829354711
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.2589326963
Short name T645
Test name
Test status
Simulation time 832308822 ps
CPU time 15.66 seconds
Started Feb 09 04:21:42 AM UTC 25
Finished Feb 09 04:21:59 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589326963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2589326963
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2884919133
Short name T641
Test name
Test status
Simulation time 426279792 ps
CPU time 9.46 seconds
Started Feb 09 04:21:42 AM UTC 25
Finished Feb 09 04:21:53 AM UTC 25
Peak memory 257252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884919133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2884919133
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.3324380263
Short name T64
Test name
Test status
Simulation time 254764009 ps
CPU time 6.75 seconds
Started Feb 09 04:21:34 AM UTC 25
Finished Feb 09 04:21:42 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324380263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3324380263
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.370609272
Short name T253
Test name
Test status
Simulation time 8631134653 ps
CPU time 54.56 seconds
Started Feb 09 04:21:42 AM UTC 25
Finished Feb 09 04:22:38 AM UTC 25
Peak memory 267608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370609272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.370609272
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.2054468955
Short name T473
Test name
Test status
Simulation time 619513086 ps
CPU time 24.16 seconds
Started Feb 09 04:21:47 AM UTC 25
Finished Feb 09 04:22:13 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054468955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2054468955
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.1993574936
Short name T468
Test name
Test status
Simulation time 3442107902 ps
CPU time 18.91 seconds
Started Feb 09 04:21:42 AM UTC 25
Finished Feb 09 04:22:02 AM UTC 25
Peak memory 253160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993574936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1993574936
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3320805883
Short name T643
Test name
Test status
Simulation time 1653351276 ps
CPU time 13.54 seconds
Started Feb 09 04:21:40 AM UTC 25
Finished Feb 09 04:21:55 AM UTC 25
Peak memory 257244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320805883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3320805883
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.2786241805
Short name T644
Test name
Test status
Simulation time 459638298 ps
CPU time 9.37 seconds
Started Feb 09 04:21:47 AM UTC 25
Finished Feb 09 04:21:58 AM UTC 25
Peak memory 257448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786241805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2786241805
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.3940383300
Short name T638
Test name
Test status
Simulation time 482273579 ps
CPU time 11.36 seconds
Started Feb 09 04:21:32 AM UTC 25
Finished Feb 09 04:21:45 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940383300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3940383300
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.2224632717
Short name T403
Test name
Test status
Simulation time 17762394801 ps
CPU time 137.34 seconds
Started Feb 09 04:21:50 AM UTC 25
Finished Feb 09 04:24:09 AM UTC 25
Peak memory 267528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224632717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.2224632717
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.2604475275
Short name T663
Test name
Test status
Simulation time 14892820670 ps
CPU time 55.27 seconds
Started Feb 09 04:21:47 AM UTC 25
Finished Feb 09 04:22:44 AM UTC 25
Peak memory 253440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604475275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2604475275
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.3119454222
Short name T652
Test name
Test status
Simulation time 571993859 ps
CPU time 5.82 seconds
Started Feb 09 04:22:12 AM UTC 25
Finished Feb 09 04:22:19 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119454222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3119454222
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.2821665410
Short name T650
Test name
Test status
Simulation time 1022690574 ps
CPU time 12.91 seconds
Started Feb 09 04:21:59 AM UTC 25
Finished Feb 09 04:22:13 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821665410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2821665410
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.4237624837
Short name T464
Test name
Test status
Simulation time 545957934 ps
CPU time 25.8 seconds
Started Feb 09 04:21:56 AM UTC 25
Finished Feb 09 04:22:23 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237624837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.4237624837
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.2768030340
Short name T194
Test name
Test status
Simulation time 452746561 ps
CPU time 5.54 seconds
Started Feb 09 04:21:54 AM UTC 25
Finished Feb 09 04:22:00 AM UTC 25
Peak memory 251416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768030340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2768030340
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.4013604904
Short name T653
Test name
Test status
Simulation time 477761288 ps
CPU time 17.99 seconds
Started Feb 09 04:22:01 AM UTC 25
Finished Feb 09 04:22:21 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013604904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.4013604904
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.3678167823
Short name T649
Test name
Test status
Simulation time 211629590 ps
CPU time 9.72 seconds
Started Feb 09 04:22:01 AM UTC 25
Finished Feb 09 04:22:12 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678167823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3678167823
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1731692879
Short name T160
Test name
Test status
Simulation time 473883396 ps
CPU time 8.8 seconds
Started Feb 09 04:21:54 AM UTC 25
Finished Feb 09 04:22:04 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731692879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1731692879
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.4059574177
Short name T647
Test name
Test status
Simulation time 1911959028 ps
CPU time 15.64 seconds
Started Feb 09 04:21:54 AM UTC 25
Finished Feb 09 04:22:10 AM UTC 25
Peak memory 257436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059574177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.4059574177
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.3357290674
Short name T648
Test name
Test status
Simulation time 206924489 ps
CPU time 6.66 seconds
Started Feb 09 04:22:04 AM UTC 25
Finished Feb 09 04:22:12 AM UTC 25
Peak memory 251000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357290674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3357290674
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.172903434
Short name T646
Test name
Test status
Simulation time 878118176 ps
CPU time 7.49 seconds
Started Feb 09 04:21:54 AM UTC 25
Finished Feb 09 04:22:02 AM UTC 25
Peak memory 251208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172903434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.otp_ctrl_smoke.172903434
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.677823855
Short name T498
Test name
Test status
Simulation time 12824056285 ps
CPU time 190.23 seconds
Started Feb 09 04:22:11 AM UTC 25
Finished Feb 09 04:25:25 AM UTC 25
Peak memory 267860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677823855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.677823855
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3899291119
Short name T156
Test name
Test status
Simulation time 58008686211 ps
CPU time 822.54 seconds
Started Feb 09 04:22:05 AM UTC 25
Finished Feb 09 04:35:57 AM UTC 25
Peak memory 267936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3899291119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_a
ll_with_rand_reset.3899291119
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.60736242
Short name T655
Test name
Test status
Simulation time 2155607818 ps
CPU time 23.99 seconds
Started Feb 09 04:22:04 AM UTC 25
Finished Feb 09 04:22:29 AM UTC 25
Peak memory 253268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60736242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.60736242
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.1359731792
Short name T659
Test name
Test status
Simulation time 62927991 ps
CPU time 2.66 seconds
Started Feb 09 04:22:31 AM UTC 25
Finished Feb 09 04:22:35 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359731792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1359731792
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.828073430
Short name T86
Test name
Test status
Simulation time 1630221033 ps
CPU time 45.69 seconds
Started Feb 09 04:22:21 AM UTC 25
Finished Feb 09 04:23:08 AM UTC 25
Peak memory 257268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828073430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.828073430
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.1351943895
Short name T664
Test name
Test status
Simulation time 369865256 ps
CPU time 26.3 seconds
Started Feb 09 04:22:21 AM UTC 25
Finished Feb 09 04:22:48 AM UTC 25
Peak memory 253404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351943895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1351943895
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.234195249
Short name T475
Test name
Test status
Simulation time 1006875114 ps
CPU time 39.91 seconds
Started Feb 09 04:22:20 AM UTC 25
Finished Feb 09 04:23:02 AM UTC 25
Peak memory 251424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234195249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.234195249
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.3384493217
Short name T65
Test name
Test status
Simulation time 139347837 ps
CPU time 6.63 seconds
Started Feb 09 04:22:20 AM UTC 25
Finished Feb 09 04:22:28 AM UTC 25
Peak memory 251188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384493217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3384493217
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.1265803106
Short name T658
Test name
Test status
Simulation time 374182929 ps
CPU time 12.28 seconds
Started Feb 09 04:22:21 AM UTC 25
Finished Feb 09 04:22:34 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265803106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1265803106
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.730724822
Short name T485
Test name
Test status
Simulation time 12888940770 ps
CPU time 37.32 seconds
Started Feb 09 04:22:22 AM UTC 25
Finished Feb 09 04:23:01 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730724822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.730724822
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.212722817
Short name T654
Test name
Test status
Simulation time 221631236 ps
CPU time 5.52 seconds
Started Feb 09 04:22:20 AM UTC 25
Finished Feb 09 04:22:27 AM UTC 25
Peak memory 251208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212722817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.212722817
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.509216825
Short name T660
Test name
Test status
Simulation time 794092773 ps
CPU time 16.99 seconds
Started Feb 09 04:22:20 AM UTC 25
Finished Feb 09 04:22:39 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509216825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.509216825
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.2959431559
Short name T657
Test name
Test status
Simulation time 143240269 ps
CPU time 6.13 seconds
Started Feb 09 04:22:25 AM UTC 25
Finished Feb 09 04:22:32 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959431559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2959431559
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.1714950912
Short name T656
Test name
Test status
Simulation time 173060042 ps
CPU time 8.01 seconds
Started Feb 09 04:22:20 AM UTC 25
Finished Feb 09 04:22:30 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714950912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1714950912
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1978968390
Short name T481
Test name
Test status
Simulation time 18071357652 ps
CPU time 245.93 seconds
Started Feb 09 04:22:31 AM UTC 25
Finished Feb 09 04:26:40 AM UTC 25
Peak memory 288160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978968390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1978968390
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.570038750
Short name T26
Test name
Test status
Simulation time 88813109640 ps
CPU time 521.44 seconds
Started Feb 09 04:22:29 AM UTC 25
Finished Feb 09 04:31:17 AM UTC 25
Peak memory 300544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=570038750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_al
l_with_rand_reset.570038750
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.1384445713
Short name T665
Test name
Test status
Simulation time 443099576 ps
CPU time 21.19 seconds
Started Feb 09 04:22:28 AM UTC 25
Finished Feb 09 04:22:50 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384445713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1384445713
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.4125127667
Short name T671
Test name
Test status
Simulation time 82018046 ps
CPU time 2.39 seconds
Started Feb 09 04:23:00 AM UTC 25
Finished Feb 09 04:23:04 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125127667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.4125127667
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3420517013
Short name T93
Test name
Test status
Simulation time 1160617633 ps
CPU time 29.74 seconds
Started Feb 09 04:22:45 AM UTC 25
Finished Feb 09 04:23:16 AM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420517013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3420517013
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.555369797
Short name T428
Test name
Test status
Simulation time 594836828 ps
CPU time 20.31 seconds
Started Feb 09 04:22:43 AM UTC 25
Finished Feb 09 04:23:05 AM UTC 25
Peak memory 251200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555369797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.555369797
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.190180077
Short name T686
Test name
Test status
Simulation time 3437732298 ps
CPU time 49.77 seconds
Started Feb 09 04:22:40 AM UTC 25
Finished Feb 09 04:23:32 AM UTC 25
Peak memory 257604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190180077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.190180077
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2780971189
Short name T661
Test name
Test status
Simulation time 322680674 ps
CPU time 5.82 seconds
Started Feb 09 04:22:35 AM UTC 25
Finished Feb 09 04:22:42 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780971189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2780971189
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.2748504999
Short name T666
Test name
Test status
Simulation time 1279407655 ps
CPU time 11.25 seconds
Started Feb 09 04:22:46 AM UTC 25
Finished Feb 09 04:22:58 AM UTC 25
Peak memory 257340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748504999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2748504999
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.57622410
Short name T678
Test name
Test status
Simulation time 1836945663 ps
CPU time 26.79 seconds
Started Feb 09 04:22:50 AM UTC 25
Finished Feb 09 04:23:18 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57622410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.57622410
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.2545133250
Short name T289
Test name
Test status
Simulation time 222178966 ps
CPU time 9.73 seconds
Started Feb 09 04:22:40 AM UTC 25
Finished Feb 09 04:22:51 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545133250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2545133250
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.1281763281
Short name T465
Test name
Test status
Simulation time 702759296 ps
CPU time 25.64 seconds
Started Feb 09 04:22:35 AM UTC 25
Finished Feb 09 04:23:02 AM UTC 25
Peak memory 251012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281763281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1281763281
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.959507378
Short name T668
Test name
Test status
Simulation time 594422535 ps
CPU time 8.12 seconds
Started Feb 09 04:22:52 AM UTC 25
Finished Feb 09 04:23:01 AM UTC 25
Peak memory 251048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959507378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.959507378
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.2220393367
Short name T662
Test name
Test status
Simulation time 2262590967 ps
CPU time 9.24 seconds
Started Feb 09 04:22:33 AM UTC 25
Finished Feb 09 04:22:44 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220393367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2220393367
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.1596541167
Short name T479
Test name
Test status
Simulation time 16248779543 ps
CPU time 178.64 seconds
Started Feb 09 04:22:59 AM UTC 25
Finished Feb 09 04:26:01 AM UTC 25
Peak memory 257480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596541167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.1596541167
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.2138229383
Short name T667
Test name
Test status
Simulation time 1165041130 ps
CPU time 6.04 seconds
Started Feb 09 04:22:52 AM UTC 25
Finished Feb 09 04:22:59 AM UTC 25
Peak memory 251328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138229383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2138229383
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.3413123551
Short name T680
Test name
Test status
Simulation time 106981657 ps
CPU time 2.5 seconds
Started Feb 09 04:23:18 AM UTC 25
Finished Feb 09 04:23:21 AM UTC 25
Peak memory 251228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413123551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3413123551
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.2600881682
Short name T674
Test name
Test status
Simulation time 182266577 ps
CPU time 6.08 seconds
Started Feb 09 04:23:07 AM UTC 25
Finished Feb 09 04:23:14 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600881682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.2600881682
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.3945130591
Short name T688
Test name
Test status
Simulation time 1034381077 ps
CPU time 31.99 seconds
Started Feb 09 04:23:05 AM UTC 25
Finished Feb 09 04:23:39 AM UTC 25
Peak memory 251420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945130591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3945130591
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.68886633
Short name T679
Test name
Test status
Simulation time 7141734414 ps
CPU time 13.97 seconds
Started Feb 09 04:23:05 AM UTC 25
Finished Feb 09 04:23:20 AM UTC 25
Peak memory 253228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68886633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.68886633
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.152818763
Short name T673
Test name
Test status
Simulation time 310875669 ps
CPU time 5.68 seconds
Started Feb 09 04:23:03 AM UTC 25
Finished Feb 09 04:23:09 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152818763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.152818763
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.369584667
Short name T677
Test name
Test status
Simulation time 326212817 ps
CPU time 7.23 seconds
Started Feb 09 04:23:09 AM UTC 25
Finished Feb 09 04:23:18 AM UTC 25
Peak memory 257304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369584667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.369584667
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.2420479640
Short name T694
Test name
Test status
Simulation time 3252071900 ps
CPU time 39.09 seconds
Started Feb 09 04:23:09 AM UTC 25
Finished Feb 09 04:23:50 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420479640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2420479640
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.621071027
Short name T675
Test name
Test status
Simulation time 2559543872 ps
CPU time 8.12 seconds
Started Feb 09 04:23:05 AM UTC 25
Finished Feb 09 04:23:14 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621071027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.621071027
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.4143297438
Short name T676
Test name
Test status
Simulation time 810985120 ps
CPU time 11.16 seconds
Started Feb 09 04:23:05 AM UTC 25
Finished Feb 09 04:23:17 AM UTC 25
Peak memory 257504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143297438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.4143297438
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.133227665
Short name T681
Test name
Test status
Simulation time 666729137 ps
CPU time 11.52 seconds
Started Feb 09 04:23:11 AM UTC 25
Finished Feb 09 04:23:23 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133227665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.133227665
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.939171233
Short name T672
Test name
Test status
Simulation time 135861706 ps
CPU time 5.1 seconds
Started Feb 09 04:23:02 AM UTC 25
Finished Feb 09 04:23:09 AM UTC 25
Peak memory 251144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939171233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.otp_ctrl_smoke.939171233
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2748972048
Short name T24
Test name
Test status
Simulation time 14322415484 ps
CPU time 431.89 seconds
Started Feb 09 04:23:15 AM UTC 25
Finished Feb 09 04:30:33 AM UTC 25
Peak memory 273916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2748972048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_a
ll_with_rand_reset.2748972048
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.383676237
Short name T696
Test name
Test status
Simulation time 6143891976 ps
CPU time 38.35 seconds
Started Feb 09 04:23:13 AM UTC 25
Finished Feb 09 04:23:53 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383676237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.383676237
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.3297257979
Short name T690
Test name
Test status
Simulation time 622127635 ps
CPU time 2.68 seconds
Started Feb 09 04:23:38 AM UTC 25
Finished Feb 09 04:23:42 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297257979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3297257979
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.2792195001
Short name T693
Test name
Test status
Simulation time 660613322 ps
CPU time 22.57 seconds
Started Feb 09 04:23:24 AM UTC 25
Finished Feb 09 04:23:48 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792195001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2792195001
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.1851648655
Short name T470
Test name
Test status
Simulation time 2935444963 ps
CPU time 33.55 seconds
Started Feb 09 04:23:23 AM UTC 25
Finished Feb 09 04:23:58 AM UTC 25
Peak memory 253564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851648655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1851648655
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.3121402331
Short name T691
Test name
Test status
Simulation time 2470028398 ps
CPU time 14.21 seconds
Started Feb 09 04:23:28 AM UTC 25
Finished Feb 09 04:23:43 AM UTC 25
Peak memory 257280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121402331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3121402331
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.2565556096
Short name T383
Test name
Test status
Simulation time 25977056272 ps
CPU time 81.37 seconds
Started Feb 09 04:23:28 AM UTC 25
Finished Feb 09 04:24:51 AM UTC 25
Peak memory 253312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565556096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.2565556096
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.814344699
Short name T684
Test name
Test status
Simulation time 373709559 ps
CPU time 5.73 seconds
Started Feb 09 04:23:22 AM UTC 25
Finished Feb 09 04:23:29 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814344699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.814344699
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.3266971134
Short name T687
Test name
Test status
Simulation time 697950561 ps
CPU time 15.83 seconds
Started Feb 09 04:23:20 AM UTC 25
Finished Feb 09 04:23:37 AM UTC 25
Peak memory 257244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266971134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3266971134
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.3457470743
Short name T689
Test name
Test status
Simulation time 174500500 ps
CPU time 8.44 seconds
Started Feb 09 04:23:30 AM UTC 25
Finished Feb 09 04:23:40 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457470743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3457470743
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.4219439974
Short name T685
Test name
Test status
Simulation time 724540370 ps
CPU time 8.14 seconds
Started Feb 09 04:23:19 AM UTC 25
Finished Feb 09 04:23:29 AM UTC 25
Peak memory 251028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219439974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.otp_ctrl_smoke.4219439974
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.315486945
Short name T704
Test name
Test status
Simulation time 10235667912 ps
CPU time 44.59 seconds
Started Feb 09 04:23:36 AM UTC 25
Finished Feb 09 04:24:22 AM UTC 25
Peak memory 253300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315486945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.315486945
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1219793954
Short name T385
Test name
Test status
Simulation time 264421232882 ps
CPU time 1548.29 seconds
Started Feb 09 04:23:33 AM UTC 25
Finished Feb 09 04:49:39 AM UTC 25
Peak memory 325116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1219793954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_a
ll_with_rand_reset.1219793954
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.4182994287
Short name T692
Test name
Test status
Simulation time 665991348 ps
CPU time 14.09 seconds
Started Feb 09 04:23:30 AM UTC 25
Finished Feb 09 04:23:46 AM UTC 25
Peak memory 253304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182994287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.4182994287
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.2053096641
Short name T700
Test name
Test status
Simulation time 38586530 ps
CPU time 2.29 seconds
Started Feb 09 04:24:02 AM UTC 25
Finished Feb 09 04:24:05 AM UTC 25
Peak memory 250744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053096641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2053096641
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.902273889
Short name T699
Test name
Test status
Simulation time 1045610283 ps
CPU time 12.61 seconds
Started Feb 09 04:23:50 AM UTC 25
Finished Feb 09 04:24:03 AM UTC 25
Peak memory 257332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902273889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.902273889
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.2967850925
Short name T701
Test name
Test status
Simulation time 1268568822 ps
CPU time 19.3 seconds
Started Feb 09 04:23:46 AM UTC 25
Finished Feb 09 04:24:07 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967850925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2967850925
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.3464329514
Short name T750
Test name
Test status
Simulation time 12297198052 ps
CPU time 171.61 seconds
Started Feb 09 04:23:44 AM UTC 25
Finished Feb 09 04:26:39 AM UTC 25
Peak memory 251424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464329514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3464329514
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3176425633
Short name T44
Test name
Test status
Simulation time 624777476 ps
CPU time 6.25 seconds
Started Feb 09 04:23:43 AM UTC 25
Finished Feb 09 04:23:50 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176425633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3176425633
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.2689150504
Short name T669
Test name
Test status
Simulation time 7366961930 ps
CPU time 15.61 seconds
Started Feb 09 04:23:52 AM UTC 25
Finished Feb 09 04:24:09 AM UTC 25
Peak memory 253216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689150504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2689150504
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3391814411
Short name T707
Test name
Test status
Simulation time 2528567419 ps
CPU time 38.21 seconds
Started Feb 09 04:23:52 AM UTC 25
Finished Feb 09 04:24:32 AM UTC 25
Peak memory 253428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391814411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3391814411
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3006795445
Short name T455
Test name
Test status
Simulation time 4230948054 ps
CPU time 16.64 seconds
Started Feb 09 04:23:43 AM UTC 25
Finished Feb 09 04:24:01 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006795445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3006795445
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.1514499795
Short name T670
Test name
Test status
Simulation time 8731544822 ps
CPU time 28.37 seconds
Started Feb 09 04:23:43 AM UTC 25
Finished Feb 09 04:24:12 AM UTC 25
Peak memory 251360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514499795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1514499795
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.3597668462
Short name T697
Test name
Test status
Simulation time 265092201 ps
CPU time 7.65 seconds
Started Feb 09 04:23:52 AM UTC 25
Finished Feb 09 04:24:01 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597668462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3597668462
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.3214146645
Short name T695
Test name
Test status
Simulation time 630775406 ps
CPU time 6.26 seconds
Started Feb 09 04:23:43 AM UTC 25
Finished Feb 09 04:23:50 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214146645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3214146645
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.2391574304
Short name T405
Test name
Test status
Simulation time 7121255555 ps
CPU time 133.88 seconds
Started Feb 09 04:24:02 AM UTC 25
Finished Feb 09 04:26:18 AM UTC 25
Peak memory 263148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391574304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.2391574304
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.2458081936
Short name T698
Test name
Test status
Simulation time 654494918 ps
CPU time 6.69 seconds
Started Feb 09 04:23:55 AM UTC 25
Finished Feb 09 04:24:02 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458081936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2458081936
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.2307875510
Short name T377
Test name
Test status
Simulation time 200526262 ps
CPU time 2.22 seconds
Started Feb 09 04:24:30 AM UTC 25
Finished Feb 09 04:24:33 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307875510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2307875510
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.2283827516
Short name T379
Test name
Test status
Simulation time 1923730364 ps
CPU time 27.11 seconds
Started Feb 09 04:24:11 AM UTC 25
Finished Feb 09 04:24:40 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283827516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2283827516
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.3285882243
Short name T703
Test name
Test status
Simulation time 1861722006 ps
CPU time 10.03 seconds
Started Feb 09 04:24:09 AM UTC 25
Finished Feb 09 04:24:20 AM UTC 25
Peak memory 251452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285882243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3285882243
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.4136612064
Short name T651
Test name
Test status
Simulation time 463128916 ps
CPU time 5.32 seconds
Started Feb 09 04:24:04 AM UTC 25
Finished Feb 09 04:24:11 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136612064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.4136612064
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.3057335254
Short name T706
Test name
Test status
Simulation time 809343154 ps
CPU time 14.3 seconds
Started Feb 09 04:24:14 AM UTC 25
Finished Feb 09 04:24:29 AM UTC 25
Peak memory 253372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057335254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3057335254
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.4280219857
Short name T378
Test name
Test status
Simulation time 3417434360 ps
CPU time 15.94 seconds
Started Feb 09 04:24:19 AM UTC 25
Finished Feb 09 04:24:36 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280219857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.4280219857
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.3656702052
Short name T284
Test name
Test status
Simulation time 652750953 ps
CPU time 25.21 seconds
Started Feb 09 04:24:08 AM UTC 25
Finished Feb 09 04:24:35 AM UTC 25
Peak memory 257504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656702052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3656702052
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.889408685
Short name T683
Test name
Test status
Simulation time 371767834 ps
CPU time 9.92 seconds
Started Feb 09 04:24:06 AM UTC 25
Finished Feb 09 04:24:18 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889408685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.889408685
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.258660460
Short name T705
Test name
Test status
Simulation time 258620250 ps
CPU time 6.71 seconds
Started Feb 09 04:24:19 AM UTC 25
Finished Feb 09 04:24:27 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258660460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.258660460
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.4012155041
Short name T702
Test name
Test status
Simulation time 474906622 ps
CPU time 14.12 seconds
Started Feb 09 04:24:03 AM UTC 25
Finished Feb 09 04:24:18 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012155041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.otp_ctrl_smoke.4012155041
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.3935807643
Short name T406
Test name
Test status
Simulation time 65154754914 ps
CPU time 392.52 seconds
Started Feb 09 04:24:28 AM UTC 25
Finished Feb 09 04:31:05 AM UTC 25
Peak memory 275744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935807643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.3935807643
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.4132222370
Short name T21
Test name
Test status
Simulation time 24803782052 ps
CPU time 306.08 seconds
Started Feb 09 04:24:24 AM UTC 25
Finished Feb 09 04:29:34 AM UTC 25
Peak memory 267768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4132222370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_a
ll_with_rand_reset.4132222370
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.1179357855
Short name T711
Test name
Test status
Simulation time 1817750883 ps
CPU time 41.92 seconds
Started Feb 09 04:24:21 AM UTC 25
Finished Feb 09 04:25:05 AM UTC 25
Peak memory 257276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179357855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1179357855
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.2099513501
Short name T713
Test name
Test status
Simulation time 659970645 ps
CPU time 2.41 seconds
Started Feb 09 04:25:04 AM UTC 25
Finished Feb 09 04:25:08 AM UTC 25
Peak memory 250820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099513501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2099513501
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.396512386
Short name T487
Test name
Test status
Simulation time 1674616150 ps
CPU time 26.02 seconds
Started Feb 09 04:24:45 AM UTC 25
Finished Feb 09 04:25:12 AM UTC 25
Peak memory 257268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396512386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.396512386
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.743873540
Short name T714
Test name
Test status
Simulation time 669039172 ps
CPU time 27.42 seconds
Started Feb 09 04:24:41 AM UTC 25
Finished Feb 09 04:25:09 AM UTC 25
Peak memory 253376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743873540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.743873540
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.3041415640
Short name T712
Test name
Test status
Simulation time 2316259911 ps
CPU time 28.75 seconds
Started Feb 09 04:24:37 AM UTC 25
Finished Feb 09 04:25:07 AM UTC 25
Peak memory 251284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041415640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3041415640
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.48048574
Short name T381
Test name
Test status
Simulation time 1440721896 ps
CPU time 5.91 seconds
Started Feb 09 04:24:36 AM UTC 25
Finished Feb 09 04:24:43 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48048574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.48048574
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.306151053
Short name T710
Test name
Test status
Simulation time 1412979883 ps
CPU time 16.74 seconds
Started Feb 09 04:24:45 AM UTC 25
Finished Feb 09 04:25:03 AM UTC 25
Peak memory 253400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306151053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.306151053
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.2240157125
Short name T500
Test name
Test status
Simulation time 602872191 ps
CPU time 31.38 seconds
Started Feb 09 04:24:45 AM UTC 25
Finished Feb 09 04:25:17 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240157125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2240157125
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.3679044955
Short name T709
Test name
Test status
Simulation time 1277282844 ps
CPU time 23.7 seconds
Started Feb 09 04:24:36 AM UTC 25
Finished Feb 09 04:25:01 AM UTC 25
Peak memory 257440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679044955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3679044955
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.2134945881
Short name T708
Test name
Test status
Simulation time 261178396 ps
CPU time 8.72 seconds
Started Feb 09 04:24:45 AM UTC 25
Finished Feb 09 04:24:55 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134945881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2134945881
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3079681816
Short name T382
Test name
Test status
Simulation time 314599482 ps
CPU time 8.69 seconds
Started Feb 09 04:24:33 AM UTC 25
Finished Feb 09 04:24:43 AM UTC 25
Peak memory 257320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079681816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3079681816
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.56345727
Short name T761
Test name
Test status
Simulation time 4804542917 ps
CPU time 107.62 seconds
Started Feb 09 04:25:04 AM UTC 25
Finished Feb 09 04:26:54 AM UTC 25
Peak memory 255200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56345727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.56345727
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.30992470
Short name T329
Test name
Test status
Simulation time 99007690793 ps
CPU time 1265.09 seconds
Started Feb 09 04:24:56 AM UTC 25
Finished Feb 09 04:46:15 AM UTC 25
Peak memory 552640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=30992470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
_with_rand_reset.30992470
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.2402497495
Short name T715
Test name
Test status
Simulation time 3226687315 ps
CPU time 22.37 seconds
Started Feb 09 04:24:52 AM UTC 25
Finished Feb 09 04:25:16 AM UTC 25
Peak memory 253440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402497495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2402497495
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.1843631344
Short name T721
Test name
Test status
Simulation time 1170459751 ps
CPU time 4.23 seconds
Started Feb 09 04:25:21 AM UTC 25
Finished Feb 09 04:25:26 AM UTC 25
Peak memory 251012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843631344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1843631344
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.1188026491
Short name T245
Test name
Test status
Simulation time 5872633611 ps
CPU time 23.04 seconds
Started Feb 09 04:25:11 AM UTC 25
Finished Feb 09 04:25:36 AM UTC 25
Peak memory 257404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188026491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1188026491
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1532501537
Short name T244
Test name
Test status
Simulation time 351512181 ps
CPU time 23.84 seconds
Started Feb 09 04:25:10 AM UTC 25
Finished Feb 09 04:25:35 AM UTC 25
Peak memory 251064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532501537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1532501537
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.161206585
Short name T734
Test name
Test status
Simulation time 5358558341 ps
CPU time 57.47 seconds
Started Feb 09 04:25:10 AM UTC 25
Finished Feb 09 04:26:09 AM UTC 25
Peak memory 253380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161206585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.161206585
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.1672493895
Short name T199
Test name
Test status
Simulation time 215946329 ps
CPU time 5.05 seconds
Started Feb 09 04:25:04 AM UTC 25
Finished Feb 09 04:25:11 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672493895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1672493895
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.2039608840
Short name T719
Test name
Test status
Simulation time 461268332 ps
CPU time 11.11 seconds
Started Feb 09 04:25:11 AM UTC 25
Finished Feb 09 04:25:24 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039608840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2039608840
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.2435474652
Short name T718
Test name
Test status
Simulation time 252695942 ps
CPU time 8.8 seconds
Started Feb 09 04:25:13 AM UTC 25
Finished Feb 09 04:25:23 AM UTC 25
Peak memory 253168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435474652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2435474652
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.1146669153
Short name T722
Test name
Test status
Simulation time 302492121 ps
CPU time 16.74 seconds
Started Feb 09 04:25:10 AM UTC 25
Finished Feb 09 04:25:28 AM UTC 25
Peak memory 253064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146669153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1146669153
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.4039742436
Short name T717
Test name
Test status
Simulation time 2540735606 ps
CPU time 9.3 seconds
Started Feb 09 04:25:10 AM UTC 25
Finished Feb 09 04:25:20 AM UTC 25
Peak memory 257192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039742436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.4039742436
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.1732492419
Short name T720
Test name
Test status
Simulation time 184871740 ps
CPU time 7.62 seconds
Started Feb 09 04:25:16 AM UTC 25
Finished Feb 09 04:25:25 AM UTC 25
Peak memory 257252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732492419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1732492419
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.3964745609
Short name T716
Test name
Test status
Simulation time 494846216 ps
CPU time 11.07 seconds
Started Feb 09 04:25:04 AM UTC 25
Finished Feb 09 04:25:17 AM UTC 25
Peak memory 257488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964745609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3964745609
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3040237556
Short name T723
Test name
Test status
Simulation time 452144811 ps
CPU time 9.64 seconds
Started Feb 09 04:25:20 AM UTC 25
Finished Feb 09 04:25:30 AM UTC 25
Peak memory 251080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040237556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3040237556
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.975494780
Short name T755
Test name
Test status
Simulation time 33103716147 ps
CPU time 83.42 seconds
Started Feb 09 04:25:18 AM UTC 25
Finished Feb 09 04:26:43 AM UTC 25
Peak memory 253004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975494780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.975494780
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.2503775891
Short name T256
Test name
Test status
Simulation time 576515387 ps
CPU time 3.12 seconds
Started Feb 09 04:13:26 AM UTC 25
Finished Feb 09 04:13:30 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503775891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2503775891
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1136658816
Short name T143
Test name
Test status
Simulation time 2164279944 ps
CPU time 44.11 seconds
Started Feb 09 04:13:04 AM UTC 25
Finished Feb 09 04:13:50 AM UTC 25
Peak memory 251328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136658816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1136658816
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1785924492
Short name T48
Test name
Test status
Simulation time 1332825401 ps
CPU time 23.25 seconds
Started Feb 09 04:13:14 AM UTC 25
Finished Feb 09 04:13:38 AM UTC 25
Peak memory 257276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785924492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1785924492
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2865004542
Short name T181
Test name
Test status
Simulation time 868557037 ps
CPU time 12.92 seconds
Started Feb 09 04:13:11 AM UTC 25
Finished Feb 09 04:13:25 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865004542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2865004542
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.2213461529
Short name T258
Test name
Test status
Simulation time 1606911868 ps
CPU time 48.07 seconds
Started Feb 09 04:13:09 AM UTC 25
Finished Feb 09 04:13:59 AM UTC 25
Peak memory 253228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213461529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2213461529
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.2636854516
Short name T185
Test name
Test status
Simulation time 523710306 ps
CPU time 6.2 seconds
Started Feb 09 04:13:02 AM UTC 25
Finished Feb 09 04:13:10 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636854516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2636854516
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.352590254
Short name T182
Test name
Test status
Simulation time 2037693976 ps
CPU time 9.84 seconds
Started Feb 09 04:13:16 AM UTC 25
Finished Feb 09 04:13:28 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352590254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.352590254
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.1063072155
Short name T236
Test name
Test status
Simulation time 6311303247 ps
CPU time 17.64 seconds
Started Feb 09 04:13:16 AM UTC 25
Finished Feb 09 04:13:35 AM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063072155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1063072155
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.2164510541
Short name T233
Test name
Test status
Simulation time 270243058 ps
CPU time 9.61 seconds
Started Feb 09 04:13:07 AM UTC 25
Finished Feb 09 04:13:18 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164510541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2164510541
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2727431262
Short name T234
Test name
Test status
Simulation time 493705079 ps
CPU time 15.53 seconds
Started Feb 09 04:13:05 AM UTC 25
Finished Feb 09 04:13:21 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727431262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2727431262
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.1511619582
Short name T235
Test name
Test status
Simulation time 183692081 ps
CPU time 8.92 seconds
Started Feb 09 04:13:16 AM UTC 25
Finished Feb 09 04:13:27 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511619582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1511619582
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.3565078051
Short name T268
Test name
Test status
Simulation time 43402627035 ps
CPU time 218.26 seconds
Started Feb 09 04:13:26 AM UTC 25
Finished Feb 09 04:17:08 AM UTC 25
Peak memory 297636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565078051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3565078051
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1957730903
Short name T511
Test name
Test status
Simulation time 296255420 ps
CPU time 10.5 seconds
Started Feb 09 04:12:57 AM UTC 25
Finished Feb 09 04:13:09 AM UTC 25
Peak memory 251180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957730903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1957730903
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1031124659
Short name T341
Test name
Test status
Simulation time 260454384855 ps
CPU time 2504.53 seconds
Started Feb 09 04:13:19 AM UTC 25
Finished Feb 09 04:55:29 AM UTC 25
Peak memory 521856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1031124659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_al
l_with_rand_reset.1031124659
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.3876354999
Short name T237
Test name
Test status
Simulation time 1096729318 ps
CPU time 32.51 seconds
Started Feb 09 04:13:17 AM UTC 25
Finished Feb 09 04:13:51 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876354999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3876354999
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.2816592830
Short name T724
Test name
Test status
Simulation time 129325052 ps
CPU time 2.91 seconds
Started Feb 09 04:25:46 AM UTC 25
Finished Feb 09 04:25:50 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816592830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2816592830
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1225536725
Short name T251
Test name
Test status
Simulation time 1142971375 ps
CPU time 9.89 seconds
Started Feb 09 04:25:37 AM UTC 25
Finished Feb 09 04:25:48 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225536725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1225536725
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.2528782059
Short name T737
Test name
Test status
Simulation time 3633350826 ps
CPU time 40.89 seconds
Started Feb 09 04:25:31 AM UTC 25
Finished Feb 09 04:26:13 AM UTC 25
Peak memory 255220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528782059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2528782059
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.2044073377
Short name T249
Test name
Test status
Simulation time 7043041017 ps
CPU time 14.26 seconds
Started Feb 09 04:25:31 AM UTC 25
Finished Feb 09 04:25:46 AM UTC 25
Peak memory 253284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044073377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2044073377
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.3033153519
Short name T172
Test name
Test status
Simulation time 1962856751 ps
CPU time 5.94 seconds
Started Feb 09 04:25:25 AM UTC 25
Finished Feb 09 04:25:32 AM UTC 25
Peak memory 251328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033153519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3033153519
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.3597757112
Short name T254
Test name
Test status
Simulation time 923102806 ps
CPU time 34.17 seconds
Started Feb 09 04:25:37 AM UTC 25
Finished Feb 09 04:26:13 AM UTC 25
Peak memory 255200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597757112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3597757112
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.2402991044
Short name T729
Test name
Test status
Simulation time 852677889 ps
CPU time 20.01 seconds
Started Feb 09 04:25:37 AM UTC 25
Finished Feb 09 04:25:58 AM UTC 25
Peak memory 257272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402991044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2402991044
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.3555001239
Short name T250
Test name
Test status
Simulation time 1113785907 ps
CPU time 15.76 seconds
Started Feb 09 04:25:31 AM UTC 25
Finished Feb 09 04:25:48 AM UTC 25
Peak memory 250736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555001239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3555001239
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.2875911829
Short name T725
Test name
Test status
Simulation time 1725450547 ps
CPU time 20.22 seconds
Started Feb 09 04:25:31 AM UTC 25
Finished Feb 09 04:25:52 AM UTC 25
Peak memory 252680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875911829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2875911829
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.219753851
Short name T247
Test name
Test status
Simulation time 215803111 ps
CPU time 7 seconds
Started Feb 09 04:25:37 AM UTC 25
Finished Feb 09 04:25:45 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219753851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.219753851
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.1536016748
Short name T243
Test name
Test status
Simulation time 646312861 ps
CPU time 8.81 seconds
Started Feb 09 04:25:24 AM UTC 25
Finished Feb 09 04:25:34 AM UTC 25
Peak memory 251304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536016748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1536016748
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.91900080
Short name T139
Test name
Test status
Simulation time 23549015423 ps
CPU time 295.47 seconds
Started Feb 09 04:25:43 AM UTC 25
Finished Feb 09 04:30:43 AM UTC 25
Peak memory 274016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91900080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ba
se_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.91900080
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1390918355
Short name T318
Test name
Test status
Simulation time 28349950554 ps
CPU time 411.12 seconds
Started Feb 09 04:25:37 AM UTC 25
Finished Feb 09 04:32:34 AM UTC 25
Peak memory 267772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1390918355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_a
ll_with_rand_reset.1390918355
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2270124134
Short name T248
Test name
Test status
Simulation time 241179106 ps
CPU time 7.23 seconds
Started Feb 09 04:25:37 AM UTC 25
Finished Feb 09 04:25:46 AM UTC 25
Peak memory 257344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270124134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2270124134
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1845083799
Short name T736
Test name
Test status
Simulation time 475643328 ps
CPU time 4.22 seconds
Started Feb 09 04:26:06 AM UTC 25
Finished Feb 09 04:26:11 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845083799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1845083799
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.1961994696
Short name T732
Test name
Test status
Simulation time 305945116 ps
CPU time 12.23 seconds
Started Feb 09 04:25:53 AM UTC 25
Finished Feb 09 04:26:06 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961994696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1961994696
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.2388031885
Short name T740
Test name
Test status
Simulation time 688452482 ps
CPU time 27.89 seconds
Started Feb 09 04:25:52 AM UTC 25
Finished Feb 09 04:26:21 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388031885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2388031885
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.3947135770
Short name T730
Test name
Test status
Simulation time 435940801 ps
CPU time 8.46 seconds
Started Feb 09 04:25:51 AM UTC 25
Finished Feb 09 04:26:00 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947135770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3947135770
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.4283876302
Short name T726
Test name
Test status
Simulation time 290674329 ps
CPU time 5.55 seconds
Started Feb 09 04:25:47 AM UTC 25
Finished Feb 09 04:25:54 AM UTC 25
Peak memory 251416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283876302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.4283876302
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.1727112168
Short name T735
Test name
Test status
Simulation time 1098377939 ps
CPU time 14.81 seconds
Started Feb 09 04:25:55 AM UTC 25
Finished Feb 09 04:26:11 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727112168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1727112168
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.1249190854
Short name T480
Test name
Test status
Simulation time 673617005 ps
CPU time 17.33 seconds
Started Feb 09 04:25:58 AM UTC 25
Finished Feb 09 04:26:16 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249190854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1249190854
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.2126195260
Short name T727
Test name
Test status
Simulation time 123886075 ps
CPU time 6.08 seconds
Started Feb 09 04:25:49 AM UTC 25
Finished Feb 09 04:25:56 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126195260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2126195260
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.3162403887
Short name T731
Test name
Test status
Simulation time 852500687 ps
CPU time 12.73 seconds
Started Feb 09 04:25:49 AM UTC 25
Finished Feb 09 04:26:03 AM UTC 25
Peak memory 257440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162403887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3162403887
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.1472721583
Short name T733
Test name
Test status
Simulation time 259110973 ps
CPU time 9.05 seconds
Started Feb 09 04:25:58 AM UTC 25
Finished Feb 09 04:26:08 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472721583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1472721583
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.2761092684
Short name T728
Test name
Test status
Simulation time 3067600527 ps
CPU time 9.23 seconds
Started Feb 09 04:25:46 AM UTC 25
Finished Feb 09 04:25:57 AM UTC 25
Peak memory 251432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761092684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2761092684
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.999304254
Short name T852
Test name
Test status
Simulation time 42617728987 ps
CPU time 304.54 seconds
Started Feb 09 04:26:01 AM UTC 25
Finished Feb 09 04:31:10 AM UTC 25
Peak memory 320952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999304254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_b
ase_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.999304254
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.1195127258
Short name T745
Test name
Test status
Simulation time 5106887163 ps
CPU time 29.07 seconds
Started Feb 09 04:25:58 AM UTC 25
Finished Feb 09 04:26:28 AM UTC 25
Peak memory 257340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195127258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1195127258
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.940692796
Short name T743
Test name
Test status
Simulation time 54514736 ps
CPU time 2.57 seconds
Started Feb 09 04:26:23 AM UTC 25
Finished Feb 09 04:26:26 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940692796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.940692796
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.415816290
Short name T741
Test name
Test status
Simulation time 1033470802 ps
CPU time 10.78 seconds
Started Feb 09 04:26:14 AM UTC 25
Finished Feb 09 04:26:26 AM UTC 25
Peak memory 257332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415816290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.415816290
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.4278700341
Short name T744
Test name
Test status
Simulation time 1075623742 ps
CPU time 14.59 seconds
Started Feb 09 04:26:12 AM UTC 25
Finished Feb 09 04:26:28 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278700341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.4278700341
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.369892571
Short name T753
Test name
Test status
Simulation time 2742959846 ps
CPU time 29.14 seconds
Started Feb 09 04:26:12 AM UTC 25
Finished Feb 09 04:26:43 AM UTC 25
Peak memory 253344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369892571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.369892571
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.949059029
Short name T201
Test name
Test status
Simulation time 123073844 ps
CPU time 5.07 seconds
Started Feb 09 04:26:07 AM UTC 25
Finished Feb 09 04:26:14 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949059029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.949059029
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.865108008
Short name T764
Test name
Test status
Simulation time 2046926946 ps
CPU time 44.21 seconds
Started Feb 09 04:26:14 AM UTC 25
Finished Feb 09 04:27:00 AM UTC 25
Peak memory 267572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865108008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.865108008
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.249622278
Short name T757
Test name
Test status
Simulation time 7407258018 ps
CPU time 28.1 seconds
Started Feb 09 04:26:16 AM UTC 25
Finished Feb 09 04:26:45 AM UTC 25
Peak memory 253220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249622278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.249622278
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.618302390
Short name T146
Test name
Test status
Simulation time 460401938 ps
CPU time 8.37 seconds
Started Feb 09 04:26:10 AM UTC 25
Finished Feb 09 04:26:19 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618302390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.618302390
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.4177125107
Short name T739
Test name
Test status
Simulation time 745926966 ps
CPU time 9.96 seconds
Started Feb 09 04:26:09 AM UTC 25
Finished Feb 09 04:26:20 AM UTC 25
Peak memory 257440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177125107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.4177125107
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.1693806000
Short name T742
Test name
Test status
Simulation time 300013100 ps
CPU time 7.75 seconds
Started Feb 09 04:26:17 AM UTC 25
Finished Feb 09 04:26:26 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693806000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1693806000
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.3971624921
Short name T738
Test name
Test status
Simulation time 869924727 ps
CPU time 9.51 seconds
Started Feb 09 04:26:06 AM UTC 25
Finished Feb 09 04:26:17 AM UTC 25
Peak memory 257280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971624921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3971624921
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.2202068270
Short name T138
Test name
Test status
Simulation time 40546730353 ps
CPU time 192.68 seconds
Started Feb 09 04:26:23 AM UTC 25
Finished Feb 09 04:29:38 AM UTC 25
Peak memory 283872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202068270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.2202068270
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3571255750
Short name T345
Test name
Test status
Simulation time 360859197268 ps
CPU time 3038.88 seconds
Started Feb 09 04:26:23 AM UTC 25
Finished Feb 09 05:17:34 AM UTC 25
Peak memory 404772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3571255750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_a
ll_with_rand_reset.3571255750
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.3957216367
Short name T746
Test name
Test status
Simulation time 1196197064 ps
CPU time 16.38 seconds
Started Feb 09 04:26:17 AM UTC 25
Finished Feb 09 04:26:35 AM UTC 25
Peak memory 251200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957216367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3957216367
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.34951929
Short name T756
Test name
Test status
Simulation time 153051522 ps
CPU time 2.58 seconds
Started Feb 09 04:26:40 AM UTC 25
Finished Feb 09 04:26:44 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34951929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.34951929
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.4213731512
Short name T758
Test name
Test status
Simulation time 641051619 ps
CPU time 16.17 seconds
Started Feb 09 04:26:29 AM UTC 25
Finished Feb 09 04:26:47 AM UTC 25
Peak memory 251292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213731512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.4213731512
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3747179380
Short name T783
Test name
Test status
Simulation time 4404155259 ps
CPU time 55.84 seconds
Started Feb 09 04:26:27 AM UTC 25
Finished Feb 09 04:27:24 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747179380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3747179380
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.3544050385
Short name T60
Test name
Test status
Simulation time 91632161 ps
CPU time 5.22 seconds
Started Feb 09 04:26:27 AM UTC 25
Finished Feb 09 04:26:33 AM UTC 25
Peak memory 251224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544050385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3544050385
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.289917223
Short name T751
Test name
Test status
Simulation time 129740257 ps
CPU time 4.38 seconds
Started Feb 09 04:26:34 AM UTC 25
Finished Feb 09 04:26:39 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289917223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.289917223
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.2453620230
Short name T759
Test name
Test status
Simulation time 457521549 ps
CPU time 12.75 seconds
Started Feb 09 04:26:36 AM UTC 25
Finished Feb 09 04:26:50 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453620230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2453620230
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.244258800
Short name T752
Test name
Test status
Simulation time 555532520 ps
CPU time 11.64 seconds
Started Feb 09 04:26:27 AM UTC 25
Finished Feb 09 04:26:39 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244258800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.244258800
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.2140074013
Short name T748
Test name
Test status
Simulation time 165236086 ps
CPU time 7.84 seconds
Started Feb 09 04:26:27 AM UTC 25
Finished Feb 09 04:26:36 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140074013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2140074013
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3924216211
Short name T754
Test name
Test status
Simulation time 2356079611 ps
CPU time 4.81 seconds
Started Feb 09 04:26:37 AM UTC 25
Finished Feb 09 04:26:43 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924216211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3924216211
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.1869185909
Short name T749
Test name
Test status
Simulation time 475919415 ps
CPU time 12.43 seconds
Started Feb 09 04:26:23 AM UTC 25
Finished Feb 09 04:26:36 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869185909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1869185909
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.4131423082
Short name T344
Test name
Test status
Simulation time 450900723963 ps
CPU time 2417.47 seconds
Started Feb 09 04:26:37 AM UTC 25
Finished Feb 09 05:07:20 AM UTC 25
Peak memory 292352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4131423082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_a
ll_with_rand_reset.4131423082
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.2442241863
Short name T760
Test name
Test status
Simulation time 8935042108 ps
CPU time 15.47 seconds
Started Feb 09 04:26:37 AM UTC 25
Finished Feb 09 04:26:54 AM UTC 25
Peak memory 251200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442241863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2442241863
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.1770495698
Short name T768
Test name
Test status
Simulation time 76207460 ps
CPU time 2.59 seconds
Started Feb 09 04:27:02 AM UTC 25
Finished Feb 09 04:27:05 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770495698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1770495698
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.1208312230
Short name T782
Test name
Test status
Simulation time 1265627586 ps
CPU time 33.95 seconds
Started Feb 09 04:26:47 AM UTC 25
Finished Feb 09 04:27:22 AM UTC 25
Peak memory 253436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208312230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1208312230
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.951828904
Short name T773
Test name
Test status
Simulation time 5905710075 ps
CPU time 26.61 seconds
Started Feb 09 04:26:47 AM UTC 25
Finished Feb 09 04:27:15 AM UTC 25
Peak memory 253532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951828904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.951828904
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2895678799
Short name T763
Test name
Test status
Simulation time 849077585 ps
CPU time 9.39 seconds
Started Feb 09 04:26:47 AM UTC 25
Finished Feb 09 04:26:57 AM UTC 25
Peak memory 251424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895678799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2895678799
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.3275908164
Short name T198
Test name
Test status
Simulation time 1771972223 ps
CPU time 7.22 seconds
Started Feb 09 04:26:47 AM UTC 25
Finished Feb 09 04:26:55 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275908164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3275908164
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.739304668
Short name T775
Test name
Test status
Simulation time 3380500347 ps
CPU time 26.11 seconds
Started Feb 09 04:26:48 AM UTC 25
Finished Feb 09 04:27:16 AM UTC 25
Peak memory 255252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739304668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.739304668
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.1980999344
Short name T770
Test name
Test status
Simulation time 6547172750 ps
CPU time 16.12 seconds
Started Feb 09 04:26:51 AM UTC 25
Finished Feb 09 04:27:08 AM UTC 25
Peak memory 253496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980999344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1980999344
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.1498873592
Short name T766
Test name
Test status
Simulation time 477063991 ps
CPU time 13.83 seconds
Started Feb 09 04:26:47 AM UTC 25
Finished Feb 09 04:27:02 AM UTC 25
Peak memory 253284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498873592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1498873592
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.1071859713
Short name T765
Test name
Test status
Simulation time 1328707235 ps
CPU time 12.49 seconds
Started Feb 09 04:26:47 AM UTC 25
Finished Feb 09 04:27:01 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071859713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1071859713
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.4291362997
Short name T771
Test name
Test status
Simulation time 1237980226 ps
CPU time 9.6 seconds
Started Feb 09 04:26:58 AM UTC 25
Finished Feb 09 04:27:08 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291362997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.4291362997
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.1629503211
Short name T762
Test name
Test status
Simulation time 1029116196 ps
CPU time 13.71 seconds
Started Feb 09 04:26:40 AM UTC 25
Finished Feb 09 04:26:55 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629503211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1629503211
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.3178405618
Short name T830
Test name
Test status
Simulation time 33907926068 ps
CPU time 167.51 seconds
Started Feb 09 04:26:58 AM UTC 25
Finished Feb 09 04:29:48 AM UTC 25
Peak memory 255500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178405618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.3178405618
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2295891102
Short name T1155
Test name
Test status
Simulation time 58984049177 ps
CPU time 1408.92 seconds
Started Feb 09 04:26:58 AM UTC 25
Finished Feb 09 04:50:42 AM UTC 25
Peak memory 411132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2295891102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_a
ll_with_rand_reset.2295891102
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.3811827953
Short name T767
Test name
Test status
Simulation time 639793180 ps
CPU time 6.35 seconds
Started Feb 09 04:26:58 AM UTC 25
Finished Feb 09 04:27:05 AM UTC 25
Peak memory 257472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811827953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3811827953
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3945529147
Short name T781
Test name
Test status
Simulation time 248247005 ps
CPU time 2.38 seconds
Started Feb 09 04:27:18 AM UTC 25
Finished Feb 09 04:27:22 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945529147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3945529147
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.2753714249
Short name T774
Test name
Test status
Simulation time 301793026 ps
CPU time 5.34 seconds
Started Feb 09 04:27:09 AM UTC 25
Finished Feb 09 04:27:15 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753714249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2753714249
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.2625575337
Short name T779
Test name
Test status
Simulation time 436714634 ps
CPU time 11.82 seconds
Started Feb 09 04:27:06 AM UTC 25
Finished Feb 09 04:27:19 AM UTC 25
Peak memory 253124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625575337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2625575337
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.492521551
Short name T776
Test name
Test status
Simulation time 500093126 ps
CPU time 9.09 seconds
Started Feb 09 04:27:06 AM UTC 25
Finished Feb 09 04:27:17 AM UTC 25
Peak memory 250900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492521551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.492521551
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.2130554336
Short name T769
Test name
Test status
Simulation time 307338067 ps
CPU time 4.81 seconds
Started Feb 09 04:27:02 AM UTC 25
Finished Feb 09 04:27:08 AM UTC 25
Peak memory 251416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130554336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2130554336
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.577679341
Short name T790
Test name
Test status
Simulation time 12979805996 ps
CPU time 30.22 seconds
Started Feb 09 04:27:09 AM UTC 25
Finished Feb 09 04:27:40 AM UTC 25
Peak memory 253300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577679341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.577679341
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.1010176041
Short name T786
Test name
Test status
Simulation time 1308398445 ps
CPU time 24.64 seconds
Started Feb 09 04:27:10 AM UTC 25
Finished Feb 09 04:27:36 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010176041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1010176041
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3862394733
Short name T777
Test name
Test status
Simulation time 1729906047 ps
CPU time 14.54 seconds
Started Feb 09 04:27:03 AM UTC 25
Finished Feb 09 04:27:19 AM UTC 25
Peak memory 253116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862394733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3862394733
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.151564915
Short name T778
Test name
Test status
Simulation time 1711733648 ps
CPU time 16.24 seconds
Started Feb 09 04:27:02 AM UTC 25
Finished Feb 09 04:27:19 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151564915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.151564915
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.1445436953
Short name T780
Test name
Test status
Simulation time 2461017862 ps
CPU time 8.22 seconds
Started Feb 09 04:27:11 AM UTC 25
Finished Feb 09 04:27:20 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445436953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1445436953
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3351729250
Short name T772
Test name
Test status
Simulation time 235222079 ps
CPU time 7.05 seconds
Started Feb 09 04:27:02 AM UTC 25
Finished Feb 09 04:27:10 AM UTC 25
Peak memory 251300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351729250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3351729250
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.2591737573
Short name T813
Test name
Test status
Simulation time 24357604888 ps
CPU time 85.06 seconds
Started Feb 09 04:27:17 AM UTC 25
Finished Feb 09 04:28:44 AM UTC 25
Peak memory 257284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591737573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.2591737573
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1826785808
Short name T350
Test name
Test status
Simulation time 90300363940 ps
CPU time 1891.22 seconds
Started Feb 09 04:27:17 AM UTC 25
Finished Feb 09 04:59:09 AM UTC 25
Peak memory 314876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1826785808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_a
ll_with_rand_reset.1826785808
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.3865375889
Short name T789
Test name
Test status
Simulation time 1099815245 ps
CPU time 21.23 seconds
Started Feb 09 04:27:17 AM UTC 25
Finished Feb 09 04:27:39 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865375889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3865375889
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.2899381388
Short name T791
Test name
Test status
Simulation time 591296829 ps
CPU time 3.28 seconds
Started Feb 09 04:27:41 AM UTC 25
Finished Feb 09 04:27:46 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899381388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2899381388
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.1990188596
Short name T799
Test name
Test status
Simulation time 1345835287 ps
CPU time 37.17 seconds
Started Feb 09 04:27:25 AM UTC 25
Finished Feb 09 04:28:04 AM UTC 25
Peak memory 257440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990188596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1990188596
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.1194245701
Short name T788
Test name
Test status
Simulation time 2682367877 ps
CPU time 13.18 seconds
Started Feb 09 04:27:24 AM UTC 25
Finished Feb 09 04:27:38 AM UTC 25
Peak memory 253304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194245701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1194245701
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.96492013
Short name T787
Test name
Test status
Simulation time 355369015 ps
CPU time 13.8 seconds
Started Feb 09 04:27:22 AM UTC 25
Finished Feb 09 04:27:37 AM UTC 25
Peak memory 251208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96492013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.96492013
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.3056180463
Short name T784
Test name
Test status
Simulation time 125946822 ps
CPU time 5.32 seconds
Started Feb 09 04:27:21 AM UTC 25
Finished Feb 09 04:27:28 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056180463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3056180463
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.625942058
Short name T835
Test name
Test status
Simulation time 70289254529 ps
CPU time 146.05 seconds
Started Feb 09 04:27:29 AM UTC 25
Finished Feb 09 04:29:58 AM UTC 25
Peak memory 267636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625942058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.625942058
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1843134675
Short name T490
Test name
Test status
Simulation time 614466795 ps
CPU time 31.68 seconds
Started Feb 09 04:27:32 AM UTC 25
Finished Feb 09 04:28:06 AM UTC 25
Peak memory 257244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843134675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1843134675
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.1640372012
Short name T794
Test name
Test status
Simulation time 963973519 ps
CPU time 29.82 seconds
Started Feb 09 04:27:21 AM UTC 25
Finished Feb 09 04:27:53 AM UTC 25
Peak memory 251260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640372012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1640372012
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.1228647702
Short name T793
Test name
Test status
Simulation time 1453857633 ps
CPU time 26.49 seconds
Started Feb 09 04:27:21 AM UTC 25
Finished Feb 09 04:27:49 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228647702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1228647702
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.1596578816
Short name T792
Test name
Test status
Simulation time 209028967 ps
CPU time 8.57 seconds
Started Feb 09 04:27:37 AM UTC 25
Finished Feb 09 04:27:47 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596578816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1596578816
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.3564487362
Short name T785
Test name
Test status
Simulation time 247551923 ps
CPU time 8.81 seconds
Started Feb 09 04:27:21 AM UTC 25
Finished Feb 09 04:27:31 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564487362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3564487362
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.3232388920
Short name T859
Test name
Test status
Simulation time 39925620513 ps
CPU time 231.47 seconds
Started Feb 09 04:27:41 AM UTC 25
Finished Feb 09 04:31:37 AM UTC 25
Peak memory 284000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232388920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.3232388920
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.4193417010
Short name T798
Test name
Test status
Simulation time 18872491106 ps
CPU time 23.9 seconds
Started Feb 09 04:27:38 AM UTC 25
Finished Feb 09 04:28:04 AM UTC 25
Peak memory 253440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193417010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.4193417010
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.2736889674
Short name T802
Test name
Test status
Simulation time 59064750 ps
CPU time 2.71 seconds
Started Feb 09 04:28:13 AM UTC 25
Finished Feb 09 04:28:17 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736889674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2736889674
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1427965863
Short name T800
Test name
Test status
Simulation time 1559761513 ps
CPU time 11.2 seconds
Started Feb 09 04:27:59 AM UTC 25
Finished Feb 09 04:28:11 AM UTC 25
Peak memory 257468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427965863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1427965863
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.83497749
Short name T810
Test name
Test status
Simulation time 2194556517 ps
CPU time 38.69 seconds
Started Feb 09 04:27:57 AM UTC 25
Finished Feb 09 04:28:37 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83497749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.83497749
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.61899361
Short name T803
Test name
Test status
Simulation time 1375282506 ps
CPU time 26.42 seconds
Started Feb 09 04:27:56 AM UTC 25
Finished Feb 09 04:28:24 AM UTC 25
Peak memory 251308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61899361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.61899361
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.2906729676
Short name T795
Test name
Test status
Simulation time 638290139 ps
CPU time 6.25 seconds
Started Feb 09 04:27:48 AM UTC 25
Finished Feb 09 04:27:55 AM UTC 25
Peak memory 251352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906729676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2906729676
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.91262363
Short name T805
Test name
Test status
Simulation time 1245539300 ps
CPU time 23.13 seconds
Started Feb 09 04:28:00 AM UTC 25
Finished Feb 09 04:28:25 AM UTC 25
Peak memory 253340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91262363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.91262363
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.740704682
Short name T471
Test name
Test status
Simulation time 15329860796 ps
CPU time 33.74 seconds
Started Feb 09 04:28:05 AM UTC 25
Finished Feb 09 04:28:40 AM UTC 25
Peak memory 253116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740704682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.740704682
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.3462910771
Short name T170
Test name
Test status
Simulation time 669323503 ps
CPU time 9.43 seconds
Started Feb 09 04:27:54 AM UTC 25
Finished Feb 09 04:28:04 AM UTC 25
Peak memory 251168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462910771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.3462910771
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.92550754
Short name T797
Test name
Test status
Simulation time 516160215 ps
CPU time 6.55 seconds
Started Feb 09 04:27:50 AM UTC 25
Finished Feb 09 04:27:58 AM UTC 25
Peak memory 257316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92550754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_T
EST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.92550754
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.3697275467
Short name T801
Test name
Test status
Simulation time 476575819 ps
CPU time 6.88 seconds
Started Feb 09 04:28:05 AM UTC 25
Finished Feb 09 04:28:13 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697275467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3697275467
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.375933931
Short name T796
Test name
Test status
Simulation time 283090423 ps
CPU time 6.7 seconds
Started Feb 09 04:27:48 AM UTC 25
Finished Feb 09 04:27:56 AM UTC 25
Peak memory 251380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375933931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.otp_ctrl_smoke.375933931
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.3165963129
Short name T396
Test name
Test status
Simulation time 72140440840 ps
CPU time 145.98 seconds
Started Feb 09 04:28:12 AM UTC 25
Finished Feb 09 04:30:41 AM UTC 25
Peak memory 257632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165963129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.3165963129
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2355113631
Short name T294
Test name
Test status
Simulation time 42023336987 ps
CPU time 365.57 seconds
Started Feb 09 04:28:07 AM UTC 25
Finished Feb 09 04:34:18 AM UTC 25
Peak memory 304632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2355113631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_a
ll_with_rand_reset.2355113631
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.3691587828
Short name T804
Test name
Test status
Simulation time 825719181 ps
CPU time 16.34 seconds
Started Feb 09 04:28:07 AM UTC 25
Finished Feb 09 04:28:25 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691587828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3691587828
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.2032776763
Short name T815
Test name
Test status
Simulation time 835821528 ps
CPU time 4 seconds
Started Feb 09 04:28:46 AM UTC 25
Finished Feb 09 04:28:51 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032776763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2032776763
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.653787168
Short name T61
Test name
Test status
Simulation time 1614198654 ps
CPU time 28.37 seconds
Started Feb 09 04:28:32 AM UTC 25
Finished Feb 09 04:29:01 AM UTC 25
Peak memory 253172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653787168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.653787168
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.3429685202
Short name T816
Test name
Test status
Simulation time 3874739188 ps
CPU time 22.06 seconds
Started Feb 09 04:28:30 AM UTC 25
Finished Feb 09 04:28:54 AM UTC 25
Peak memory 251456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429685202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3429685202
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.1274905036
Short name T809
Test name
Test status
Simulation time 249628609 ps
CPU time 8.6 seconds
Started Feb 09 04:28:26 AM UTC 25
Finished Feb 09 04:28:36 AM UTC 25
Peak memory 250948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274905036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1274905036
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.121199427
Short name T806
Test name
Test status
Simulation time 148701140 ps
CPU time 5.84 seconds
Started Feb 09 04:28:22 AM UTC 25
Finished Feb 09 04:28:29 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121199427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.121199427
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.2383245413
Short name T819
Test name
Test status
Simulation time 12276027224 ps
CPU time 31.87 seconds
Started Feb 09 04:28:33 AM UTC 25
Finished Feb 09 04:29:06 AM UTC 25
Peak memory 253280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383245413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2383245413
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.3937002604
Short name T814
Test name
Test status
Simulation time 453299759 ps
CPU time 15.76 seconds
Started Feb 09 04:28:33 AM UTC 25
Finished Feb 09 04:28:50 AM UTC 25
Peak memory 251124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937002604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3937002604
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2253285778
Short name T808
Test name
Test status
Simulation time 558240716 ps
CPU time 5.01 seconds
Started Feb 09 04:28:26 AM UTC 25
Finished Feb 09 04:28:32 AM UTC 25
Peak memory 250772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253285778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2253285778
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.272443023
Short name T811
Test name
Test status
Simulation time 405501045 ps
CPU time 15.52 seconds
Started Feb 09 04:28:24 AM UTC 25
Finished Feb 09 04:28:41 AM UTC 25
Peak memory 251296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272443023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.272443023
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.894156364
Short name T812
Test name
Test status
Simulation time 117700639 ps
CPU time 6.36 seconds
Started Feb 09 04:28:36 AM UTC 25
Finished Feb 09 04:28:44 AM UTC 25
Peak memory 257192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894156364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.894156364
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.3963202623
Short name T807
Test name
Test status
Simulation time 282735047 ps
CPU time 12.18 seconds
Started Feb 09 04:28:18 AM UTC 25
Finished Feb 09 04:28:32 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963202623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3963202623
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.4280201937
Short name T401
Test name
Test status
Simulation time 54616109760 ps
CPU time 131.52 seconds
Started Feb 09 04:28:43 AM UTC 25
Finished Feb 09 04:30:57 AM UTC 25
Peak memory 259400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280201937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.4280201937
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3720756752
Short name T1182
Test name
Test status
Simulation time 326372645831 ps
CPU time 2332.84 seconds
Started Feb 09 04:28:41 AM UTC 25
Finished Feb 09 05:08:00 AM UTC 25
Peak memory 349664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3720756752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_a
ll_with_rand_reset.3720756752
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.2671272153
Short name T820
Test name
Test status
Simulation time 900591303 ps
CPU time 27.54 seconds
Started Feb 09 04:28:39 AM UTC 25
Finished Feb 09 04:29:08 AM UTC 25
Peak memory 253184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671272153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2671272153
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.3967913785
Short name T826
Test name
Test status
Simulation time 67853601 ps
CPU time 2.98 seconds
Started Feb 09 04:29:32 AM UTC 25
Finished Feb 09 04:29:36 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967913785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3967913785
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.1592342579
Short name T62
Test name
Test status
Simulation time 738583800 ps
CPU time 21.26 seconds
Started Feb 09 04:29:07 AM UTC 25
Finished Feb 09 04:29:30 AM UTC 25
Peak memory 251176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592342579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1592342579
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.2224844587
Short name T823
Test name
Test status
Simulation time 4951482548 ps
CPU time 25.42 seconds
Started Feb 09 04:29:03 AM UTC 25
Finished Feb 09 04:29:29 AM UTC 25
Peak memory 251256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224844587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2224844587
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.413236821
Short name T838
Test name
Test status
Simulation time 5668802457 ps
CPU time 58.43 seconds
Started Feb 09 04:28:59 AM UTC 25
Finished Feb 09 04:29:59 AM UTC 25
Peak memory 253316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413236821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.413236821
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.4211656947
Short name T817
Test name
Test status
Simulation time 215009514 ps
CPU time 5.42 seconds
Started Feb 09 04:28:51 AM UTC 25
Finished Feb 09 04:28:58 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211656947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.4211656947
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.701377780
Short name T836
Test name
Test status
Simulation time 1756244946 ps
CPU time 50.67 seconds
Started Feb 09 04:29:07 AM UTC 25
Finished Feb 09 04:29:59 AM UTC 25
Peak memory 267284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701377780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.701377780
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.752040519
Short name T747
Test name
Test status
Simulation time 376196807 ps
CPU time 10.64 seconds
Started Feb 09 04:29:09 AM UTC 25
Finished Feb 09 04:29:21 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752040519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.752040519
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.3973562458
Short name T822
Test name
Test status
Simulation time 1491578774 ps
CPU time 26.53 seconds
Started Feb 09 04:28:55 AM UTC 25
Finished Feb 09 04:29:23 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973562458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3973562458
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.1226410387
Short name T825
Test name
Test status
Simulation time 8276093046 ps
CPU time 38.84 seconds
Started Feb 09 04:28:53 AM UTC 25
Finished Feb 09 04:29:33 AM UTC 25
Peak memory 251364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226410387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1226410387
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.2607365016
Short name T824
Test name
Test status
Simulation time 91573633 ps
CPU time 3.94 seconds
Started Feb 09 04:29:24 AM UTC 25
Finished Feb 09 04:29:30 AM UTC 25
Peak memory 251236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607365016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2607365016
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.1880962311
Short name T818
Test name
Test status
Simulation time 4543704818 ps
CPU time 18 seconds
Started Feb 09 04:28:46 AM UTC 25
Finished Feb 09 04:29:06 AM UTC 25
Peak memory 257384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880962311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1880962311
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.4205583215
Short name T862
Test name
Test status
Simulation time 13383585315 ps
CPU time 128 seconds
Started Feb 09 04:29:31 AM UTC 25
Finished Feb 09 04:31:42 AM UTC 25
Peak memory 255392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205583215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_
base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.4205583215
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.165300993
Short name T293
Test name
Test status
Simulation time 108702165654 ps
CPU time 231.82 seconds
Started Feb 09 04:29:25 AM UTC 25
Finished Feb 09 04:33:20 AM UTC 25
Peak memory 302692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=165300993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_al
l_with_rand_reset.165300993
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.1970376406
Short name T827
Test name
Test status
Simulation time 3466222280 ps
CPU time 10.14 seconds
Started Feb 09 04:29:25 AM UTC 25
Finished Feb 09 04:29:36 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970376406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1970376406
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.1228714771
Short name T513
Test name
Test status
Simulation time 215662449 ps
CPU time 3.01 seconds
Started Feb 09 04:13:54 AM UTC 25
Finished Feb 09 04:13:58 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228714771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1228714771
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.3096529182
Short name T150
Test name
Test status
Simulation time 1217610178 ps
CPU time 19.08 seconds
Started Feb 09 04:13:30 AM UTC 25
Finished Feb 09 04:13:51 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096529182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3096529182
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3903213159
Short name T512
Test name
Test status
Simulation time 266130475 ps
CPU time 6.64 seconds
Started Feb 09 04:13:36 AM UTC 25
Finished Feb 09 04:13:44 AM UTC 25
Peak memory 255288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903213159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3903213159
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.2514476251
Short name T9
Test name
Test status
Simulation time 2901481133 ps
CPU time 24.31 seconds
Started Feb 09 04:13:36 AM UTC 25
Finished Feb 09 04:14:02 AM UTC 25
Peak memory 251432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514476251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.2514476251
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.2581927695
Short name T257
Test name
Test status
Simulation time 1943317670 ps
CPU time 17.04 seconds
Started Feb 09 04:13:33 AM UTC 25
Finished Feb 09 04:13:52 AM UTC 25
Peak memory 251180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581927695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2581927695
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.4046854792
Short name T102
Test name
Test status
Simulation time 379660849 ps
CPU time 5.88 seconds
Started Feb 09 04:13:28 AM UTC 25
Finished Feb 09 04:13:36 AM UTC 25
Peak memory 253276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046854792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.4046854792
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.3472763508
Short name T200
Test name
Test status
Simulation time 1695851230 ps
CPU time 36.7 seconds
Started Feb 09 04:13:40 AM UTC 25
Finished Feb 09 04:14:18 AM UTC 25
Peak memory 253216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472763508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3472763508
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.1208092067
Short name T463
Test name
Test status
Simulation time 4853564502 ps
CPU time 16.62 seconds
Started Feb 09 04:13:42 AM UTC 25
Finished Feb 09 04:14:00 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208092067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1208092067
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.77457133
Short name T1
Test name
Test status
Simulation time 230360625 ps
CPU time 12.08 seconds
Started Feb 09 04:13:33 AM UTC 25
Finished Feb 09 04:13:47 AM UTC 25
Peak memory 250824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77457133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.77457133
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.211302541
Short name T456
Test name
Test status
Simulation time 749807973 ps
CPU time 19.19 seconds
Started Feb 09 04:13:33 AM UTC 25
Finished Feb 09 04:13:54 AM UTC 25
Peak memory 256984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211302541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_
TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.211302541
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.3366401859
Short name T447
Test name
Test status
Simulation time 274053589 ps
CPU time 6.59 seconds
Started Feb 09 04:13:45 AM UTC 25
Finished Feb 09 04:13:53 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366401859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3366401859
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1908687709
Short name T417
Test name
Test status
Simulation time 560433706 ps
CPU time 10.8 seconds
Started Feb 09 04:13:28 AM UTC 25
Finished Feb 09 04:13:41 AM UTC 25
Peak memory 250960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908687709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1908687709
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3081712471
Short name T488
Test name
Test status
Simulation time 73017337609 ps
CPU time 1413.57 seconds
Started Feb 09 04:13:54 AM UTC 25
Finished Feb 09 04:37:42 AM UTC 25
Peak memory 276132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3081712471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_al
l_with_rand_reset.3081712471
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.1780230085
Short name T316
Test name
Test status
Simulation time 5981870690 ps
CPU time 36.2 seconds
Started Feb 09 04:13:47 AM UTC 25
Finished Feb 09 04:14:25 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780230085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1780230085
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.1565682744
Short name T828
Test name
Test status
Simulation time 234085202 ps
CPU time 4.77 seconds
Started Feb 09 04:29:32 AM UTC 25
Finished Feb 09 04:29:37 AM UTC 25
Peak memory 253400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565682744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1565682744
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.2111046487
Short name T304
Test name
Test status
Simulation time 2215351769 ps
CPU time 8.81 seconds
Started Feb 09 04:29:34 AM UTC 25
Finished Feb 09 04:29:44 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111046487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2111046487
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.2243328501
Short name T394
Test name
Test status
Simulation time 215595851056 ps
CPU time 1123.6 seconds
Started Feb 09 04:29:36 AM UTC 25
Finished Feb 09 04:48:33 AM UTC 25
Peak memory 361976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2243328501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_a
ll_with_rand_reset.2243328501
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.217127246
Short name T829
Test name
Test status
Simulation time 180511675 ps
CPU time 5.04 seconds
Started Feb 09 04:29:36 AM UTC 25
Finished Feb 09 04:29:42 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217127246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.217127246
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.2271831207
Short name T832
Test name
Test status
Simulation time 1827637212 ps
CPU time 11.22 seconds
Started Feb 09 04:29:36 AM UTC 25
Finished Feb 09 04:29:49 AM UTC 25
Peak memory 251004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271831207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2271831207
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.2406408541
Short name T489
Test name
Test status
Simulation time 27669048400 ps
CPU time 502.02 seconds
Started Feb 09 04:29:38 AM UTC 25
Finished Feb 09 04:38:07 AM UTC 25
Peak memory 280252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2406408541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_a
ll_with_rand_reset.2406408541
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.2950025009
Short name T90
Test name
Test status
Simulation time 200735584 ps
CPU time 4.77 seconds
Started Feb 09 04:29:43 AM UTC 25
Finished Feb 09 04:29:48 AM UTC 25
Peak memory 253464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950025009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2950025009
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.695256291
Short name T831
Test name
Test status
Simulation time 129651718 ps
CPU time 3.88 seconds
Started Feb 09 04:29:44 AM UTC 25
Finished Feb 09 04:29:49 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695256291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.695256291
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3708534351
Short name T834
Test name
Test status
Simulation time 110571589 ps
CPU time 6.3 seconds
Started Feb 09 04:29:50 AM UTC 25
Finished Feb 09 04:29:57 AM UTC 25
Peak memory 250948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708534351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3708534351
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.4198937642
Short name T837
Test name
Test status
Simulation time 189571834 ps
CPU time 8.09 seconds
Started Feb 09 04:29:50 AM UTC 25
Finished Feb 09 04:29:59 AM UTC 25
Peak memory 250752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198937642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.4198937642
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1283904379
Short name T390
Test name
Test status
Simulation time 54187230457 ps
CPU time 400.3 seconds
Started Feb 09 04:29:50 AM UTC 25
Finished Feb 09 04:36:36 AM UTC 25
Peak memory 267772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1283904379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_a
ll_with_rand_reset.1283904379
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.3683710436
Short name T833
Test name
Test status
Simulation time 1784978813 ps
CPU time 4.81 seconds
Started Feb 09 04:29:50 AM UTC 25
Finished Feb 09 04:29:56 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683710436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3683710436
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.1784698660
Short name T290
Test name
Test status
Simulation time 813738674 ps
CPU time 25.13 seconds
Started Feb 09 04:29:57 AM UTC 25
Finished Feb 09 04:30:24 AM UTC 25
Peak memory 251260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784698660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1784698660
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3190233401
Short name T348
Test name
Test status
Simulation time 95954211466 ps
CPU time 1674.02 seconds
Started Feb 09 04:29:58 AM UTC 25
Finished Feb 09 04:58:11 AM UTC 25
Peak memory 364220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3190233401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_a
ll_with_rand_reset.3190233401
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.20067698
Short name T840
Test name
Test status
Simulation time 298720132 ps
CPU time 6.18 seconds
Started Feb 09 04:30:02 AM UTC 25
Finished Feb 09 04:30:09 AM UTC 25
Peak memory 251264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20067698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.20067698
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2379740623
Short name T842
Test name
Test status
Simulation time 403915267 ps
CPU time 14.27 seconds
Started Feb 09 04:30:02 AM UTC 25
Finished Feb 09 04:30:17 AM UTC 25
Peak memory 253372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379740623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2379740623
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.902045328
Short name T501
Test name
Test status
Simulation time 39579971740 ps
CPU time 442.31 seconds
Started Feb 09 04:30:02 AM UTC 25
Finished Feb 09 04:37:30 AM UTC 25
Peak memory 269824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=902045328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_al
l_with_rand_reset.902045328
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.3707318312
Short name T841
Test name
Test status
Simulation time 2661786406 ps
CPU time 7.4 seconds
Started Feb 09 04:30:02 AM UTC 25
Finished Feb 09 04:30:11 AM UTC 25
Peak memory 251420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707318312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3707318312
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1450243187
Short name T839
Test name
Test status
Simulation time 314935382 ps
CPU time 5.81 seconds
Started Feb 09 04:30:02 AM UTC 25
Finished Feb 09 04:30:09 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450243187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1450243187
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.969654645
Short name T843
Test name
Test status
Simulation time 409808366 ps
CPU time 7 seconds
Started Feb 09 04:30:10 AM UTC 25
Finished Feb 09 04:30:19 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969654645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.969654645
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.114228861
Short name T844
Test name
Test status
Simulation time 2405260853 ps
CPU time 9.61 seconds
Started Feb 09 04:30:11 AM UTC 25
Finished Feb 09 04:30:23 AM UTC 25
Peak memory 251164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114228861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.114228861
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3069289491
Short name T496
Test name
Test status
Simulation time 16102656214 ps
CPU time 358.79 seconds
Started Feb 09 04:30:19 AM UTC 25
Finished Feb 09 04:36:23 AM UTC 25
Peak memory 267772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3069289491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_a
ll_with_rand_reset.3069289491
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.3780095234
Short name T56
Test name
Test status
Simulation time 492368565 ps
CPU time 5.92 seconds
Started Feb 09 04:30:20 AM UTC 25
Finished Feb 09 04:30:27 AM UTC 25
Peak memory 251416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780095234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3780095234
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.3028490204
Short name T845
Test name
Test status
Simulation time 498535796 ps
CPU time 8.94 seconds
Started Feb 09 04:30:22 AM UTC 25
Finished Feb 09 04:30:32 AM UTC 25
Peak memory 253284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028490204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3028490204
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3831847980
Short name T386
Test name
Test status
Simulation time 54701159614 ps
CPU time 1241.12 seconds
Started Feb 09 04:30:23 AM UTC 25
Finished Feb 09 04:51:19 AM UTC 25
Peak memory 290300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3831847980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_a
ll_with_rand_reset.3831847980
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.3558265801
Short name T46
Test name
Test status
Simulation time 328209743 ps
CPU time 4.82 seconds
Started Feb 09 04:30:25 AM UTC 25
Finished Feb 09 04:30:31 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558265801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3558265801
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.1077124245
Short name T167
Test name
Test status
Simulation time 996920189 ps
CPU time 15.68 seconds
Started Feb 09 04:30:28 AM UTC 25
Finished Feb 09 04:30:45 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077124245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1077124245
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.4115360884
Short name T352
Test name
Test status
Simulation time 80859201231 ps
CPU time 2045.52 seconds
Started Feb 09 04:30:32 AM UTC 25
Finished Feb 09 05:04:59 AM UTC 25
Peak memory 284284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4115360884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_a
ll_with_rand_reset.4115360884
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.396199278
Short name T515
Test name
Test status
Simulation time 183040191 ps
CPU time 1.92 seconds
Started Feb 09 04:14:15 AM UTC 25
Finished Feb 09 04:14:18 AM UTC 25
Peak memory 251032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396199278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.396199278
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.1095424396
Short name T462
Test name
Test status
Simulation time 1713532528 ps
CPU time 14.97 seconds
Started Feb 09 04:13:55 AM UTC 25
Finished Feb 09 04:14:11 AM UTC 25
Peak memory 257308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095424396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1095424396
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.4051000384
Short name T106
Test name
Test status
Simulation time 1716647557 ps
CPU time 20.84 seconds
Started Feb 09 04:14:01 AM UTC 25
Finished Feb 09 04:14:23 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051000384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.4051000384
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.681019945
Short name T264
Test name
Test status
Simulation time 994608569 ps
CPU time 26.02 seconds
Started Feb 09 04:14:01 AM UTC 25
Finished Feb 09 04:14:28 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681019945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.681019945
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.1560931674
Short name T514
Test name
Test status
Simulation time 148962684 ps
CPU time 6.03 seconds
Started Feb 09 04:14:01 AM UTC 25
Finished Feb 09 04:14:08 AM UTC 25
Peak memory 253076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560931674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1560931674
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1122402784
Short name T186
Test name
Test status
Simulation time 215497211 ps
CPU time 3.97 seconds
Started Feb 09 04:13:54 AM UTC 25
Finished Feb 09 04:13:59 AM UTC 25
Peak memory 251392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122402784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1122402784
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.1546845504
Short name T188
Test name
Test status
Simulation time 1417622471 ps
CPU time 15.83 seconds
Started Feb 09 04:14:01 AM UTC 25
Finished Feb 09 04:14:18 AM UTC 25
Peak memory 253344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546845504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1546845504
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2061214364
Short name T281
Test name
Test status
Simulation time 3926241277 ps
CPU time 28.71 seconds
Started Feb 09 04:14:03 AM UTC 25
Finished Feb 09 04:14:33 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061214364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2061214364
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.3180072427
Short name T162
Test name
Test status
Simulation time 196823870 ps
CPU time 7.07 seconds
Started Feb 09 04:13:59 AM UTC 25
Finished Feb 09 04:14:07 AM UTC 25
Peak memory 251048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180072427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3180072427
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.2453863842
Short name T295
Test name
Test status
Simulation time 740177995 ps
CPU time 33.54 seconds
Started Feb 09 04:13:59 AM UTC 25
Finished Feb 09 04:14:34 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453863842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2453863842
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.4283267955
Short name T418
Test name
Test status
Simulation time 2282924854 ps
CPU time 9.81 seconds
Started Feb 09 04:14:06 AM UTC 25
Finished Feb 09 04:14:17 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283267955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.4283267955
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.82999547
Short name T300
Test name
Test status
Simulation time 4687116216 ps
CPU time 18.96 seconds
Started Feb 09 04:13:54 AM UTC 25
Finished Feb 09 04:14:14 AM UTC 25
Peak memory 251428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82999547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.otp_ctrl_smoke.82999547
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3685496467
Short name T282
Test name
Test status
Simulation time 1136494205054 ps
CPU time 3598.74 seconds
Started Feb 09 04:14:09 AM UTC 25
Finished Feb 09 05:14:46 AM UTC 25
Peak memory 513728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3685496467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_al
l_with_rand_reset.3685496467
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.327105646
Short name T317
Test name
Test status
Simulation time 584448888 ps
CPU time 10.83 seconds
Started Feb 09 04:14:07 AM UTC 25
Finished Feb 09 04:14:19 AM UTC 25
Peak memory 257340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327105646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.327105646
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.4217805442
Short name T846
Test name
Test status
Simulation time 196267909 ps
CPU time 4.29 seconds
Started Feb 09 04:30:34 AM UTC 25
Finished Feb 09 04:30:39 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217805442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.4217805442
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1901664831
Short name T399
Test name
Test status
Simulation time 671386853 ps
CPU time 18.91 seconds
Started Feb 09 04:30:34 AM UTC 25
Finished Feb 09 04:30:54 AM UTC 25
Peak memory 251300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901664831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1901664831
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.3743214673
Short name T397
Test name
Test status
Simulation time 1280798394 ps
CPU time 4.3 seconds
Started Feb 09 04:30:40 AM UTC 25
Finished Feb 09 04:30:45 AM UTC 25
Peak memory 251224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743214673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3743214673
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.1348423679
Short name T398
Test name
Test status
Simulation time 373969479 ps
CPU time 5.1 seconds
Started Feb 09 04:30:41 AM UTC 25
Finished Feb 09 04:30:47 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348423679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1348423679
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3160315408
Short name T1009
Test name
Test status
Simulation time 70940393874 ps
CPU time 1069.88 seconds
Started Feb 09 04:30:45 AM UTC 25
Finished Feb 09 04:48:48 AM UTC 25
Peak memory 337660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3160315408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_a
ll_with_rand_reset.3160315408
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.3524433978
Short name T847
Test name
Test status
Simulation time 107741681 ps
CPU time 5.33 seconds
Started Feb 09 04:30:51 AM UTC 25
Finished Feb 09 04:30:58 AM UTC 25
Peak memory 250832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524433978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3524433978
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.3870273537
Short name T848
Test name
Test status
Simulation time 670953934 ps
CPU time 6.28 seconds
Started Feb 09 04:30:51 AM UTC 25
Finished Feb 09 04:30:59 AM UTC 25
Peak memory 251336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870273537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3870273537
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.1127659305
Short name T855
Test name
Test status
Simulation time 630281417 ps
CPU time 24.58 seconds
Started Feb 09 04:30:55 AM UTC 25
Finished Feb 09 04:31:21 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127659305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1127659305
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.4007791001
Short name T849
Test name
Test status
Simulation time 537834858 ps
CPU time 4.8 seconds
Started Feb 09 04:30:57 AM UTC 25
Finished Feb 09 04:31:03 AM UTC 25
Peak memory 253336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007791001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.4007791001
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.3020840423
Short name T850
Test name
Test status
Simulation time 134235663 ps
CPU time 4.89 seconds
Started Feb 09 04:31:00 AM UTC 25
Finished Feb 09 04:31:06 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020840423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3020840423
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3318987906
Short name T851
Test name
Test status
Simulation time 145316282 ps
CPU time 5.79 seconds
Started Feb 09 04:31:00 AM UTC 25
Finished Feb 09 04:31:07 AM UTC 25
Peak memory 251156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318987906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3318987906
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.4132814726
Short name T858
Test name
Test status
Simulation time 2352807385 ps
CPU time 24.49 seconds
Started Feb 09 04:31:04 AM UTC 25
Finished Feb 09 04:31:29 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132814726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.4132814726
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.221800394
Short name T1176
Test name
Test status
Simulation time 582349053891 ps
CPU time 1374.68 seconds
Started Feb 09 04:31:09 AM UTC 25
Finished Feb 09 04:54:19 AM UTC 25
Peak memory 374120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=221800394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_al
l_with_rand_reset.221800394
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3827895783
Short name T853
Test name
Test status
Simulation time 236048995 ps
CPU time 3.74 seconds
Started Feb 09 04:31:09 AM UTC 25
Finished Feb 09 04:31:14 AM UTC 25
Peak memory 253296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827895783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3827895783
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.2832981256
Short name T854
Test name
Test status
Simulation time 133186847 ps
CPU time 5.79 seconds
Started Feb 09 04:31:09 AM UTC 25
Finished Feb 09 04:31:16 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832981256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2832981256
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.399173115
Short name T856
Test name
Test status
Simulation time 147755299 ps
CPU time 4.8 seconds
Started Feb 09 04:31:15 AM UTC 25
Finished Feb 09 04:31:21 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399173115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.399173115
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.2497907586
Short name T857
Test name
Test status
Simulation time 451793302 ps
CPU time 7.74 seconds
Started Feb 09 04:31:16 AM UTC 25
Finished Feb 09 04:31:25 AM UTC 25
Peak memory 257252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497907586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2497907586
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2774272011
Short name T1175
Test name
Test status
Simulation time 64650738965 ps
CPU time 1272.56 seconds
Started Feb 09 04:31:19 AM UTC 25
Finished Feb 09 04:52:46 AM UTC 25
Peak memory 327420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2774272011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_a
ll_with_rand_reset.2774272011
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.321620247
Short name T47
Test name
Test status
Simulation time 308686809 ps
CPU time 5.81 seconds
Started Feb 09 04:31:22 AM UTC 25
Finished Feb 09 04:31:29 AM UTC 25
Peak memory 251316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321620247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.321620247
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.1804375085
Short name T161
Test name
Test status
Simulation time 2359918185 ps
CPU time 6.7 seconds
Started Feb 09 04:31:23 AM UTC 25
Finished Feb 09 04:31:30 AM UTC 25
Peak memory 251076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804375085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1804375085
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1525582483
Short name T1177
Test name
Test status
Simulation time 326893612298 ps
CPU time 1388.03 seconds
Started Feb 09 04:31:27 AM UTC 25
Finished Feb 09 04:54:50 AM UTC 25
Peak memory 333312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1525582483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_a
ll_with_rand_reset.1525582483
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.2849247126
Short name T860
Test name
Test status
Simulation time 173230738 ps
CPU time 6.15 seconds
Started Feb 09 04:31:30 AM UTC 25
Finished Feb 09 04:31:38 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849247126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2849247126
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.857832147
Short name T861
Test name
Test status
Simulation time 653804187 ps
CPU time 10.37 seconds
Started Feb 09 04:31:30 AM UTC 25
Finished Feb 09 04:31:42 AM UTC 25
Peak memory 251064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857832147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.857832147
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.3973960464
Short name T520
Test name
Test status
Simulation time 221062082 ps
CPU time 2.95 seconds
Started Feb 09 04:14:35 AM UTC 25
Finished Feb 09 04:14:39 AM UTC 25
Peak memory 251000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973960464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3973960464
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.571124556
Short name T151
Test name
Test status
Simulation time 3687510495 ps
CPU time 28.88 seconds
Started Feb 09 04:14:19 AM UTC 25
Finished Feb 09 04:14:49 AM UTC 25
Peak memory 253560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571124556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.571124556
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.51794015
Short name T518
Test name
Test status
Simulation time 385541084 ps
CPU time 6.84 seconds
Started Feb 09 04:14:24 AM UTC 25
Finished Feb 09 04:14:32 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51794015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.51794015
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.3900578197
Short name T274
Test name
Test status
Simulation time 1872488269 ps
CPU time 37.7 seconds
Started Feb 09 04:14:22 AM UTC 25
Finished Feb 09 04:15:02 AM UTC 25
Peak memory 255272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900578197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3900578197
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1487535234
Short name T460
Test name
Test status
Simulation time 2171055833 ps
CPU time 21.04 seconds
Started Feb 09 04:14:20 AM UTC 25
Finished Feb 09 04:14:43 AM UTC 25
Peak memory 251436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487535234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1487535234
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.892769891
Short name T416
Test name
Test status
Simulation time 497927618 ps
CPU time 7.16 seconds
Started Feb 09 04:14:26 AM UTC 25
Finished Feb 09 04:14:35 AM UTC 25
Peak memory 257500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892769891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.892769891
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.2199371481
Short name T519
Test name
Test status
Simulation time 539646596 ps
CPU time 8.31 seconds
Started Feb 09 04:14:27 AM UTC 25
Finished Feb 09 04:14:37 AM UTC 25
Peak memory 253152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199371481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2199371481
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3575678910
Short name T517
Test name
Test status
Simulation time 303000400 ps
CPU time 6.24 seconds
Started Feb 09 04:14:20 AM UTC 25
Finished Feb 09 04:14:28 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575678910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3575678910
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.3973946961
Short name T458
Test name
Test status
Simulation time 926269700 ps
CPU time 27.87 seconds
Started Feb 09 04:14:19 AM UTC 25
Finished Feb 09 04:14:48 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973946961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3973946961
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.2040542605
Short name T299
Test name
Test status
Simulation time 170471432 ps
CPU time 5.83 seconds
Started Feb 09 04:14:27 AM UTC 25
Finished Feb 09 04:14:34 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040542605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2040542605
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.421338229
Short name T516
Test name
Test status
Simulation time 184735464 ps
CPU time 4.43 seconds
Started Feb 09 04:14:16 AM UTC 25
Finished Feb 09 04:14:22 AM UTC 25
Peak memory 251204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421338229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.otp_ctrl_smoke.421338229
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1374967536
Short name T896
Test name
Test status
Simulation time 726898148066 ps
CPU time 1508.17 seconds
Started Feb 09 04:14:29 AM UTC 25
Finished Feb 09 04:39:54 AM UTC 25
Peak memory 271844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1374967536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_al
l_with_rand_reset.1374967536
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.3177328575
Short name T259
Test name
Test status
Simulation time 753123346 ps
CPU time 11.29 seconds
Started Feb 09 04:14:29 AM UTC 25
Finished Feb 09 04:14:42 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177328575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.3177328575
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.1133640335
Short name T863
Test name
Test status
Simulation time 2157116210 ps
CPU time 10.22 seconds
Started Feb 09 04:31:35 AM UTC 25
Finished Feb 09 04:31:46 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133640335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1133640335
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.796871924
Short name T147
Test name
Test status
Simulation time 715639476 ps
CPU time 6.68 seconds
Started Feb 09 04:31:42 AM UTC 25
Finished Feb 09 04:31:50 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796871924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.796871924
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.1011229578
Short name T864
Test name
Test status
Simulation time 2095261453 ps
CPU time 7.63 seconds
Started Feb 09 04:31:44 AM UTC 25
Finished Feb 09 04:31:53 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011229578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1011229578
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.123157820
Short name T866
Test name
Test status
Simulation time 3518981398 ps
CPU time 15.37 seconds
Started Feb 09 04:31:44 AM UTC 25
Finished Feb 09 04:32:01 AM UTC 25
Peak memory 253216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123157820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.123157820
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.414380501
Short name T391
Test name
Test status
Simulation time 75033059285 ps
CPU time 502.91 seconds
Started Feb 09 04:31:47 AM UTC 25
Finished Feb 09 04:40:16 AM UTC 25
Peak memory 273920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=414380501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_al
l_with_rand_reset.414380501
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.2851585901
Short name T865
Test name
Test status
Simulation time 569376505 ps
CPU time 6.04 seconds
Started Feb 09 04:31:50 AM UTC 25
Finished Feb 09 04:31:58 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851585901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2851585901
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.2498555383
Short name T867
Test name
Test status
Simulation time 395461781 ps
CPU time 13.18 seconds
Started Feb 09 04:31:53 AM UTC 25
Finished Feb 09 04:32:08 AM UTC 25
Peak memory 251004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498555383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2498555383
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2822850685
Short name T353
Test name
Test status
Simulation time 847669631517 ps
CPU time 2080.89 seconds
Started Feb 09 04:31:59 AM UTC 25
Finished Feb 09 05:07:03 AM UTC 25
Peak memory 316924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2822850685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_a
ll_with_rand_reset.2822850685
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.4030584954
Short name T68
Test name
Test status
Simulation time 162173495 ps
CPU time 5.56 seconds
Started Feb 09 04:32:02 AM UTC 25
Finished Feb 09 04:32:09 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030584954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.4030584954
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.137300344
Short name T868
Test name
Test status
Simulation time 387405559 ps
CPU time 14 seconds
Started Feb 09 04:32:09 AM UTC 25
Finished Feb 09 04:32:25 AM UTC 25
Peak memory 251256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137300344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.137300344
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3477819682
Short name T909
Test name
Test status
Simulation time 42684225344 ps
CPU time 745.25 seconds
Started Feb 09 04:32:09 AM UTC 25
Finished Feb 09 04:44:44 AM UTC 25
Peak memory 267836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3477819682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_a
ll_with_rand_reset.3477819682
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.3467216027
Short name T869
Test name
Test status
Simulation time 390591115 ps
CPU time 5.78 seconds
Started Feb 09 04:32:26 AM UTC 25
Finished Feb 09 04:32:33 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467216027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3467216027
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.248577302
Short name T400
Test name
Test status
Simulation time 641453601 ps
CPU time 10.97 seconds
Started Feb 09 04:32:34 AM UTC 25
Finished Feb 09 04:32:46 AM UTC 25
Peak memory 253176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248577302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.248577302
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.847386352
Short name T870
Test name
Test status
Simulation time 296310794 ps
CPU time 5.24 seconds
Started Feb 09 04:32:46 AM UTC 25
Finished Feb 09 04:32:52 AM UTC 25
Peak memory 253148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847386352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.847386352
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3039881683
Short name T871
Test name
Test status
Simulation time 257615149 ps
CPU time 9.21 seconds
Started Feb 09 04:32:47 AM UTC 25
Finished Feb 09 04:32:57 AM UTC 25
Peak memory 251044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039881683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3039881683
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1203367881
Short name T346
Test name
Test status
Simulation time 2101660269108 ps
CPU time 3414.2 seconds
Started Feb 09 04:32:53 AM UTC 25
Finished Feb 09 05:30:21 AM UTC 25
Peak memory 273916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1203367881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_a
ll_with_rand_reset.1203367881
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.2173888142
Short name T872
Test name
Test status
Simulation time 230402948 ps
CPU time 5.65 seconds
Started Feb 09 04:32:58 AM UTC 25
Finished Feb 09 04:33:05 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173888142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2173888142
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.3338818167
Short name T873
Test name
Test status
Simulation time 363100715 ps
CPU time 6.21 seconds
Started Feb 09 04:33:05 AM UTC 25
Finished Feb 09 04:33:13 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338818167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3338818167
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2987108024
Short name T1178
Test name
Test status
Simulation time 207395434139 ps
CPU time 1297.14 seconds
Started Feb 09 04:33:14 AM UTC 25
Finished Feb 09 04:55:05 AM UTC 25
Peak memory 286396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2987108024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_a
ll_with_rand_reset.2987108024
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.631445271
Short name T88
Test name
Test status
Simulation time 691106834 ps
CPU time 4.75 seconds
Started Feb 09 04:33:21 AM UTC 25
Finished Feb 09 04:33:27 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631445271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.631445271
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.2690142804
Short name T874
Test name
Test status
Simulation time 1406721285 ps
CPU time 18.51 seconds
Started Feb 09 04:33:28 AM UTC 25
Finished Feb 09 04:33:48 AM UTC 25
Peak memory 251072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690142804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2690142804
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.3443813465
Short name T875
Test name
Test status
Simulation time 275016802 ps
CPU time 5.34 seconds
Started Feb 09 04:34:19 AM UTC 25
Finished Feb 09 04:34:26 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443813465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3443813465
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.2195734336
Short name T302
Test name
Test status
Simulation time 139897697 ps
CPU time 4.52 seconds
Started Feb 09 04:34:26 AM UTC 25
Finished Feb 09 04:34:32 AM UTC 25
Peak memory 251108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195734336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2195734336
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1189296675
Short name T1186
Test name
Test status
Simulation time 317682133034 ps
CPU time 2551.15 seconds
Started Feb 09 04:34:33 AM UTC 25
Finished Feb 09 05:17:30 AM UTC 25
Peak memory 290300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1189296675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_a
ll_with_rand_reset.1189296675
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.4090892471
Short name T80
Test name
Test status
Simulation time 172598589 ps
CPU time 5.89 seconds
Started Feb 09 04:34:42 AM UTC 25
Finished Feb 09 04:34:49 AM UTC 25
Peak memory 251156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090892471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.4090892471
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.4103619390
Short name T876
Test name
Test status
Simulation time 322002874 ps
CPU time 5.07 seconds
Started Feb 09 04:34:50 AM UTC 25
Finished Feb 09 04:34:56 AM UTC 25
Peak memory 251068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103619390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.4103619390
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.1470820367
Short name T269
Test name
Test status
Simulation time 138747211 ps
CPU time 2.73 seconds
Started Feb 09 04:14:54 AM UTC 25
Finished Feb 09 04:14:58 AM UTC 25
Peak memory 251096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470820367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1470820367
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.1063901944
Short name T271
Test name
Test status
Simulation time 932704749 ps
CPU time 21.02 seconds
Started Feb 09 04:14:36 AM UTC 25
Finished Feb 09 04:14:58 AM UTC 25
Peak memory 253440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063901944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1063901944
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.3630880045
Short name T275
Test name
Test status
Simulation time 543639364 ps
CPU time 15.24 seconds
Started Feb 09 04:14:46 AM UTC 25
Finished Feb 09 04:15:03 AM UTC 25
Peak memory 251060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630880045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3630880045
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.2714376252
Short name T272
Test name
Test status
Simulation time 753715964 ps
CPU time 13.49 seconds
Started Feb 09 04:14:46 AM UTC 25
Finished Feb 09 04:15:01 AM UTC 25
Peak memory 251148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714376252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2714376252
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.278455610
Short name T524
Test name
Test status
Simulation time 251170779 ps
CPU time 5.32 seconds
Started Feb 09 04:14:46 AM UTC 25
Finished Feb 09 04:14:53 AM UTC 25
Peak memory 257256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278455610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.278455610
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2750272711
Short name T165
Test name
Test status
Simulation time 2377502526 ps
CPU time 25.46 seconds
Started Feb 09 04:14:39 AM UTC 25
Finished Feb 09 04:15:06 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750272711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2750272711
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.2208796400
Short name T523
Test name
Test status
Simulation time 458202346 ps
CPU time 11.09 seconds
Started Feb 09 04:14:37 AM UTC 25
Finished Feb 09 04:14:50 AM UTC 25
Peak memory 251104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208796400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2208796400
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.2760138244
Short name T276
Test name
Test status
Simulation time 2217084082 ps
CPU time 11.24 seconds
Started Feb 09 04:14:50 AM UTC 25
Finished Feb 09 04:15:03 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760138244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2760138244
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.924797162
Short name T522
Test name
Test status
Simulation time 1918703166 ps
CPU time 5.91 seconds
Started Feb 09 04:14:35 AM UTC 25
Finished Feb 09 04:14:42 AM UTC 25
Peak memory 257352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924797162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.otp_ctrl_smoke.924797162
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3035975124
Short name T270
Test name
Test status
Simulation time 258761230 ps
CPU time 6.43 seconds
Started Feb 09 04:14:51 AM UTC 25
Finished Feb 09 04:14:58 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035975124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3035975124
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.2444810722
Short name T877
Test name
Test status
Simulation time 480290965 ps
CPU time 6.05 seconds
Started Feb 09 04:35:11 AM UTC 25
Finished Feb 09 04:35:18 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444810722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2444810722
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3152542179
Short name T878
Test name
Test status
Simulation time 148547404 ps
CPU time 6.81 seconds
Started Feb 09 04:35:19 AM UTC 25
Finished Feb 09 04:35:27 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152542179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3152542179
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1407630960
Short name T1187
Test name
Test status
Simulation time 87251225156 ps
CPU time 2517.65 seconds
Started Feb 09 04:35:29 AM UTC 25
Finished Feb 09 05:17:54 AM UTC 25
Peak memory 290300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1407630960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_a
ll_with_rand_reset.1407630960
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.1886953483
Short name T92
Test name
Test status
Simulation time 647054069 ps
CPU time 5.95 seconds
Started Feb 09 04:35:37 AM UTC 25
Finished Feb 09 04:35:44 AM UTC 25
Peak memory 251136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886953483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1886953483
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1902207756
Short name T291
Test name
Test status
Simulation time 539953772 ps
CPU time 15.21 seconds
Started Feb 09 04:35:45 AM UTC 25
Finished Feb 09 04:36:02 AM UTC 25
Peak memory 251300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902207756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1902207756
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3666117749
Short name T912
Test name
Test status
Simulation time 25103091262 ps
CPU time 536.47 seconds
Started Feb 09 04:35:59 AM UTC 25
Finished Feb 09 04:45:02 AM UTC 25
Peak memory 333308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3666117749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_a
ll_with_rand_reset.3666117749
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.1395955454
Short name T879
Test name
Test status
Simulation time 207339124 ps
CPU time 6.03 seconds
Started Feb 09 04:36:03 AM UTC 25
Finished Feb 09 04:36:10 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395955454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1395955454
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.297637111
Short name T881
Test name
Test status
Simulation time 483699613 ps
CPU time 10.22 seconds
Started Feb 09 04:36:11 AM UTC 25
Finished Feb 09 04:36:23 AM UTC 25
Peak memory 253368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297637111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.297637111
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.69444039
Short name T343
Test name
Test status
Simulation time 202604003649 ps
CPU time 1807.02 seconds
Started Feb 09 04:36:25 AM UTC 25
Finished Feb 09 05:06:53 AM UTC 25
Peak memory 316928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=69444039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all
_with_rand_reset.69444039
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.3518284037
Short name T882
Test name
Test status
Simulation time 114098438 ps
CPU time 5.97 seconds
Started Feb 09 04:36:25 AM UTC 25
Finished Feb 09 04:36:32 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518284037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3518284037
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.467280496
Short name T883
Test name
Test status
Simulation time 180281875 ps
CPU time 11.09 seconds
Started Feb 09 04:36:25 AM UTC 25
Finished Feb 09 04:36:37 AM UTC 25
Peak memory 253084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467280496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.467280496
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.429020731
Short name T384
Test name
Test status
Simulation time 22537438012 ps
CPU time 455.7 seconds
Started Feb 09 04:36:33 AM UTC 25
Finished Feb 09 04:44:15 AM UTC 25
Peak memory 267776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=429020731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_al
l_with_rand_reset.429020731
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.1194729060
Short name T884
Test name
Test status
Simulation time 122815926 ps
CPU time 4.91 seconds
Started Feb 09 04:36:37 AM UTC 25
Finished Feb 09 04:36:43 AM UTC 25
Peak memory 253180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194729060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1194729060
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3379021776
Short name T885
Test name
Test status
Simulation time 322900231 ps
CPU time 4.31 seconds
Started Feb 09 04:36:38 AM UTC 25
Finished Feb 09 04:36:44 AM UTC 25
Peak memory 251072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379021776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3379021776
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.500966755
Short name T886
Test name
Test status
Simulation time 225062237 ps
CPU time 5.8 seconds
Started Feb 09 04:36:45 AM UTC 25
Finished Feb 09 04:36:52 AM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500966755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.500966755
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.56420076
Short name T887
Test name
Test status
Simulation time 1261199214 ps
CPU time 15.29 seconds
Started Feb 09 04:36:47 AM UTC 25
Finished Feb 09 04:37:03 AM UTC 25
Peak memory 251064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56420076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.56420076
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4085045664
Short name T497
Test name
Test status
Simulation time 36902364219 ps
CPU time 920.81 seconds
Started Feb 09 04:36:53 AM UTC 25
Finished Feb 09 04:52:25 AM UTC 25
Peak memory 341756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4085045664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_a
ll_with_rand_reset.4085045664
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.555960414
Short name T888
Test name
Test status
Simulation time 302247571 ps
CPU time 6.88 seconds
Started Feb 09 04:37:04 AM UTC 25
Finished Feb 09 04:37:12 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555960414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.555960414
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.3257886595
Short name T889
Test name
Test status
Simulation time 320553390 ps
CPU time 4.71 seconds
Started Feb 09 04:37:15 AM UTC 25
Finished Feb 09 04:37:21 AM UTC 25
Peak memory 253280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257886595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3257886595
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.307902325
Short name T395
Test name
Test status
Simulation time 91149512815 ps
CPU time 899.23 seconds
Started Feb 09 04:37:15 AM UTC 25
Finished Feb 09 04:52:24 AM UTC 25
Peak memory 321216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=307902325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_al
l_with_rand_reset.307902325
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.531584426
Short name T890
Test name
Test status
Simulation time 262448218 ps
CPU time 6.62 seconds
Started Feb 09 04:37:22 AM UTC 25
Finished Feb 09 04:37:30 AM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531584426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.531584426
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.494644255
Short name T891
Test name
Test status
Simulation time 192010069 ps
CPU time 13.67 seconds
Started Feb 09 04:37:32 AM UTC 25
Finished Feb 09 04:37:47 AM UTC 25
Peak memory 251036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494644255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.494644255
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1152889154
Short name T349
Test name
Test status
Simulation time 69012842879 ps
CPU time 1248.1 seconds
Started Feb 09 04:37:32 AM UTC 25
Finished Feb 09 04:58:35 AM UTC 25
Peak memory 372220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1152889154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_a
ll_with_rand_reset.1152889154
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.4126049140
Short name T892
Test name
Test status
Simulation time 432353843 ps
CPU time 6.83 seconds
Started Feb 09 04:37:46 AM UTC 25
Finished Feb 09 04:37:54 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126049140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.4126049140
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.50185831
Short name T173
Test name
Test status
Simulation time 268747521 ps
CPU time 5.15 seconds
Started Feb 09 04:37:49 AM UTC 25
Finished Feb 09 04:37:55 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50185831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctr
l_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.50185831
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3899683662
Short name T154
Test name
Test status
Simulation time 146612895233 ps
CPU time 1194.27 seconds
Started Feb 09 04:37:55 AM UTC 25
Finished Feb 09 04:58:02 AM UTC 25
Peak memory 361976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3899683662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_a
ll_with_rand_reset.3899683662
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.3983623919
Short name T893
Test name
Test status
Simulation time 153904386 ps
CPU time 5.93 seconds
Started Feb 09 04:37:56 AM UTC 25
Finished Feb 09 04:38:03 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983623919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3983623919
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.1785941121
Short name T894
Test name
Test status
Simulation time 160433623 ps
CPU time 4.71 seconds
Started Feb 09 04:38:04 AM UTC 25
Finished Feb 09 04:38:10 AM UTC 25
Peak memory 251072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785941121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1785941121
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3001393752
Short name T351
Test name
Test status
Simulation time 139729374325 ps
CPU time 1252.12 seconds
Started Feb 09 04:38:09 AM UTC 25
Finished Feb 09 04:59:15 AM UTC 25
Peak memory 337468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3001393752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_a
ll_with_rand_reset.3001393752
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.2546703580
Short name T409
Test name
Test status
Simulation time 93059806 ps
CPU time 2.48 seconds
Started Feb 09 04:15:12 AM UTC 25
Finished Feb 09 04:15:16 AM UTC 25
Peak memory 251100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546703580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2546703580
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.620866716
Short name T407
Test name
Test status
Simulation time 1151819391 ps
CPU time 14.28 seconds
Started Feb 09 04:14:59 AM UTC 25
Finished Feb 09 04:15:14 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620866716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.620866716
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1848493202
Short name T37
Test name
Test status
Simulation time 4765776748 ps
CPU time 51.54 seconds
Started Feb 09 04:15:04 AM UTC 25
Finished Feb 09 04:15:57 AM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848493202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1848493202
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3323135213
Short name T411
Test name
Test status
Simulation time 884794819 ps
CPU time 13.75 seconds
Started Feb 09 04:15:01 AM UTC 25
Finished Feb 09 04:15:16 AM UTC 25
Peak memory 251200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323135213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3323135213
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3105740484
Short name T408
Test name
Test status
Simulation time 1149101745 ps
CPU time 12.31 seconds
Started Feb 09 04:15:01 AM UTC 25
Finished Feb 09 04:15:15 AM UTC 25
Peak memory 251372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105740484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3105740484
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.419302178
Short name T526
Test name
Test status
Simulation time 8596949363 ps
CPU time 36.87 seconds
Started Feb 09 04:15:04 AM UTC 25
Finished Feb 09 04:15:42 AM UTC 25
Peak memory 253212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419302178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.419302178
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1820091629
Short name T298
Test name
Test status
Simulation time 436743093 ps
CPU time 22.47 seconds
Started Feb 09 04:15:04 AM UTC 25
Finished Feb 09 04:15:27 AM UTC 25
Peak memory 253156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820091629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1820091629
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.2392520809
Short name T422
Test name
Test status
Simulation time 3218647322 ps
CPU time 32.07 seconds
Started Feb 09 04:15:00 AM UTC 25
Finished Feb 09 04:15:33 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392520809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2392520809
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.2098385710
Short name T459
Test name
Test status
Simulation time 8711476723 ps
CPU time 25.55 seconds
Started Feb 09 04:14:59 AM UTC 25
Finished Feb 09 04:15:25 AM UTC 25
Peak memory 257504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098385710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2098385710
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3644164915
Short name T412
Test name
Test status
Simulation time 528139864 ps
CPU time 13.92 seconds
Started Feb 09 04:15:04 AM UTC 25
Finished Feb 09 04:15:19 AM UTC 25
Peak memory 257248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644164915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM
_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3644164915
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2738584952
Short name T273
Test name
Test status
Simulation time 424112531 ps
CPU time 4.32 seconds
Started Feb 09 04:14:56 AM UTC 25
Finished Feb 09 04:15:01 AM UTC 25
Peak memory 253160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738584952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2738584952
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3790617586
Short name T410
Test name
Test status
Simulation time 474916676 ps
CPU time 9.91 seconds
Started Feb 09 04:15:05 AM UTC 25
Finished Feb 09 04:15:16 AM UTC 25
Peak memory 257272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790617586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3790617586
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3541488398
Short name T81
Test name
Test status
Simulation time 1666682376 ps
CPU time 6.73 seconds
Started Feb 09 04:38:10 AM UTC 25
Finished Feb 09 04:38:18 AM UTC 25
Peak memory 253244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541488398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3541488398
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.2292825073
Short name T895
Test name
Test status
Simulation time 1043077261 ps
CPU time 9.38 seconds
Started Feb 09 04:38:20 AM UTC 25
Finished Feb 09 04:38:30 AM UTC 25
Peak memory 251072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292825073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2292825073
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2426092005
Short name T78
Test name
Test status
Simulation time 419480870 ps
CPU time 4.55 seconds
Started Feb 09 04:39:14 AM UTC 25
Finished Feb 09 04:39:19 AM UTC 25
Peak memory 251324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426092005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2426092005
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.2337381157
Short name T174
Test name
Test status
Simulation time 288739315 ps
CPU time 8.74 seconds
Started Feb 09 04:39:20 AM UTC 25
Finished Feb 09 04:39:30 AM UTC 25
Peak memory 253372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337381157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.2337381157
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1645129350
Short name T1188
Test name
Test status
Simulation time 111039686474 ps
CPU time 2669.02 seconds
Started Feb 09 04:39:31 AM UTC 25
Finished Feb 09 05:24:30 AM UTC 25
Peak memory 603616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1645129350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_a
ll_with_rand_reset.1645129350
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.3574142944
Short name T897
Test name
Test status
Simulation time 297952777 ps
CPU time 6.73 seconds
Started Feb 09 04:39:57 AM UTC 25
Finished Feb 09 04:40:05 AM UTC 25
Peak memory 253464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574142944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3574142944
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.1454131258
Short name T898
Test name
Test status
Simulation time 1101470199 ps
CPU time 19.83 seconds
Started Feb 09 04:40:06 AM UTC 25
Finished Feb 09 04:40:27 AM UTC 25
Peak memory 253112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454131258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1454131258
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2070051016
Short name T1181
Test name
Test status
Simulation time 255568331038 ps
CPU time 965.41 seconds
Started Feb 09 04:40:18 AM UTC 25
Finished Feb 09 04:56:34 AM UTC 25
Peak memory 273916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2070051016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_a
ll_with_rand_reset.2070051016
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.1204446198
Short name T899
Test name
Test status
Simulation time 111238926 ps
CPU time 5.48 seconds
Started Feb 09 04:40:28 AM UTC 25
Finished Feb 09 04:40:35 AM UTC 25
Peak memory 253208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204446198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1204446198
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.2861204416
Short name T900
Test name
Test status
Simulation time 299583349 ps
CPU time 6.68 seconds
Started Feb 09 04:40:28 AM UTC 25
Finished Feb 09 04:40:36 AM UTC 25
Peak memory 251172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861204416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2861204416
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.2647003319
Short name T901
Test name
Test status
Simulation time 122079668 ps
CPU time 4.4 seconds
Started Feb 09 04:40:38 AM UTC 25
Finished Feb 09 04:40:44 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647003319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2647003319
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.1710810075
Short name T902
Test name
Test status
Simulation time 110444598 ps
CPU time 6.12 seconds
Started Feb 09 04:40:41 AM UTC 25
Finished Feb 09 04:40:48 AM UTC 25
Peak memory 251040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710810075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1710810075
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1243367884
Short name T1185
Test name
Test status
Simulation time 74033932918 ps
CPU time 2091.17 seconds
Started Feb 09 04:40:44 AM UTC 25
Finished Feb 09 05:15:59 AM UTC 25
Peak memory 269820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1243367884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_a
ll_with_rand_reset.1243367884
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.3787007197
Short name T903
Test name
Test status
Simulation time 169408045 ps
CPU time 6.3 seconds
Started Feb 09 04:40:49 AM UTC 25
Finished Feb 09 04:40:57 AM UTC 25
Peak memory 251388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787007197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3787007197
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.2137593875
Short name T904
Test name
Test status
Simulation time 287609639 ps
CPU time 4.08 seconds
Started Feb 09 04:40:57 AM UTC 25
Finished Feb 09 04:41:03 AM UTC 25
Peak memory 251068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137593875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2137593875
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.663295381
Short name T905
Test name
Test status
Simulation time 109065568 ps
CPU time 4.99 seconds
Started Feb 09 04:41:19 AM UTC 25
Finished Feb 09 04:41:25 AM UTC 25
Peak memory 251128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663295381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.663295381
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.1819040
Short name T906
Test name
Test status
Simulation time 209371334 ps
CPU time 4.53 seconds
Started Feb 09 04:41:26 AM UTC 25
Finished Feb 09 04:41:32 AM UTC 25
Peak memory 251068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl
_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1819040
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3687963709
Short name T1180
Test name
Test status
Simulation time 56027647113 ps
CPU time 882.16 seconds
Started Feb 09 04:41:32 AM UTC 25
Finished Feb 09 04:56:25 AM UTC 25
Peak memory 269820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3687963709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_a
ll_with_rand_reset.3687963709
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2760635290
Short name T907
Test name
Test status
Simulation time 181198129 ps
CPU time 5.81 seconds
Started Feb 09 04:44:17 AM UTC 25
Finished Feb 09 04:44:23 AM UTC 25
Peak memory 251196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760635290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2760635290
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.2769049874
Short name T908
Test name
Test status
Simulation time 186635507 ps
CPU time 13.19 seconds
Started Feb 09 04:44:25 AM UTC 25
Finished Feb 09 04:44:39 AM UTC 25
Peak memory 251232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769049874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2769049874
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1815118846
Short name T1179
Test name
Test status
Simulation time 34846143518 ps
CPU time 632.24 seconds
Started Feb 09 04:44:33 AM UTC 25
Finished Feb 09 04:55:13 AM UTC 25
Peak memory 364028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1815118846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_a
ll_with_rand_reset.1815118846
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3460724368
Short name T910
Test name
Test status
Simulation time 109345150 ps
CPU time 5.3 seconds
Started Feb 09 04:44:40 AM UTC 25
Finished Feb 09 04:44:47 AM UTC 25
Peak memory 251160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460724368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3460724368
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.2728688292
Short name T911
Test name
Test status
Simulation time 5556038868 ps
CPU time 15.6 seconds
Started Feb 09 04:44:45 AM UTC 25
Finished Feb 09 04:45:02 AM UTC 25
Peak memory 253248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728688292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2728688292
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.426919371
Short name T1183
Test name
Test status
Simulation time 87670188246 ps
CPU time 1549.88 seconds
Started Feb 09 04:44:48 AM UTC 25
Finished Feb 09 05:10:55 AM UTC 25
Peak memory 378368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=426919371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_al
l_with_rand_reset.426919371
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.1196923791
Short name T913
Test name
Test status
Simulation time 130691169 ps
CPU time 4.7 seconds
Started Feb 09 04:45:02 AM UTC 25
Finished Feb 09 04:45:08 AM UTC 25
Peak memory 251132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196923791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1196923791
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.639587539
Short name T914
Test name
Test status
Simulation time 259625176 ps
CPU time 9.06 seconds
Started Feb 09 04:45:06 AM UTC 25
Finished Feb 09 04:45:16 AM UTC 25
Peak memory 251320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639587539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ct
rl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.639587539
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.77759094
Short name T354
Test name
Test status
Simulation time 1194047508678 ps
CPU time 2808.23 seconds
Started Feb 09 04:45:09 AM UTC 25
Finished Feb 09 05:32:27 AM UTC 25
Peak memory 497156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl
_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=77759094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all
_with_rand_reset.77759094
Directory /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest
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