| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.51 | 93.58 | 96.60 | 95.50 | 89.64 | 97.21 | 96.03 | 92.99 |
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3367764923 | Oct 15 09:37:14 AM UTC 24 | Oct 15 09:37:17 AM UTC 24 | 67877810 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2841752592 | Oct 15 09:37:14 AM UTC 24 | Oct 15 09:37:18 AM UTC 24 | 637490672 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2481773688 | Oct 15 09:37:13 AM UTC 24 | Oct 15 09:37:20 AM UTC 24 | 1748747557 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1960747490 | Oct 15 09:36:59 AM UTC 24 | Oct 15 09:37:20 AM UTC 24 | 2529064375 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3586494438 | Oct 15 09:37:17 AM UTC 24 | Oct 15 09:37:21 AM UTC 24 | 149759031 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.570316429 | Oct 15 09:37:17 AM UTC 24 | Oct 15 09:37:21 AM UTC 24 | 148755091 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1991726240 | Oct 15 09:37:15 AM UTC 24 | Oct 15 09:37:21 AM UTC 24 | 116010400 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.504178727 | Oct 15 09:37:15 AM UTC 24 | Oct 15 09:37:21 AM UTC 24 | 1699475337 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2397468219 | Oct 15 09:37:19 AM UTC 24 | Oct 15 09:37:22 AM UTC 24 | 97657724 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.602582826 | Oct 15 09:37:13 AM UTC 24 | Oct 15 09:37:22 AM UTC 24 | 1534595315 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1254828181 | Oct 15 09:37:19 AM UTC 24 | Oct 15 09:37:22 AM UTC 24 | 50131545 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3189239394 | Oct 15 09:37:07 AM UTC 24 | Oct 15 09:37:22 AM UTC 24 | 1236339017 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.361773086 | Oct 15 09:37:17 AM UTC 24 | Oct 15 09:37:23 AM UTC 24 | 1132675122 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.757977363 | Oct 15 09:37:17 AM UTC 24 | Oct 15 09:37:23 AM UTC 24 | 380031045 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.34932681 | Oct 15 09:37:16 AM UTC 24 | Oct 15 09:37:23 AM UTC 24 | 219966963 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1271993810 | Oct 15 09:37:21 AM UTC 24 | Oct 15 09:37:24 AM UTC 24 | 76569810 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4048336894 | Oct 15 09:37:19 AM UTC 24 | Oct 15 09:37:25 AM UTC 24 | 218104005 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3717203302 | Oct 15 09:37:22 AM UTC 24 | Oct 15 09:37:25 AM UTC 24 | 101128601 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3102829740 | Oct 15 09:37:22 AM UTC 24 | Oct 15 09:37:25 AM UTC 24 | 79642351 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2195823284 | Oct 15 09:37:28 AM UTC 24 | Oct 15 09:37:31 AM UTC 24 | 41615820 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.3400904862 | Oct 15 09:37:28 AM UTC 24 | Oct 15 09:37:31 AM UTC 24 | 604755291 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2937031033 | Oct 15 09:37:23 AM UTC 24 | Oct 15 09:37:26 AM UTC 24 | 126602600 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1371660689 | Oct 15 09:37:10 AM UTC 24 | Oct 15 09:37:26 AM UTC 24 | 9838441046 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2530029158 | Oct 15 09:37:23 AM UTC 24 | Oct 15 09:37:27 AM UTC 24 | 596063930 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1999704464 | Oct 15 09:37:13 AM UTC 24 | Oct 15 09:37:27 AM UTC 24 | 1190681913 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1545368796 | Oct 15 09:37:24 AM UTC 24 | Oct 15 09:37:27 AM UTC 24 | 70432709 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.446122684 | Oct 15 09:37:23 AM UTC 24 | Oct 15 09:37:27 AM UTC 24 | 112819513 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.1947304304 | Oct 15 09:37:24 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 146176168 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1817654017 | Oct 15 09:37:25 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 42056203 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2041516111 | Oct 15 09:37:24 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 71619363 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.884827893 | Oct 15 09:37:23 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 271675437 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.308733575 | Oct 15 09:37:26 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 136360195 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3328108424 | Oct 15 09:37:22 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 1677183904 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.240093207 | Oct 15 09:37:22 AM UTC 24 | Oct 15 09:37:28 AM UTC 24 | 388022936 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.2995343806 | Oct 15 09:37:26 AM UTC 24 | Oct 15 09:37:29 AM UTC 24 | 49557589 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.3781081444 | Oct 15 09:37:26 AM UTC 24 | Oct 15 09:37:29 AM UTC 24 | 146841576 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.505303453 | Oct 15 09:37:16 AM UTC 24 | Oct 15 09:37:29 AM UTC 24 | 2477533843 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1748607765 | Oct 15 09:37:27 AM UTC 24 | Oct 15 09:37:30 AM UTC 24 | 526732440 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.1033920690 | Oct 15 09:37:27 AM UTC 24 | Oct 15 09:37:30 AM UTC 24 | 47590357 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.109250536 | Oct 15 09:37:27 AM UTC 24 | Oct 15 09:37:30 AM UTC 24 | 155538603 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.1519927373 | Oct 15 09:37:28 AM UTC 24 | Oct 15 09:37:31 AM UTC 24 | 128171993 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.2752156201 | Oct 15 09:37:28 AM UTC 24 | Oct 15 09:37:31 AM UTC 24 | 122370406 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.2404276969 | Oct 15 09:37:28 AM UTC 24 | Oct 15 09:37:32 AM UTC 24 | 117553116 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3089271675 | Oct 15 09:37:13 AM UTC 24 | Oct 15 09:37:32 AM UTC 24 | 1390766438 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2281652940 | Oct 15 09:37:29 AM UTC 24 | Oct 15 09:37:32 AM UTC 24 | 40608140 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.1873627820 | Oct 15 09:37:30 AM UTC 24 | Oct 15 09:37:32 AM UTC 24 | 72666995 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.3599151503 | Oct 15 09:37:29 AM UTC 24 | Oct 15 09:37:32 AM UTC 24 | 93116820 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1415568497 | Oct 15 09:37:29 AM UTC 24 | Oct 15 09:37:33 AM UTC 24 | 41434086 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.2715270709 | Oct 15 09:37:29 AM UTC 24 | Oct 15 09:37:33 AM UTC 24 | 150343699 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.1421712709 | Oct 15 09:37:29 AM UTC 24 | Oct 15 09:37:33 AM UTC 24 | 559543663 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2194448262 | Oct 15 09:37:31 AM UTC 24 | Oct 15 09:37:33 AM UTC 24 | 42487160 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.2916456064 | Oct 15 09:37:31 AM UTC 24 | Oct 15 09:37:33 AM UTC 24 | 167240915 ps | ||
| T1305 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.308230671 | Oct 15 09:37:31 AM UTC 24 | Oct 15 09:37:33 AM UTC 24 | 37322270 ps | ||
| T1306 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1300415496 | Oct 15 09:37:31 AM UTC 24 | Oct 15 09:37:34 AM UTC 24 | 134023235 ps | ||
| T1307 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2440692402 | Oct 15 09:37:22 AM UTC 24 | Oct 15 09:37:34 AM UTC 24 | 636083530 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1104750444 | Oct 15 09:37:02 AM UTC 24 | Oct 15 09:37:34 AM UTC 24 | 1615485017 ps | ||
| T1308 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.2757417883 | Oct 15 09:37:32 AM UTC 24 | Oct 15 09:37:35 AM UTC 24 | 544517368 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3477408622 | Oct 15 09:37:03 AM UTC 24 | Oct 15 09:37:36 AM UTC 24 | 4571804187 ps | ||
| T1309 | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.622955034 | Oct 15 09:37:19 AM UTC 24 | Oct 15 09:37:55 AM UTC 24 | 20404540782 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.347204534 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1242686415 ps |
| CPU time | 10.88 seconds |
| Started | Oct 15 09:37:34 AM UTC 24 |
| Finished | Oct 15 09:37:46 AM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347204534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.347204534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.2999165972 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 613325186 ps |
| CPU time | 13.7 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:37:50 AM UTC 24 |
| Peak memory | 253068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999165972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2999165972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1733126045 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 26186725486 ps |
| CPU time | 54.89 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:38:31 AM UTC 24 |
| Peak memory | 269336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1733126045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.otp_ctrl_stress_all_with_rand_reset.1733126045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.2803843375 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 385362253 ps |
| CPU time | 16.09 seconds |
| Started | Oct 15 09:37:34 AM UTC 24 |
| Finished | Oct 15 09:37:51 AM UTC 24 |
| Peak memory | 259152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803843375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2803843375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.3807683336 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 8430768504 ps |
| CPU time | 49.94 seconds |
| Started | Oct 15 09:37:43 AM UTC 24 |
| Finished | Oct 15 09:38:35 AM UTC 24 |
| Peak memory | 269160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807683336 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.3807683336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.1030197229 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1268158351 ps |
| CPU time | 17.64 seconds |
| Started | Oct 15 09:38:07 AM UTC 24 |
| Finished | Oct 15 09:38:26 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030197229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1030197229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.2709224803 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1550012836 ps |
| CPU time | 16.69 seconds |
| Started | Oct 15 09:37:51 AM UTC 24 |
| Finished | Oct 15 09:38:09 AM UTC 24 |
| Peak memory | 259124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709224803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2709224803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1489696194 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5949557967 ps |
| CPU time | 48.18 seconds |
| Started | Oct 15 09:38:31 AM UTC 24 |
| Finished | Oct 15 09:39:21 AM UTC 24 |
| Peak memory | 256920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489696194 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1489696194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.1930139101 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10535758082 ps |
| CPU time | 181.83 seconds |
| Started | Oct 15 09:37:55 AM UTC 24 |
| Finished | Oct 15 09:41:00 AM UTC 24 |
| Peak memory | 287200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930139101 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1930139101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.2478021214 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 7819795710 ps |
| CPU time | 135.55 seconds |
| Started | Oct 15 09:40:47 AM UTC 24 |
| Finished | Oct 15 09:43:05 AM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478021214 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.2478021214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.393250632 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1350628819 ps |
| CPU time | 14.92 seconds |
| Started | Oct 15 09:37:33 AM UTC 24 |
| Finished | Oct 15 09:37:50 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393250632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.393250632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.2512275751 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 897332430 ps |
| CPU time | 24.19 seconds |
| Started | Oct 15 09:37:36 AM UTC 24 |
| Finished | Oct 15 09:38:02 AM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512275751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2512275751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.2140614609 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11303928717 ps |
| CPU time | 84.34 seconds |
| Started | Oct 15 09:38:02 AM UTC 24 |
| Finished | Oct 15 09:39:28 AM UTC 24 |
| Peak memory | 259108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2140614609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.otp_ctrl_stress_all_with_rand_reset.2140614609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.198332228 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 7907863579 ps |
| CPU time | 85.02 seconds |
| Started | Oct 15 09:38:23 AM UTC 24 |
| Finished | Oct 15 09:39:50 AM UTC 24 |
| Peak memory | 267372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198332228 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.198332228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.3150741477 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3646129226 ps |
| CPU time | 29.99 seconds |
| Started | Oct 15 09:38:09 AM UTC 24 |
| Finished | Oct 15 09:38:41 AM UTC 24 |
| Peak memory | 257264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150741477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3150741477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.3166884963 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 304012171 ps |
| CPU time | 4.82 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:37:41 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166884963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3166884963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.123987983 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2064607746 ps |
| CPU time | 31.83 seconds |
| Started | Oct 15 09:39:39 AM UTC 24 |
| Finished | Oct 15 09:40:12 AM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123987983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.123987983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2613059959 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 174187664 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 09:46:12 AM UTC 24 |
| Finished | Oct 15 09:46:18 AM UTC 24 |
| Peak memory | 255024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613059959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2613059959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3204851482 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 897801666 ps |
| CPU time | 14.23 seconds |
| Started | Oct 15 09:36:25 AM UTC 24 |
| Finished | Oct 15 09:36:40 AM UTC 24 |
| Peak memory | 250700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204851482 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.3204851482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1351118327 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 185107319 ps |
| CPU time | 5.92 seconds |
| Started | Oct 15 09:38:25 AM UTC 24 |
| Finished | Oct 15 09:38:32 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351118327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1351118327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.2473476155 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 23054218001 ps |
| CPU time | 61.71 seconds |
| Started | Oct 15 09:38:09 AM UTC 24 |
| Finished | Oct 15 09:39:13 AM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473476155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2473476155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.155967078 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 631629812 ps |
| CPU time | 13.37 seconds |
| Started | Oct 15 09:37:52 AM UTC 24 |
| Finished | Oct 15 09:38:06 AM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155967078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.155967078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.4086005449 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 13929222372 ps |
| CPU time | 157.55 seconds |
| Started | Oct 15 09:38:44 AM UTC 24 |
| Finished | Oct 15 09:41:25 AM UTC 24 |
| Peak memory | 271316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4086005449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.otp_ctrl_stress_all_with_rand_reset.4086005449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.3647406741 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 29651989219 ps |
| CPU time | 46.95 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:40:06 AM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647406741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3647406741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.2061689379 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 11049451539 ps |
| CPU time | 26.7 seconds |
| Started | Oct 15 09:37:52 AM UTC 24 |
| Finished | Oct 15 09:38:20 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061689379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2061689379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.1213602145 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 256850633 ps |
| CPU time | 3.62 seconds |
| Started | Oct 15 09:45:42 AM UTC 24 |
| Finished | Oct 15 09:45:47 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213602145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1213602145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.766254626 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2761766405 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 09:38:06 AM UTC 24 |
| Finished | Oct 15 09:38:13 AM UTC 24 |
| Peak memory | 254776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766254626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.766254626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.2796544879 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 10824327997 ps |
| CPU time | 122.84 seconds |
| Started | Oct 15 09:39:03 AM UTC 24 |
| Finished | Oct 15 09:41:08 AM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796544879 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.2796544879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2418310088 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1197048484 ps |
| CPU time | 6.51 seconds |
| Started | Oct 15 09:36:14 AM UTC 24 |
| Finished | Oct 15 09:36:22 AM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418310088 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.2418310088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.2037515004 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 163705010 ps |
| CPU time | 2.74 seconds |
| Started | Oct 15 09:38:14 AM UTC 24 |
| Finished | Oct 15 09:38:18 AM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037515004 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2037515004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3997452272 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 8132048642 ps |
| CPU time | 144.31 seconds |
| Started | Oct 15 09:44:27 AM UTC 24 |
| Finished | Oct 15 09:46:54 AM UTC 24 |
| Peak memory | 269416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3997452272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.3997452272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.387275638 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2205919581 ps |
| CPU time | 19.09 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:39:02 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387275638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.387275638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.2668302324 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 10359087136 ps |
| CPU time | 199.44 seconds |
| Started | Oct 15 09:40:09 AM UTC 24 |
| Finished | Oct 15 09:43:32 AM UTC 24 |
| Peak memory | 287928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668302324 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.2668302324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.637818918 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 97554002 ps |
| CPU time | 3.47 seconds |
| Started | Oct 15 09:39:41 AM UTC 24 |
| Finished | Oct 15 09:39:46 AM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637818918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.637818918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.2934800274 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1585767274 ps |
| CPU time | 27.18 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:43:21 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934800274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2934800274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.866049225 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 288128492 ps |
| CPU time | 15.1 seconds |
| Started | Oct 15 09:37:34 AM UTC 24 |
| Finished | Oct 15 09:37:50 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866049225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.866049225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3865995157 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 293161410 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:13 AM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865995157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3865995157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.3950572894 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1341127494 ps |
| CPU time | 28.63 seconds |
| Started | Oct 15 09:38:04 AM UTC 24 |
| Finished | Oct 15 09:38:34 AM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950572894 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.3950572894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2476239546 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 24183324928 ps |
| CPU time | 129.55 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:48:40 AM UTC 24 |
| Peak memory | 259116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2476239546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 99.otp_ctrl_stress_all_with_rand_reset.2476239546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.1207392630 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 640220916 ps |
| CPU time | 12.39 seconds |
| Started | Oct 15 09:41:17 AM UTC 24 |
| Finished | Oct 15 09:41:31 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207392630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1207392630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.3074806376 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 17152684759 ps |
| CPU time | 40.53 seconds |
| Started | Oct 15 09:38:29 AM UTC 24 |
| Finished | Oct 15 09:39:12 AM UTC 24 |
| Peak memory | 259056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074806376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3074806376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.1366377488 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 521990965 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 09:39:05 AM UTC 24 |
| Finished | Oct 15 09:39:12 AM UTC 24 |
| Peak memory | 254708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366377488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1366377488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3844789729 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 150661451 ps |
| CPU time | 3.88 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844789729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3844789729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.2137451401 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2574252682 ps |
| CPU time | 7.72 seconds |
| Started | Oct 15 09:43:32 AM UTC 24 |
| Finished | Oct 15 09:43:41 AM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137451401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.2137451401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2940483637 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 5232847312 ps |
| CPU time | 38.37 seconds |
| Started | Oct 15 09:38:09 AM UTC 24 |
| Finished | Oct 15 09:38:49 AM UTC 24 |
| Peak memory | 258864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940483637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2940483637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1972050540 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 58867247702 ps |
| CPU time | 156.38 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:48:59 AM UTC 24 |
| Peak memory | 285392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1972050540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 94.otp_ctrl_stress_all_with_rand_reset.1972050540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.68718089 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 31372288289 ps |
| CPU time | 227.68 seconds |
| Started | Oct 15 09:38:39 AM UTC 24 |
| Finished | Oct 15 09:42:30 AM UTC 24 |
| Peak memory | 271636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68718089 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.68718089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.794160459 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 122606742 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 09:37:32 AM UTC 24 |
| Finished | Oct 15 09:37:38 AM UTC 24 |
| Peak memory | 254752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794160459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.794160459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.821696700 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 673702963 ps |
| CPU time | 12.98 seconds |
| Started | Oct 15 09:38:00 AM UTC 24 |
| Finished | Oct 15 09:38:14 AM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821696700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.821696700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.2631928002 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 88499583895 ps |
| CPU time | 272.71 seconds |
| Started | Oct 15 09:40:02 AM UTC 24 |
| Finished | Oct 15 09:44:38 AM UTC 24 |
| Peak memory | 269336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631928002 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.2631928002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2066751153 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1568701216 ps |
| CPU time | 16.45 seconds |
| Started | Oct 15 09:39:07 AM UTC 24 |
| Finished | Oct 15 09:39:25 AM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066751153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2066751153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3649807315 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 15328066410 ps |
| CPU time | 129.73 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:45:36 AM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649807315 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3649807315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.3412112022 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 224741725 ps |
| CPU time | 5.53 seconds |
| Started | Oct 15 09:39:50 AM UTC 24 |
| Finished | Oct 15 09:39:57 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412112022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3412112022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.2824308632 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1702106395 ps |
| CPU time | 27.53 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:39:20 AM UTC 24 |
| Peak memory | 252336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824308632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2824308632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.3471977628 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 6643931803 ps |
| CPU time | 147.85 seconds |
| Started | Oct 15 09:41:04 AM UTC 24 |
| Finished | Oct 15 09:43:35 AM UTC 24 |
| Peak memory | 275616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471977628 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.3471977628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.805084622 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 215485456 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805084622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.805084622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.4053497528 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4578670661 ps |
| CPU time | 103.39 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:44:38 AM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4053497528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.otp_ctrl_stress_all_with_rand_reset.4053497528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.2764735945 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 10637725487 ps |
| CPU time | 32.5 seconds |
| Started | Oct 15 09:38:37 AM UTC 24 |
| Finished | Oct 15 09:39:11 AM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764735945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2764735945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.623528682 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1140146919 ps |
| CPU time | 15.59 seconds |
| Started | Oct 15 09:41:52 AM UTC 24 |
| Finished | Oct 15 09:42:09 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623528682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.623528682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1104750444 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1615485017 ps |
| CPU time | 30.2 seconds |
| Started | Oct 15 09:37:02 AM UTC 24 |
| Finished | Oct 15 09:37:34 AM UTC 24 |
| Peak memory | 254060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104750444 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.1104750444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.4078403204 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1145016517 ps |
| CPU time | 12.34 seconds |
| Started | Oct 15 09:39:07 AM UTC 24 |
| Finished | Oct 15 09:39:21 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078403204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.4078403204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.3922520330 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4199440213 ps |
| CPU time | 36.27 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:55 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922520330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3922520330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.2998032415 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 478143749 ps |
| CPU time | 7.88 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:27 AM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998032415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2998032415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.4233329832 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 199053240 ps |
| CPU time | 5.19 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:24 AM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233329832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.4233329832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.270616428 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 448748536 ps |
| CPU time | 9.83 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:34 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270616428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.270616428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.893474444 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 519118121 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893474444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.893474444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.447138751 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 217442005 ps |
| CPU time | 9.95 seconds |
| Started | Oct 15 09:45:18 AM UTC 24 |
| Finished | Oct 15 09:45:29 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447138751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.447138751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.1072728291 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 987071327 ps |
| CPU time | 13.42 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:32 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072728291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.1072728291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.4251177351 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 17852599997 ps |
| CPU time | 131.58 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:41:32 AM UTC 24 |
| Peak memory | 259368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251177351 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.4251177351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2750452413 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 140200309 ps |
| CPU time | 2.54 seconds |
| Started | Oct 15 09:36:46 AM UTC 24 |
| Finished | Oct 15 09:36:50 AM UTC 24 |
| Peak memory | 250628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750452413 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2750452413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3766698719 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 29570221961 ps |
| CPU time | 160.87 seconds |
| Started | Oct 15 09:42:01 AM UTC 24 |
| Finished | Oct 15 09:44:45 AM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3766698719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.otp_ctrl_stress_all_with_rand_reset.3766698719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3312480900 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2853529565 ps |
| CPU time | 40.81 seconds |
| Started | Oct 15 09:40:53 AM UTC 24 |
| Finished | Oct 15 09:41:35 AM UTC 24 |
| Peak memory | 256968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312480900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3312480900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.3561807173 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1190687010 ps |
| CPU time | 13.2 seconds |
| Started | Oct 15 09:37:51 AM UTC 24 |
| Finished | Oct 15 09:38:06 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561807173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3561807173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1371660689 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 9838441046 ps |
| CPU time | 15.05 seconds |
| Started | Oct 15 09:37:10 AM UTC 24 |
| Finished | Oct 15 09:37:26 AM UTC 24 |
| Peak memory | 251024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371660689 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1371660689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.1182805971 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 815043100 ps |
| CPU time | 27.16 seconds |
| Started | Oct 15 09:41:36 AM UTC 24 |
| Finished | Oct 15 09:42:05 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182805971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1182805971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.1287259670 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1524546786 ps |
| CPU time | 21.59 seconds |
| Started | Oct 15 09:38:16 AM UTC 24 |
| Finished | Oct 15 09:38:38 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287259670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1287259670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.2945473870 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 11771497108 ps |
| CPU time | 29.98 seconds |
| Started | Oct 15 09:40:06 AM UTC 24 |
| Finished | Oct 15 09:40:38 AM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945473870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2945473870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.2228819242 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 418995287 ps |
| CPU time | 5.96 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:58 AM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228819242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2228819242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2433362653 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 67012120330 ps |
| CPU time | 126.57 seconds |
| Started | Oct 15 09:40:55 AM UTC 24 |
| Finished | Oct 15 09:43:04 AM UTC 24 |
| Peak memory | 269416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2433362653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.otp_ctrl_stress_all_with_rand_reset.2433362653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1464802034 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1535328906 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 09:38:53 AM UTC 24 |
| Finished | Oct 15 09:38:59 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464802034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1464802034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.242730557 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 293268821 ps |
| CPU time | 5.92 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:50 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242730557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.242730557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.3709652409 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 346362728 ps |
| CPU time | 4.45 seconds |
| Started | Oct 15 09:46:44 AM UTC 24 |
| Finished | Oct 15 09:46:50 AM UTC 24 |
| Peak memory | 254744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709652409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3709652409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.950467924 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 567161345 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:46:57 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950467924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.950467924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1422467272 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 29216590667 ps |
| CPU time | 163.58 seconds |
| Started | Oct 15 09:39:30 AM UTC 24 |
| Finished | Oct 15 09:42:16 AM UTC 24 |
| Peak memory | 275552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1422467272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.otp_ctrl_stress_all_with_rand_reset.1422467272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2498202865 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5934428285 ps |
| CPU time | 90.64 seconds |
| Started | Oct 15 09:41:37 AM UTC 24 |
| Finished | Oct 15 09:43:09 AM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2498202865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.otp_ctrl_stress_all_with_rand_reset.2498202865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.4066791254 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 22269613231 ps |
| CPU time | 90.59 seconds |
| Started | Oct 15 09:42:15 AM UTC 24 |
| Finished | Oct 15 09:43:47 AM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066791254 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.4066791254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.2268011283 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 9081214191 ps |
| CPU time | 32.27 seconds |
| Started | Oct 15 09:37:34 AM UTC 24 |
| Finished | Oct 15 09:38:07 AM UTC 24 |
| Peak memory | 254960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268011283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2268011283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1960747490 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2529064375 ps |
| CPU time | 20.3 seconds |
| Started | Oct 15 09:36:59 AM UTC 24 |
| Finished | Oct 15 09:37:20 AM UTC 24 |
| Peak memory | 254948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960747490 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.1960747490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3477408622 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4571804187 ps |
| CPU time | 30.4 seconds |
| Started | Oct 15 09:37:03 AM UTC 24 |
| Finished | Oct 15 09:37:36 AM UTC 24 |
| Peak memory | 255012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477408622 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.3477408622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3586494438 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 149759031 ps |
| CPU time | 2.52 seconds |
| Started | Oct 15 09:37:17 AM UTC 24 |
| Finished | Oct 15 09:37:21 AM UTC 24 |
| Peak memory | 250644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586494438 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3586494438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.3023745297 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 72201962 ps |
| CPU time | 1.94 seconds |
| Started | Oct 15 09:37:32 AM UTC 24 |
| Finished | Oct 15 09:37:35 AM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023745297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3023745297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.1182914225 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 766707476 ps |
| CPU time | 13.01 seconds |
| Started | Oct 15 09:38:17 AM UTC 24 |
| Finished | Oct 15 09:38:31 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182914225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1182914225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.3814837925 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7612952702 ps |
| CPU time | 18.2 seconds |
| Started | Oct 15 09:37:40 AM UTC 24 |
| Finished | Oct 15 09:37:59 AM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814837925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.3814837925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.1648573372 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 7445249410 ps |
| CPU time | 20.11 seconds |
| Started | Oct 15 09:39:29 AM UTC 24 |
| Finished | Oct 15 09:39:51 AM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648573372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1648573372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4224601325 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4758802851 ps |
| CPU time | 22.7 seconds |
| Started | Oct 15 09:36:42 AM UTC 24 |
| Finished | Oct 15 09:37:06 AM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224601325 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.4224601325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.3706363824 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2601668175 ps |
| CPU time | 24.9 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:21 AM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706363824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3706363824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.1002766258 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 177298803 ps |
| CPU time | 3.94 seconds |
| Started | Oct 15 09:47:58 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002766258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1002766258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.3927783598 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1089770020 ps |
| CPU time | 9.91 seconds |
| Started | Oct 15 09:38:25 AM UTC 24 |
| Finished | Oct 15 09:38:36 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927783598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.3927783598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.415003236 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6322692799 ps |
| CPU time | 69.5 seconds |
| Started | Oct 15 09:39:13 AM UTC 24 |
| Finished | Oct 15 09:40:25 AM UTC 24 |
| Peak memory | 259068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415003236 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.415003236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.2099713706 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 185468682 ps |
| CPU time | 3.84 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099713706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2099713706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3635953151 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 225357014 ps |
| CPU time | 10.19 seconds |
| Started | Oct 15 09:39:05 AM UTC 24 |
| Finished | Oct 15 09:39:16 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635953151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3635953151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.906676609 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 173368284708 ps |
| CPU time | 229.19 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:41:28 AM UTC 24 |
| Peak memory | 299336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906676609 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.906676609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.2875859452 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 259860372 ps |
| CPU time | 6.86 seconds |
| Started | Oct 15 09:38:57 AM UTC 24 |
| Finished | Oct 15 09:39:06 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875859452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2875859452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.559311396 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 837851855 ps |
| CPU time | 9.67 seconds |
| Started | Oct 15 09:36:14 AM UTC 24 |
| Finished | Oct 15 09:36:25 AM UTC 24 |
| Peak memory | 250560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559311396 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.559311396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.4289243527 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 74711967 ps |
| CPU time | 3.13 seconds |
| Started | Oct 15 09:36:13 AM UTC 24 |
| Finished | Oct 15 09:36:17 AM UTC 24 |
| Peak memory | 250652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289243527 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.4289243527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.54017636 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1668295135 ps |
| CPU time | 5.16 seconds |
| Started | Oct 15 09:36:17 AM UTC 24 |
| Finished | Oct 15 09:36:23 AM UTC 24 |
| Peak memory | 257060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=54017636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_ mem_rw_with_rand_reset.54017636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.735827989 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 667208563 ps |
| CPU time | 2.93 seconds |
| Started | Oct 15 09:36:14 AM UTC 24 |
| Finished | Oct 15 09:36:18 AM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735827989 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.735827989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1666684339 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 37564638 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 09:36:09 AM UTC 24 |
| Finished | Oct 15 09:36:12 AM UTC 24 |
| Peak memory | 240524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666684339 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1666684339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1475865033 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 72546477 ps |
| CPU time | 2.04 seconds |
| Started | Oct 15 09:36:12 AM UTC 24 |
| Finished | Oct 15 09:36:15 AM UTC 24 |
| Peak memory | 239888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475865033 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.1475865033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1504032223 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 538318496 ps |
| CPU time | 3.48 seconds |
| Started | Oct 15 09:36:09 AM UTC 24 |
| Finished | Oct 15 09:36:13 AM UTC 24 |
| Peak memory | 240172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504032223 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.1504032223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3748201779 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 90046221 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 09:36:15 AM UTC 24 |
| Finished | Oct 15 09:36:20 AM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748201779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.3748201779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1871144896 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 121195986 ps |
| CPU time | 4.52 seconds |
| Started | Oct 15 09:36:07 AM UTC 24 |
| Finished | Oct 15 09:36:13 AM UTC 24 |
| Peak memory | 256940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871144896 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1871144896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2870997717 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 20068072503 ps |
| CPU time | 25.19 seconds |
| Started | Oct 15 09:36:08 AM UTC 24 |
| Finished | Oct 15 09:36:35 AM UTC 24 |
| Peak memory | 255072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870997717 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.2870997717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.893957922 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 95013508 ps |
| CPU time | 4.28 seconds |
| Started | Oct 15 09:36:23 AM UTC 24 |
| Finished | Oct 15 09:36:28 AM UTC 24 |
| Peak memory | 250628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893957922 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.893957922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.111620008 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 166685736 ps |
| CPU time | 5.12 seconds |
| Started | Oct 15 09:36:23 AM UTC 24 |
| Finished | Oct 15 09:36:29 AM UTC 24 |
| Peak memory | 250620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111620008 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.111620008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2174843264 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 249948109 ps |
| CPU time | 3.15 seconds |
| Started | Oct 15 09:36:22 AM UTC 24 |
| Finished | Oct 15 09:36:26 AM UTC 24 |
| Peak memory | 250584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174843264 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.2174843264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.460232485 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 998895991 ps |
| CPU time | 5.55 seconds |
| Started | Oct 15 09:36:24 AM UTC 24 |
| Finished | Oct 15 09:36:30 AM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=460232485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr _mem_rw_with_rand_reset.460232485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1162816078 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 129367839 ps |
| CPU time | 2.44 seconds |
| Started | Oct 15 09:36:23 AM UTC 24 |
| Finished | Oct 15 09:36:26 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162816078 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1162816078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.759563799 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 77954439 ps |
| CPU time | 2.44 seconds |
| Started | Oct 15 09:36:18 AM UTC 24 |
| Finished | Oct 15 09:36:22 AM UTC 24 |
| Peak memory | 239840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759563799 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.759563799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4159608356 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 42337304 ps |
| CPU time | 2.19 seconds |
| Started | Oct 15 09:36:22 AM UTC 24 |
| Finished | Oct 15 09:36:25 AM UTC 24 |
| Peak memory | 239520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159608356 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.4159608356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3854773171 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 544670783 ps |
| CPU time | 2.18 seconds |
| Started | Oct 15 09:36:20 AM UTC 24 |
| Finished | Oct 15 09:36:24 AM UTC 24 |
| Peak memory | 239712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854773171 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.3854773171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3511628473 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 189489451 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 09:36:23 AM UTC 24 |
| Finished | Oct 15 09:36:26 AM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511628473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.3511628473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1528343334 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 87330015 ps |
| CPU time | 3.52 seconds |
| Started | Oct 15 09:36:17 AM UTC 24 |
| Finished | Oct 15 09:36:22 AM UTC 24 |
| Peak memory | 257064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528343334 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1528343334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.351234765 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2008004290 ps |
| CPU time | 11.97 seconds |
| Started | Oct 15 09:36:18 AM UTC 24 |
| Finished | Oct 15 09:36:31 AM UTC 24 |
| Peak memory | 250920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351234765 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.351234765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3522286503 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 109103112 ps |
| CPU time | 3.79 seconds |
| Started | Oct 15 09:37:01 AM UTC 24 |
| Finished | Oct 15 09:37:07 AM UTC 24 |
| Peak memory | 256808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3522286503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.3522286503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.859987154 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 598624857 ps |
| CPU time | 2.5 seconds |
| Started | Oct 15 09:37:00 AM UTC 24 |
| Finished | Oct 15 09:37:04 AM UTC 24 |
| Peak memory | 256772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859987154 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.859987154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.2776762212 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 43021062 ps |
| CPU time | 2.28 seconds |
| Started | Oct 15 09:36:59 AM UTC 24 |
| Finished | Oct 15 09:37:02 AM UTC 24 |
| Peak memory | 240140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776762212 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2776762212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3844008071 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 1263680682 ps |
| CPU time | 7.46 seconds |
| Started | Oct 15 09:37:01 AM UTC 24 |
| Finished | Oct 15 09:37:10 AM UTC 24 |
| Peak memory | 250716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844008071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.3844008071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1051304133 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 102943313 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 09:36:57 AM UTC 24 |
| Finished | Oct 15 09:37:03 AM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051304133 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1051304133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.491887361 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 160324267 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 09:37:03 AM UTC 24 |
| Finished | Oct 15 09:37:07 AM UTC 24 |
| Peak memory | 256904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=491887361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_cs r_mem_rw_with_rand_reset.491887361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1128021325 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 56447149 ps |
| CPU time | 1.56 seconds |
| Started | Oct 15 09:37:02 AM UTC 24 |
| Finished | Oct 15 09:37:05 AM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128021325 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1128021325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.4184002691 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 40176804 ps |
| CPU time | 1.55 seconds |
| Started | Oct 15 09:37:02 AM UTC 24 |
| Finished | Oct 15 09:37:05 AM UTC 24 |
| Peak memory | 238436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184002691 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.4184002691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2317524691 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 98935447 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 09:37:02 AM UTC 24 |
| Finished | Oct 15 09:37:08 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317524691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.2317524691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.735689799 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 272261170 ps |
| CPU time | 7.38 seconds |
| Started | Oct 15 09:37:01 AM UTC 24 |
| Finished | Oct 15 09:37:10 AM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735689799 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.735689799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2786633199 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 193073356 ps |
| CPU time | 3.97 seconds |
| Started | Oct 15 09:37:07 AM UTC 24 |
| Finished | Oct 15 09:37:12 AM UTC 24 |
| Peak memory | 256920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2786633199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.2786633199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.947891257 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 44936072 ps |
| CPU time | 2.02 seconds |
| Started | Oct 15 09:37:05 AM UTC 24 |
| Finished | Oct 15 09:37:09 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947891257 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.947891257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3138441262 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 621921828 ps |
| CPU time | 2.21 seconds |
| Started | Oct 15 09:37:05 AM UTC 24 |
| Finished | Oct 15 09:37:09 AM UTC 24 |
| Peak memory | 240588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138441262 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3138441262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1831625205 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 99907322 ps |
| CPU time | 2.94 seconds |
| Started | Oct 15 09:37:05 AM UTC 24 |
| Finished | Oct 15 09:37:10 AM UTC 24 |
| Peak memory | 250644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831625205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.1831625205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3554314739 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 172153106 ps |
| CPU time | 6.57 seconds |
| Started | Oct 15 09:37:03 AM UTC 24 |
| Finished | Oct 15 09:37:11 AM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554314739 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3554314739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.39254591 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 98977426 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 09:37:09 AM UTC 24 |
| Finished | Oct 15 09:37:13 AM UTC 24 |
| Peak memory | 254844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=39254591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr _mem_rw_with_rand_reset.39254591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2947557621 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 44774111 ps |
| CPU time | 2.35 seconds |
| Started | Oct 15 09:37:08 AM UTC 24 |
| Finished | Oct 15 09:37:11 AM UTC 24 |
| Peak memory | 250656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947557621 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2947557621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1905194941 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 37703638 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 09:37:08 AM UTC 24 |
| Finished | Oct 15 09:37:11 AM UTC 24 |
| Peak memory | 240148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905194941 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1905194941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3098784765 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 66694563 ps |
| CPU time | 2.08 seconds |
| Started | Oct 15 09:37:09 AM UTC 24 |
| Finished | Oct 15 09:37:12 AM UTC 24 |
| Peak memory | 250760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098784765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.3098784765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3689061099 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 167603017 ps |
| CPU time | 8.21 seconds |
| Started | Oct 15 09:37:07 AM UTC 24 |
| Finished | Oct 15 09:37:16 AM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689061099 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3689061099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3189239394 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 1236339017 ps |
| CPU time | 14.4 seconds |
| Started | Oct 15 09:37:07 AM UTC 24 |
| Finished | Oct 15 09:37:22 AM UTC 24 |
| Peak memory | 254880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189239394 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.3189239394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.128565666 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 271031260 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 09:37:11 AM UTC 24 |
| Finished | Oct 15 09:37:17 AM UTC 24 |
| Peak memory | 256964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=128565666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_cs r_mem_rw_with_rand_reset.128565666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2466191842 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 149554966 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 09:37:10 AM UTC 24 |
| Finished | Oct 15 09:37:14 AM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466191842 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2466191842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.66967810 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 101195524 ps |
| CPU time | 1.44 seconds |
| Started | Oct 15 09:37:10 AM UTC 24 |
| Finished | Oct 15 09:37:13 AM UTC 24 |
| Peak memory | 240452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66967810 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.66967810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1500178152 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 73467420 ps |
| CPU time | 1.86 seconds |
| Started | Oct 15 09:37:11 AM UTC 24 |
| Finished | Oct 15 09:37:14 AM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500178152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.1500178152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.561126301 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 1153642625 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 09:37:10 AM UTC 24 |
| Finished | Oct 15 09:37:15 AM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561126301 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.561126301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2481773688 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 1748747557 ps |
| CPU time | 6.18 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:20 AM UTC 24 |
| Peak memory | 256964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2481773688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.2481773688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2041249418 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 79551892 ps |
| CPU time | 2.61 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:16 AM UTC 24 |
| Peak memory | 250652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041249418 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2041249418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2611284198 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 36408106 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:16 AM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611284198 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2611284198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.226937608 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 302791818 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:17 AM UTC 24 |
| Peak memory | 250716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226937608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.226937608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1985581321 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 1582994946 ps |
| CPU time | 4.35 seconds |
| Started | Oct 15 09:37:11 AM UTC 24 |
| Finished | Oct 15 09:37:17 AM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985581321 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1985581321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3089271675 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1390766438 ps |
| CPU time | 17.79 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:32 AM UTC 24 |
| Peak memory | 254712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089271675 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.3089271675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.504178727 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 1699475337 ps |
| CPU time | 4.95 seconds |
| Started | Oct 15 09:37:15 AM UTC 24 |
| Finished | Oct 15 09:37:21 AM UTC 24 |
| Peak memory | 257032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=504178727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_cs r_mem_rw_with_rand_reset.504178727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2841752592 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 637490672 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 09:37:14 AM UTC 24 |
| Finished | Oct 15 09:37:18 AM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841752592 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2841752592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3367764923 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 67877810 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 09:37:14 AM UTC 24 |
| Finished | Oct 15 09:37:17 AM UTC 24 |
| Peak memory | 239836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367764923 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3367764923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1991726240 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 116010400 ps |
| CPU time | 4.89 seconds |
| Started | Oct 15 09:37:15 AM UTC 24 |
| Finished | Oct 15 09:37:21 AM UTC 24 |
| Peak memory | 252804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991726240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.1991726240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.602582826 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 1534595315 ps |
| CPU time | 8 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:22 AM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602582826 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.602582826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1999704464 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1190681913 ps |
| CPU time | 13.01 seconds |
| Started | Oct 15 09:37:13 AM UTC 24 |
| Finished | Oct 15 09:37:27 AM UTC 24 |
| Peak memory | 254924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999704464 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.1999704464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.361773086 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 1132675122 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 09:37:17 AM UTC 24 |
| Finished | Oct 15 09:37:23 AM UTC 24 |
| Peak memory | 256832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=361773086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_cs r_mem_rw_with_rand_reset.361773086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.570316429 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 148755091 ps |
| CPU time | 2.51 seconds |
| Started | Oct 15 09:37:17 AM UTC 24 |
| Finished | Oct 15 09:37:21 AM UTC 24 |
| Peak memory | 239848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570316429 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.570316429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.757977363 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 380031045 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 09:37:17 AM UTC 24 |
| Finished | Oct 15 09:37:23 AM UTC 24 |
| Peak memory | 250692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757977363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.757977363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.34932681 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 219966963 ps |
| CPU time | 5.9 seconds |
| Started | Oct 15 09:37:16 AM UTC 24 |
| Finished | Oct 15 09:37:23 AM UTC 24 |
| Peak memory | 257088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34932681 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.34932681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.505303453 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2477533843 ps |
| CPU time | 11.51 seconds |
| Started | Oct 15 09:37:16 AM UTC 24 |
| Finished | Oct 15 09:37:29 AM UTC 24 |
| Peak memory | 250764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505303453 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.505303453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3328108424 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 1677183904 ps |
| CPU time | 5.24 seconds |
| Started | Oct 15 09:37:22 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 256900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3328108424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.3328108424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1254828181 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 50131545 ps |
| CPU time | 2.43 seconds |
| Started | Oct 15 09:37:19 AM UTC 24 |
| Finished | Oct 15 09:37:22 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254828181 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1254828181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2397468219 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 97657724 ps |
| CPU time | 2.22 seconds |
| Started | Oct 15 09:37:19 AM UTC 24 |
| Finished | Oct 15 09:37:22 AM UTC 24 |
| Peak memory | 239632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397468219 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2397468219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1271993810 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 76569810 ps |
| CPU time | 2.48 seconds |
| Started | Oct 15 09:37:21 AM UTC 24 |
| Finished | Oct 15 09:37:24 AM UTC 24 |
| Peak memory | 250760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271993810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.1271993810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4048336894 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 218104005 ps |
| CPU time | 4.96 seconds |
| Started | Oct 15 09:37:19 AM UTC 24 |
| Finished | Oct 15 09:37:25 AM UTC 24 |
| Peak memory | 256964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048336894 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.4048336894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.622955034 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 20404540782 ps |
| CPU time | 34.72 seconds |
| Started | Oct 15 09:37:19 AM UTC 24 |
| Finished | Oct 15 09:37:55 AM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622955034 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.622955034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.884827893 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 271675437 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 09:37:23 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 249852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=884827893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_cs r_mem_rw_with_rand_reset.884827893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3717203302 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 101128601 ps |
| CPU time | 1.92 seconds |
| Started | Oct 15 09:37:22 AM UTC 24 |
| Finished | Oct 15 09:37:25 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717203302 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3717203302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3102829740 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 79642351 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 09:37:22 AM UTC 24 |
| Finished | Oct 15 09:37:25 AM UTC 24 |
| Peak memory | 239828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102829740 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3102829740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.446122684 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 112819513 ps |
| CPU time | 3.27 seconds |
| Started | Oct 15 09:37:23 AM UTC 24 |
| Finished | Oct 15 09:37:27 AM UTC 24 |
| Peak memory | 250624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446122684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.446122684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.240093207 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 388022936 ps |
| CPU time | 5.24 seconds |
| Started | Oct 15 09:37:22 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 250852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240093207 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.240093207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2440692402 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 636083530 ps |
| CPU time | 10.5 seconds |
| Started | Oct 15 09:37:22 AM UTC 24 |
| Finished | Oct 15 09:37:34 AM UTC 24 |
| Peak memory | 250700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440692402 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.2440692402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1400596465 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1220628469 ps |
| CPU time | 9 seconds |
| Started | Oct 15 09:36:28 AM UTC 24 |
| Finished | Oct 15 09:36:39 AM UTC 24 |
| Peak memory | 250624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400596465 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.1400596465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2353359540 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 485268331 ps |
| CPU time | 13.68 seconds |
| Started | Oct 15 09:36:27 AM UTC 24 |
| Finished | Oct 15 09:36:42 AM UTC 24 |
| Peak memory | 250756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353359540 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.2353359540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.908996029 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 195723189 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 09:36:27 AM UTC 24 |
| Finished | Oct 15 09:36:31 AM UTC 24 |
| Peak memory | 250712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908996029 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.908996029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2784572668 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 105013626 ps |
| CPU time | 5.45 seconds |
| Started | Oct 15 09:36:30 AM UTC 24 |
| Finished | Oct 15 09:36:36 AM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2784572668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.2784572668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3863620778 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 75299906 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 09:36:27 AM UTC 24 |
| Finished | Oct 15 09:36:30 AM UTC 24 |
| Peak memory | 250560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863620778 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3863620778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.829907180 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 41178124 ps |
| CPU time | 1.89 seconds |
| Started | Oct 15 09:36:26 AM UTC 24 |
| Finished | Oct 15 09:36:29 AM UTC 24 |
| Peak memory | 240100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829907180 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.829907180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1496153695 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 72259663 ps |
| CPU time | 2.16 seconds |
| Started | Oct 15 09:36:26 AM UTC 24 |
| Finished | Oct 15 09:36:29 AM UTC 24 |
| Peak memory | 239652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496153695 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.1496153695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2606831755 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 104559955 ps |
| CPU time | 1.68 seconds |
| Started | Oct 15 09:36:26 AM UTC 24 |
| Finished | Oct 15 09:36:29 AM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606831755 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.2606831755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.4201960459 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 198154979 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 09:36:30 AM UTC 24 |
| Finished | Oct 15 09:36:35 AM UTC 24 |
| Peak memory | 250640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201960459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.4201960459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.401854841 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 2632296309 ps |
| CPU time | 7.53 seconds |
| Started | Oct 15 09:36:25 AM UTC 24 |
| Finished | Oct 15 09:36:34 AM UTC 24 |
| Peak memory | 257052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401854841 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.401854841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2937031033 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 126602600 ps |
| CPU time | 2.13 seconds |
| Started | Oct 15 09:37:23 AM UTC 24 |
| Finished | Oct 15 09:37:26 AM UTC 24 |
| Peak memory | 239264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937031033 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2937031033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2530029158 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 596063930 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 09:37:23 AM UTC 24 |
| Finished | Oct 15 09:37:27 AM UTC 24 |
| Peak memory | 240076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530029158 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2530029158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1545368796 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 70432709 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 09:37:24 AM UTC 24 |
| Finished | Oct 15 09:37:27 AM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545368796 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1545368796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.1947304304 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 146176168 ps |
| CPU time | 2.11 seconds |
| Started | Oct 15 09:37:24 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947304304 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1947304304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2041516111 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 71619363 ps |
| CPU time | 2.18 seconds |
| Started | Oct 15 09:37:24 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041516111 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2041516111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1817654017 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 42056203 ps |
| CPU time | 2.1 seconds |
| Started | Oct 15 09:37:25 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817654017 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1817654017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.3781081444 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 146841576 ps |
| CPU time | 2.14 seconds |
| Started | Oct 15 09:37:26 AM UTC 24 |
| Finished | Oct 15 09:37:29 AM UTC 24 |
| Peak memory | 240200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781081444 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3781081444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.2995343806 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 49557589 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 09:37:26 AM UTC 24 |
| Finished | Oct 15 09:37:29 AM UTC 24 |
| Peak memory | 239972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995343806 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2995343806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.308733575 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 136360195 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 09:37:26 AM UTC 24 |
| Finished | Oct 15 09:37:28 AM UTC 24 |
| Peak memory | 238836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308733575 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.308733575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1748607765 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 526732440 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 09:37:27 AM UTC 24 |
| Finished | Oct 15 09:37:30 AM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748607765 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1748607765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1081321020 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 126419104 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 09:36:35 AM UTC 24 |
| Finished | Oct 15 09:36:41 AM UTC 24 |
| Peak memory | 250708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081321020 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.1081321020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4126177702 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 608059601 ps |
| CPU time | 7 seconds |
| Started | Oct 15 09:36:34 AM UTC 24 |
| Finished | Oct 15 09:36:42 AM UTC 24 |
| Peak memory | 250692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126177702 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.4126177702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3484819296 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 101716946 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 09:36:32 AM UTC 24 |
| Finished | Oct 15 09:36:36 AM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484819296 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.3484819296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2073865248 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 90655099 ps |
| CPU time | 3.27 seconds |
| Started | Oct 15 09:36:36 AM UTC 24 |
| Finished | Oct 15 09:36:41 AM UTC 24 |
| Peak memory | 254852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2073865248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.2073865248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2162473677 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 143378851 ps |
| CPU time | 2.73 seconds |
| Started | Oct 15 09:36:32 AM UTC 24 |
| Finished | Oct 15 09:36:36 AM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162473677 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2162473677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.313566244 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 591894645 ps |
| CPU time | 3 seconds |
| Started | Oct 15 09:36:31 AM UTC 24 |
| Finished | Oct 15 09:36:35 AM UTC 24 |
| Peak memory | 239816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313566244 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.313566244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2882912361 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 38229385 ps |
| CPU time | 2.2 seconds |
| Started | Oct 15 09:36:32 AM UTC 24 |
| Finished | Oct 15 09:36:35 AM UTC 24 |
| Peak memory | 240116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882912361 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.2882912361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2652075337 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 38601942 ps |
| CPU time | 2.21 seconds |
| Started | Oct 15 09:36:31 AM UTC 24 |
| Finished | Oct 15 09:36:34 AM UTC 24 |
| Peak memory | 239956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652075337 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.2652075337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3498924481 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1282592882 ps |
| CPU time | 5.06 seconds |
| Started | Oct 15 09:36:35 AM UTC 24 |
| Finished | Oct 15 09:36:41 AM UTC 24 |
| Peak memory | 250600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498924481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.3498924481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.695483181 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 138029517 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 09:36:30 AM UTC 24 |
| Finished | Oct 15 09:36:38 AM UTC 24 |
| Peak memory | 256960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695483181 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.695483181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4048062283 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3963223035 ps |
| CPU time | 25.18 seconds |
| Started | Oct 15 09:36:30 AM UTC 24 |
| Finished | Oct 15 09:36:56 AM UTC 24 |
| Peak memory | 250956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048062283 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.4048062283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.1033920690 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 47590357 ps |
| CPU time | 1.77 seconds |
| Started | Oct 15 09:37:27 AM UTC 24 |
| Finished | Oct 15 09:37:30 AM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033920690 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1033920690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.109250536 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 155538603 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 09:37:27 AM UTC 24 |
| Finished | Oct 15 09:37:30 AM UTC 24 |
| Peak memory | 238512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109250536 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.109250536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2793981146 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 134684024 ps |
| CPU time | 1.73 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:31 AM UTC 24 |
| Peak memory | 239132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793981146 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2793981146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.2404276969 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 117553116 ps |
| CPU time | 2.58 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:32 AM UTC 24 |
| Peak memory | 240296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404276969 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2404276969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.1519927373 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 128171993 ps |
| CPU time | 1.73 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:31 AM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519927373 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.1519927373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.2752156201 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 122370406 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:31 AM UTC 24 |
| Peak memory | 240456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752156201 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2752156201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.3400904862 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 604755291 ps |
| CPU time | 2.19 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:31 AM UTC 24 |
| Peak memory | 240584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400904862 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3400904862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3497748088 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 68585768 ps |
| CPU time | 1.86 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:31 AM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497748088 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3497748088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2195823284 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 41615820 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 09:37:28 AM UTC 24 |
| Finished | Oct 15 09:37:31 AM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195823284 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2195823284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2281652940 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 40608140 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 09:37:29 AM UTC 24 |
| Finished | Oct 15 09:37:32 AM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281652940 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2281652940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1939421868 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 163978889 ps |
| CPU time | 6.52 seconds |
| Started | Oct 15 09:36:42 AM UTC 24 |
| Finished | Oct 15 09:36:49 AM UTC 24 |
| Peak memory | 250644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939421868 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.1939421868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2066516651 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 4131753869 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 09:36:41 AM UTC 24 |
| Finished | Oct 15 09:36:51 AM UTC 24 |
| Peak memory | 250620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066516651 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.2066516651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1081617973 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1623856220 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 09:36:40 AM UTC 24 |
| Finished | Oct 15 09:36:45 AM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081617973 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1081617973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3825610018 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 86240348 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 09:36:42 AM UTC 24 |
| Finished | Oct 15 09:36:46 AM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3825610018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3825610018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2337213745 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 50562196 ps |
| CPU time | 2.53 seconds |
| Started | Oct 15 09:36:40 AM UTC 24 |
| Finished | Oct 15 09:36:43 AM UTC 24 |
| Peak memory | 256628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337213745 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2337213745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2652606927 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 43203435 ps |
| CPU time | 2.32 seconds |
| Started | Oct 15 09:36:36 AM UTC 24 |
| Finished | Oct 15 09:36:40 AM UTC 24 |
| Peak memory | 239868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652606927 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2652606927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3157956024 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 41759712 ps |
| CPU time | 2.2 seconds |
| Started | Oct 15 09:36:37 AM UTC 24 |
| Finished | Oct 15 09:36:41 AM UTC 24 |
| Peak memory | 240244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157956024 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.3157956024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2106267419 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 72073638 ps |
| CPU time | 2.19 seconds |
| Started | Oct 15 09:36:37 AM UTC 24 |
| Finished | Oct 15 09:36:41 AM UTC 24 |
| Peak memory | 240524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106267419 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.2106267419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.833954433 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 267547338 ps |
| CPU time | 3.96 seconds |
| Started | Oct 15 09:36:42 AM UTC 24 |
| Finished | Oct 15 09:36:47 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833954433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.833954433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3215071135 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 288370513 ps |
| CPU time | 7.18 seconds |
| Started | Oct 15 09:36:36 AM UTC 24 |
| Finished | Oct 15 09:36:44 AM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215071135 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3215071135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1419300871 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 4979661111 ps |
| CPU time | 29.77 seconds |
| Started | Oct 15 09:36:36 AM UTC 24 |
| Finished | Oct 15 09:37:07 AM UTC 24 |
| Peak memory | 250892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419300871 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1419300871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.3599151503 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 93116820 ps |
| CPU time | 1.71 seconds |
| Started | Oct 15 09:37:29 AM UTC 24 |
| Finished | Oct 15 09:37:32 AM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599151503 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3599151503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.2715270709 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 150343699 ps |
| CPU time | 2.27 seconds |
| Started | Oct 15 09:37:29 AM UTC 24 |
| Finished | Oct 15 09:37:33 AM UTC 24 |
| Peak memory | 239860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715270709 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2715270709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.1421712709 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 559543663 ps |
| CPU time | 2.41 seconds |
| Started | Oct 15 09:37:29 AM UTC 24 |
| Finished | Oct 15 09:37:33 AM UTC 24 |
| Peak memory | 240524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421712709 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1421712709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1415568497 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 41434086 ps |
| CPU time | 1.93 seconds |
| Started | Oct 15 09:37:29 AM UTC 24 |
| Finished | Oct 15 09:37:33 AM UTC 24 |
| Peak memory | 240480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415568497 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1415568497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.1873627820 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 72666995 ps |
| CPU time | 1.49 seconds |
| Started | Oct 15 09:37:30 AM UTC 24 |
| Finished | Oct 15 09:37:32 AM UTC 24 |
| Peak memory | 238780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873627820 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.1873627820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2194448262 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 42487160 ps |
| CPU time | 1.49 seconds |
| Started | Oct 15 09:37:31 AM UTC 24 |
| Finished | Oct 15 09:37:33 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194448262 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2194448262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.2916456064 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 167240915 ps |
| CPU time | 1.56 seconds |
| Started | Oct 15 09:37:31 AM UTC 24 |
| Finished | Oct 15 09:37:33 AM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916456064 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2916456064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1300415496 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 134023235 ps |
| CPU time | 1.66 seconds |
| Started | Oct 15 09:37:31 AM UTC 24 |
| Finished | Oct 15 09:37:34 AM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300415496 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1300415496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.308230671 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 37322270 ps |
| CPU time | 1.51 seconds |
| Started | Oct 15 09:37:31 AM UTC 24 |
| Finished | Oct 15 09:37:33 AM UTC 24 |
| Peak memory | 240456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308230671 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.308230671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.2757417883 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 544517368 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 09:37:32 AM UTC 24 |
| Finished | Oct 15 09:37:35 AM UTC 24 |
| Peak memory | 239404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757417883 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2757417883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3311507554 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 100935734 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 09:36:44 AM UTC 24 |
| Finished | Oct 15 09:36:48 AM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3311507554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.3311507554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3203411382 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 42182644 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 09:36:43 AM UTC 24 |
| Finished | Oct 15 09:36:46 AM UTC 24 |
| Peak memory | 250564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203411382 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3203411382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.1190197467 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 69628453 ps |
| CPU time | 2.13 seconds |
| Started | Oct 15 09:36:42 AM UTC 24 |
| Finished | Oct 15 09:36:45 AM UTC 24 |
| Peak memory | 240452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190197467 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1190197467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.733917181 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 96183841 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 09:36:43 AM UTC 24 |
| Finished | Oct 15 09:36:47 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733917181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.733917181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3060150432 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 99382761 ps |
| CPU time | 5.66 seconds |
| Started | Oct 15 09:36:42 AM UTC 24 |
| Finished | Oct 15 09:36:49 AM UTC 24 |
| Peak memory | 256984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060150432 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3060150432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2144430404 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 131194641 ps |
| CPU time | 2.98 seconds |
| Started | Oct 15 09:36:48 AM UTC 24 |
| Finished | Oct 15 09:36:52 AM UTC 24 |
| Peak memory | 256896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2144430404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.2144430404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1546042317 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 100076499 ps |
| CPU time | 1.88 seconds |
| Started | Oct 15 09:36:46 AM UTC 24 |
| Finished | Oct 15 09:36:49 AM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546042317 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1546042317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3681955507 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 120822391 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 09:36:47 AM UTC 24 |
| Finished | Oct 15 09:36:52 AM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681955507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3681955507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.595004095 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 67627851 ps |
| CPU time | 5.1 seconds |
| Started | Oct 15 09:36:45 AM UTC 24 |
| Finished | Oct 15 09:36:51 AM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595004095 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.595004095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.445197714 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 9661259277 ps |
| CPU time | 24.68 seconds |
| Started | Oct 15 09:36:45 AM UTC 24 |
| Finished | Oct 15 09:37:11 AM UTC 24 |
| Peak memory | 254920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445197714 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.445197714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.941903343 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 158061811 ps |
| CPU time | 3.51 seconds |
| Started | Oct 15 09:36:50 AM UTC 24 |
| Finished | Oct 15 09:36:54 AM UTC 24 |
| Peak memory | 254876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=941903343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr _mem_rw_with_rand_reset.941903343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3443642866 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 86512204 ps |
| CPU time | 2.52 seconds |
| Started | Oct 15 09:36:50 AM UTC 24 |
| Finished | Oct 15 09:36:53 AM UTC 24 |
| Peak memory | 256776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443642866 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3443642866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1879301144 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 138304023 ps |
| CPU time | 1.96 seconds |
| Started | Oct 15 09:36:49 AM UTC 24 |
| Finished | Oct 15 09:36:52 AM UTC 24 |
| Peak memory | 240456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879301144 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1879301144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3470639497 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 112843668 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 09:36:50 AM UTC 24 |
| Finished | Oct 15 09:36:55 AM UTC 24 |
| Peak memory | 250712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470639497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.3470639497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.538704999 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 183247869 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 09:36:48 AM UTC 24 |
| Finished | Oct 15 09:36:58 AM UTC 24 |
| Peak memory | 256872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538704999 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.538704999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3234114586 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 666895324 ps |
| CPU time | 10.69 seconds |
| Started | Oct 15 09:36:49 AM UTC 24 |
| Finished | Oct 15 09:37:00 AM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234114586 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3234114586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.760308853 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 114731864 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 09:36:53 AM UTC 24 |
| Finished | Oct 15 09:36:59 AM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=760308853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr _mem_rw_with_rand_reset.760308853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1867210667 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 139011132 ps |
| CPU time | 2.78 seconds |
| Started | Oct 15 09:36:52 AM UTC 24 |
| Finished | Oct 15 09:36:56 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867210667 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1867210667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1296058861 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 542127058 ps |
| CPU time | 2.74 seconds |
| Started | Oct 15 09:36:52 AM UTC 24 |
| Finished | Oct 15 09:36:56 AM UTC 24 |
| Peak memory | 240316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296058861 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1296058861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3429950280 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 102205698 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 09:36:52 AM UTC 24 |
| Finished | Oct 15 09:36:56 AM UTC 24 |
| Peak memory | 250908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429950280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.3429950280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.999633254 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 3120669550 ps |
| CPU time | 9.43 seconds |
| Started | Oct 15 09:36:51 AM UTC 24 |
| Finished | Oct 15 09:37:01 AM UTC 24 |
| Peak memory | 257052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999633254 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.999633254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3577903046 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1448512093 ps |
| CPU time | 12.21 seconds |
| Started | Oct 15 09:36:52 AM UTC 24 |
| Finished | Oct 15 09:37:05 AM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577903046 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3577903046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.182537332 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 206672737 ps |
| CPU time | 4.19 seconds |
| Started | Oct 15 09:36:56 AM UTC 24 |
| Finished | Oct 15 09:37:02 AM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=182537332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr _mem_rw_with_rand_reset.182537332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2856020431 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 59393630 ps |
| CPU time | 2.31 seconds |
| Started | Oct 15 09:36:56 AM UTC 24 |
| Finished | Oct 15 09:37:00 AM UTC 24 |
| Peak memory | 250776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856020431 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2856020431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.2756932757 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 39498448 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 09:36:56 AM UTC 24 |
| Finished | Oct 15 09:37:00 AM UTC 24 |
| Peak memory | 240584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756932757 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2756932757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.789898679 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 47016594 ps |
| CPU time | 3 seconds |
| Started | Oct 15 09:36:56 AM UTC 24 |
| Finished | Oct 15 09:37:01 AM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789898679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.789898679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3776033892 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 1169990911 ps |
| CPU time | 4.99 seconds |
| Started | Oct 15 09:36:54 AM UTC 24 |
| Finished | Oct 15 09:37:00 AM UTC 24 |
| Peak memory | 257092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776033892 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3776033892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2026691341 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 703954970 ps |
| CPU time | 12.78 seconds |
| Started | Oct 15 09:36:55 AM UTC 24 |
| Finished | Oct 15 09:37:10 AM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026691341 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.2026691341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.2244442939 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 188791575 ps |
| CPU time | 3.09 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:37:39 AM UTC 24 |
| Peak memory | 252560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244442939 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2244442939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.3585656407 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 9359731352 ps |
| CPU time | 27.54 seconds |
| Started | Oct 15 09:37:33 AM UTC 24 |
| Finished | Oct 15 09:38:02 AM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585656407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3585656407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.1834476438 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 951018441 ps |
| CPU time | 22.87 seconds |
| Started | Oct 15 09:37:34 AM UTC 24 |
| Finished | Oct 15 09:37:58 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834476438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1834476438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.2831012073 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5980076882 ps |
| CPU time | 12.4 seconds |
| Started | Oct 15 09:37:32 AM UTC 24 |
| Finished | Oct 15 09:37:46 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831012073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2831012073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.3483847521 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 449128330 ps |
| CPU time | 7.41 seconds |
| Started | Oct 15 09:37:34 AM UTC 24 |
| Finished | Oct 15 09:37:42 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483847521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3483847521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.1639868471 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 160468713 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 09:37:33 AM UTC 24 |
| Finished | Oct 15 09:37:39 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639868471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1639868471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.2003365393 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 646325685 ps |
| CPU time | 16.1 seconds |
| Started | Oct 15 09:37:32 AM UTC 24 |
| Finished | Oct 15 09:37:50 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003365393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2003365393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.3937615645 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 264199165 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 09:37:32 AM UTC 24 |
| Finished | Oct 15 09:37:40 AM UTC 24 |
| Peak memory | 252468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937615645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3937615645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.468205333 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 88061190534 ps |
| CPU time | 324.4 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:43:04 AM UTC 24 |
| Peak memory | 291796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468205333 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.468205333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.46426939 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 125139647 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 09:37:46 AM UTC 24 |
| Finished | Oct 15 09:37:50 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46426939 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.46426939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.4143773534 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1208909092 ps |
| CPU time | 15.65 seconds |
| Started | Oct 15 09:37:36 AM UTC 24 |
| Finished | Oct 15 09:37:53 AM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143773534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.4143773534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.427954292 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 278733594 ps |
| CPU time | 15.05 seconds |
| Started | Oct 15 09:37:40 AM UTC 24 |
| Finished | Oct 15 09:37:56 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427954292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.427954292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.1256863485 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 998593618 ps |
| CPU time | 25.24 seconds |
| Started | Oct 15 09:37:40 AM UTC 24 |
| Finished | Oct 15 09:38:07 AM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256863485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1256863485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.1104327981 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 689889407 ps |
| CPU time | 22.31 seconds |
| Started | Oct 15 09:37:40 AM UTC 24 |
| Finished | Oct 15 09:38:03 AM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104327981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1104327981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.1831721849 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5921959286 ps |
| CPU time | 21.13 seconds |
| Started | Oct 15 09:37:40 AM UTC 24 |
| Finished | Oct 15 09:38:02 AM UTC 24 |
| Peak memory | 254640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831721849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1831721849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.2134705988 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 257132147 ps |
| CPU time | 8.72 seconds |
| Started | Oct 15 09:37:36 AM UTC 24 |
| Finished | Oct 15 09:37:46 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134705988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2134705988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.3337820980 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 656694753 ps |
| CPU time | 8.25 seconds |
| Started | Oct 15 09:37:41 AM UTC 24 |
| Finished | Oct 15 09:37:50 AM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337820980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3337820980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3853450108 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 154580608647 ps |
| CPU time | 286.32 seconds |
| Started | Oct 15 09:37:46 AM UTC 24 |
| Finished | Oct 15 09:42:37 AM UTC 24 |
| Peak memory | 297156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853450108 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3853450108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.1079762124 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1203450473 ps |
| CPU time | 11.43 seconds |
| Started | Oct 15 09:37:35 AM UTC 24 |
| Finished | Oct 15 09:37:48 AM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079762124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1079762124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.1191478345 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 756408119 ps |
| CPU time | 8.8 seconds |
| Started | Oct 15 09:37:41 AM UTC 24 |
| Finished | Oct 15 09:37:51 AM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191478345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1191478345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.548374201 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 661572178 ps |
| CPU time | 2.97 seconds |
| Started | Oct 15 09:39:03 AM UTC 24 |
| Finished | Oct 15 09:39:07 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548374201 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.548374201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.1058894506 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1299062930 ps |
| CPU time | 15.77 seconds |
| Started | Oct 15 09:39:00 AM UTC 24 |
| Finished | Oct 15 09:39:17 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058894506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.1058894506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.2698511448 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 199835361 ps |
| CPU time | 11.63 seconds |
| Started | Oct 15 09:38:59 AM UTC 24 |
| Finished | Oct 15 09:39:11 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698511448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2698511448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.2359771381 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3402027193 ps |
| CPU time | 41.84 seconds |
| Started | Oct 15 09:39:00 AM UTC 24 |
| Finished | Oct 15 09:39:44 AM UTC 24 |
| Peak memory | 269564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359771381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2359771381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.2693885124 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1339281111 ps |
| CPU time | 17.04 seconds |
| Started | Oct 15 09:39:00 AM UTC 24 |
| Finished | Oct 15 09:39:19 AM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693885124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.2693885124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.831722264 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 368480924 ps |
| CPU time | 8.56 seconds |
| Started | Oct 15 09:38:56 AM UTC 24 |
| Finished | Oct 15 09:39:05 AM UTC 24 |
| Peak memory | 252608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831722264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.831722264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.782438027 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1416261774 ps |
| CPU time | 19.7 seconds |
| Started | Oct 15 09:38:56 AM UTC 24 |
| Finished | Oct 15 09:39:17 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782438027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.782438027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.2291957821 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1857853280 ps |
| CPU time | 10.35 seconds |
| Started | Oct 15 09:39:00 AM UTC 24 |
| Finished | Oct 15 09:39:12 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291957821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2291957821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.2138804436 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 155943286 ps |
| CPU time | 4.46 seconds |
| Started | Oct 15 09:38:52 AM UTC 24 |
| Finished | Oct 15 09:38:58 AM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138804436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2138804436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.884502348 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2281263626 ps |
| CPU time | 35.36 seconds |
| Started | Oct 15 09:39:01 AM UTC 24 |
| Finished | Oct 15 09:39:37 AM UTC 24 |
| Peak memory | 269416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=884502348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.884502348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.1334235201 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 388799751 ps |
| CPU time | 8.38 seconds |
| Started | Oct 15 09:39:01 AM UTC 24 |
| Finished | Oct 15 09:39:10 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334235201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1334235201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.280404712 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 176288099 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:46:35 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280404712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.280404712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1996889115 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1444816385 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 09:46:29 AM UTC 24 |
| Finished | Oct 15 09:46:35 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996889115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1996889115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.1748368194 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 110796592 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 09:46:29 AM UTC 24 |
| Finished | Oct 15 09:46:33 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748368194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1748368194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.1931968685 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 468331902 ps |
| CPU time | 5.71 seconds |
| Started | Oct 15 09:46:31 AM UTC 24 |
| Finished | Oct 15 09:46:39 AM UTC 24 |
| Peak memory | 252996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931968685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1931968685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.176882912 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 138113226 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 09:46:31 AM UTC 24 |
| Finished | Oct 15 09:46:37 AM UTC 24 |
| Peak memory | 252536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176882912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.176882912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.4048512528 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 146511702 ps |
| CPU time | 4.66 seconds |
| Started | Oct 15 09:46:31 AM UTC 24 |
| Finished | Oct 15 09:46:38 AM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048512528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.4048512528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.4168075075 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 1741900716 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 09:46:37 AM UTC 24 |
| Finished | Oct 15 09:46:42 AM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168075075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.4168075075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.121597252 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 123949713 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 09:46:37 AM UTC 24 |
| Finished | Oct 15 09:46:42 AM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121597252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.121597252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.3705679101 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 137103961 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 09:46:37 AM UTC 24 |
| Finished | Oct 15 09:46:44 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705679101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3705679101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.4137684293 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 299848421 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 09:46:37 AM UTC 24 |
| Finished | Oct 15 09:46:47 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137684293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.4137684293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.4175685936 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1738222283 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 09:46:37 AM UTC 24 |
| Finished | Oct 15 09:46:44 AM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175685936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.4175685936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.1030270832 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 659738609 ps |
| CPU time | 8.97 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:48 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030270832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1030270832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.2280377782 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 201127370 ps |
| CPU time | 5.44 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:44 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280377782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2280377782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.1830552010 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 780058988 ps |
| CPU time | 12.98 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:52 AM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830552010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1830552010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.4180366547 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 304820204 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:43 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180366547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.4180366547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.856940121 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 904517357 ps |
| CPU time | 20.99 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:47:00 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856940121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.856940121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.2311606790 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 159188776 ps |
| CPU time | 4.45 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:43 AM UTC 24 |
| Peak memory | 252984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311606790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2311606790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.3474444588 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 205471123 ps |
| CPU time | 4.52 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:43 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474444588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3474444588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.1432291804 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 255238124 ps |
| CPU time | 6.1 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:45 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432291804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1432291804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2150615598 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 182907590 ps |
| CPU time | 5.55 seconds |
| Started | Oct 15 09:46:38 AM UTC 24 |
| Finished | Oct 15 09:46:45 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150615598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2150615598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.658513384 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 102876734 ps |
| CPU time | 2.51 seconds |
| Started | Oct 15 09:39:13 AM UTC 24 |
| Finished | Oct 15 09:39:17 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658513384 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.658513384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.4146948561 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 379026880 ps |
| CPU time | 20.87 seconds |
| Started | Oct 15 09:39:07 AM UTC 24 |
| Finished | Oct 15 09:39:30 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146948561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.4146948561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.420343807 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 168469311 ps |
| CPU time | 5.22 seconds |
| Started | Oct 15 09:39:07 AM UTC 24 |
| Finished | Oct 15 09:39:14 AM UTC 24 |
| Peak memory | 253084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420343807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.420343807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.1760684688 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2010186527 ps |
| CPU time | 10.71 seconds |
| Started | Oct 15 09:39:08 AM UTC 24 |
| Finished | Oct 15 09:39:19 AM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760684688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1760684688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.401408739 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 224422146 ps |
| CPU time | 4.05 seconds |
| Started | Oct 15 09:39:07 AM UTC 24 |
| Finished | Oct 15 09:39:12 AM UTC 24 |
| Peak memory | 252868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401408739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.401408739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.2702096847 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 220978671 ps |
| CPU time | 4.89 seconds |
| Started | Oct 15 09:39:09 AM UTC 24 |
| Finished | Oct 15 09:39:15 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702096847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2702096847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.473616716 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 7319802811 ps |
| CPU time | 11.98 seconds |
| Started | Oct 15 09:39:05 AM UTC 24 |
| Finished | Oct 15 09:39:18 AM UTC 24 |
| Peak memory | 253108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473616716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.473616716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.1997506933 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 9237079969 ps |
| CPU time | 25.03 seconds |
| Started | Oct 15 09:39:10 AM UTC 24 |
| Finished | Oct 15 09:39:36 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997506933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1997506933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.2612928249 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 126642782 ps |
| CPU time | 4.67 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:48 AM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612928249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2612928249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.2914018397 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 5730327263 ps |
| CPU time | 22.78 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 253012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914018397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.2914018397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.3460733910 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 123026878 ps |
| CPU time | 4.34 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:47 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460733910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3460733910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.2352040528 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 221611140 ps |
| CPU time | 6.72 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:49 AM UTC 24 |
| Peak memory | 252928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352040528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2352040528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.754604245 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 92019778 ps |
| CPU time | 2.98 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:47 AM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754604245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.754604245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.4110270811 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 458318772 ps |
| CPU time | 11.24 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:55 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110270811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.4110270811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.3640588253 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 142912392 ps |
| CPU time | 5.26 seconds |
| Started | Oct 15 09:46:42 AM UTC 24 |
| Finished | Oct 15 09:46:49 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640588253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3640588253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.1560740581 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 425467657 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 09:46:44 AM UTC 24 |
| Finished | Oct 15 09:46:49 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560740581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1560740581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.461091002 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 13948334760 ps |
| CPU time | 28.93 seconds |
| Started | Oct 15 09:46:44 AM UTC 24 |
| Finished | Oct 15 09:47:15 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461091002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.461091002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.1362878677 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 113324572 ps |
| CPU time | 4.11 seconds |
| Started | Oct 15 09:46:44 AM UTC 24 |
| Finished | Oct 15 09:46:50 AM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362878677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1362878677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.3363684137 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 117072488 ps |
| CPU time | 4.65 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:54 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363684137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3363684137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.806312831 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 313052941 ps |
| CPU time | 4.76 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:54 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806312831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.806312831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.126130547 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2297550206 ps |
| CPU time | 7.46 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:57 AM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126130547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.126130547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.464004280 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 527895752 ps |
| CPU time | 3.82 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:54 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464004280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.464004280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.3027969659 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2055601999 ps |
| CPU time | 7.88 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:58 AM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027969659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3027969659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.1615563571 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3911148675 ps |
| CPU time | 18.22 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:47:08 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615563571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.1615563571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.3216421757 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 221542472 ps |
| CPU time | 3.26 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:53 AM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216421757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3216421757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.468135120 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 870584209 ps |
| CPU time | 7.27 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:57 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468135120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.468135120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.1923825702 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 897092684 ps |
| CPU time | 2.63 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:22 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923825702 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1923825702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.3570346898 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1678804762 ps |
| CPU time | 23.36 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:42 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570346898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3570346898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.3391785044 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 410967117 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 09:39:13 AM UTC 24 |
| Finished | Oct 15 09:39:19 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391785044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3391785044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.3466606875 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 843915207 ps |
| CPU time | 21.52 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:41 AM UTC 24 |
| Peak memory | 253012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466606875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3466606875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.90188520 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 355287922 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 09:39:14 AM UTC 24 |
| Finished | Oct 15 09:39:19 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90188520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.90188520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2740811703 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 305065459 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 09:39:13 AM UTC 24 |
| Finished | Oct 15 09:39:21 AM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740811703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2740811703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.3139016180 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 189375686 ps |
| CPU time | 5.43 seconds |
| Started | Oct 15 09:39:13 AM UTC 24 |
| Finished | Oct 15 09:39:20 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139016180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3139016180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.2568895186 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 613125615 ps |
| CPU time | 19.75 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:39:39 AM UTC 24 |
| Peak memory | 259400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2568895186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.otp_ctrl_stress_all_with_rand_reset.2568895186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.3359458737 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 11102811331 ps |
| CPU time | 72.42 seconds |
| Started | Oct 15 09:39:18 AM UTC 24 |
| Finished | Oct 15 09:40:32 AM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359458737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.3359458737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.165226978 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 126171278 ps |
| CPU time | 4.93 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:55 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165226978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.165226978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.3954310202 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2446940785 ps |
| CPU time | 17.37 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:47:08 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954310202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3954310202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.529327114 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 370582222 ps |
| CPU time | 4.93 seconds |
| Started | Oct 15 09:46:48 AM UTC 24 |
| Finished | Oct 15 09:46:55 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529327114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.529327114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.2438580564 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 11012961183 ps |
| CPU time | 28.23 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:47:21 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438580564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2438580564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.2773995770 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 10751153042 ps |
| CPU time | 21.46 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 252916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773995770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2773995770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.3149542595 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 128513414 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:46:57 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149542595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3149542595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.3554180160 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 736496165 ps |
| CPU time | 14.78 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:47:08 AM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554180160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3554180160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.948673507 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 204288223 ps |
| CPU time | 5.93 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:46:59 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948673507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.948673507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.1776954416 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 1069768030 ps |
| CPU time | 20.83 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776954416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1776954416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.2351555832 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 241754694 ps |
| CPU time | 5.29 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:46:58 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351555832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2351555832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.2860557705 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 136343873 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 09:46:51 AM UTC 24 |
| Finished | Oct 15 09:46:56 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860557705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2860557705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.1249875832 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 244149828 ps |
| CPU time | 4.07 seconds |
| Started | Oct 15 09:46:53 AM UTC 24 |
| Finished | Oct 15 09:46:59 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249875832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1249875832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.1412162378 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2075798385 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 09:46:53 AM UTC 24 |
| Finished | Oct 15 09:47:03 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412162378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1412162378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.2644155107 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 10123505381 ps |
| CPU time | 29.91 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:33 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644155107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2644155107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.2595809889 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 404400593 ps |
| CPU time | 3.88 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595809889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2595809889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.4260468480 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 257169040 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:07 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260468480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.4260468480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.3104661183 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 126173573 ps |
| CPU time | 3.88 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104661183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3104661183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.1247064525 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 680041737 ps |
| CPU time | 18.03 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:21 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247064525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1247064525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.3482074661 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 406642592 ps |
| CPU time | 4.04 seconds |
| Started | Oct 15 09:39:24 AM UTC 24 |
| Finished | Oct 15 09:39:29 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482074661 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3482074661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.4040248327 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1599770535 ps |
| CPU time | 16.12 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:38 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040248327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.4040248327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3626376469 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 917950433 ps |
| CPU time | 14.44 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:36 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626376469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3626376469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.2940150460 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 205367648 ps |
| CPU time | 8.22 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:30 AM UTC 24 |
| Peak memory | 253200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940150460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2940150460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.3821919462 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 262835954 ps |
| CPU time | 6.7 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:28 AM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821919462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3821919462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.1944901884 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4298732042 ps |
| CPU time | 43.8 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:40:06 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944901884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1944901884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.193456219 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1004466241 ps |
| CPU time | 22.38 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:44 AM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193456219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.193456219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.3056761537 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1814179743 ps |
| CPU time | 6.28 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:28 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056761537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3056761537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.1201934174 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 462025907 ps |
| CPU time | 14.11 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:36 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201934174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1201934174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.1100955726 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 679510713 ps |
| CPU time | 6.31 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:28 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100955726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1100955726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.4171684140 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 319833861 ps |
| CPU time | 10.81 seconds |
| Started | Oct 15 09:39:20 AM UTC 24 |
| Finished | Oct 15 09:39:32 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171684140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.4171684140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.1587397629 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 41283066071 ps |
| CPU time | 228.86 seconds |
| Started | Oct 15 09:39:24 AM UTC 24 |
| Finished | Oct 15 09:43:17 AM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587397629 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.1587397629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.2654619603 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1582388357 ps |
| CPU time | 30.08 seconds |
| Started | Oct 15 09:39:21 AM UTC 24 |
| Finished | Oct 15 09:39:52 AM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654619603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2654619603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.1609741416 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2759186158 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:07 AM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609741416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1609741416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.737415481 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 862374309 ps |
| CPU time | 13.09 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:16 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737415481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.737415481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1931201108 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 143092618 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931201108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1931201108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.394354521 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 625127062 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:09 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394354521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.394354521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.1376238324 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 238401209 ps |
| CPU time | 3.59 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376238324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1376238324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.1872621945 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 617313165 ps |
| CPU time | 16.55 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:19 AM UTC 24 |
| Peak memory | 252608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872621945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1872621945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.3110870974 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 489510031 ps |
| CPU time | 5.75 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:08 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110870974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3110870974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.3517960971 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 342286940 ps |
| CPU time | 9.71 seconds |
| Started | Oct 15 09:47:01 AM UTC 24 |
| Finished | Oct 15 09:47:12 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517960971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3517960971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.1644693912 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 452965094 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644693912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1644693912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.1541168902 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 1222857654 ps |
| CPU time | 13.41 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:16 AM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541168902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1541168902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.896045971 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 218496179 ps |
| CPU time | 4.07 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:07 AM UTC 24 |
| Peak memory | 252600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896045971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.896045971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.2386051204 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 428875006 ps |
| CPU time | 4.95 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:08 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386051204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2386051204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.1549694804 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 260984402 ps |
| CPU time | 3.08 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549694804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1549694804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.1148852787 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 299059832 ps |
| CPU time | 7.7 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:11 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148852787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1148852787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.294703209 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 229795606 ps |
| CPU time | 4.54 seconds |
| Started | Oct 15 09:47:02 AM UTC 24 |
| Finished | Oct 15 09:47:07 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294703209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.294703209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.983043028 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 2387286003 ps |
| CPU time | 4.78 seconds |
| Started | Oct 15 09:47:05 AM UTC 24 |
| Finished | Oct 15 09:47:11 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983043028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.983043028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.3838442208 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2119928491 ps |
| CPU time | 7.68 seconds |
| Started | Oct 15 09:47:05 AM UTC 24 |
| Finished | Oct 15 09:47:13 AM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838442208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3838442208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.4112380836 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 550525137 ps |
| CPU time | 7.49 seconds |
| Started | Oct 15 09:47:05 AM UTC 24 |
| Finished | Oct 15 09:47:13 AM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112380836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.4112380836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.1380317468 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 288894914 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 09:47:05 AM UTC 24 |
| Finished | Oct 15 09:47:10 AM UTC 24 |
| Peak memory | 254612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380317468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1380317468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.3644024307 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 162360927 ps |
| CPU time | 3.88 seconds |
| Started | Oct 15 09:47:05 AM UTC 24 |
| Finished | Oct 15 09:47:10 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644024307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3644024307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.3975226877 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 693406011 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 09:39:32 AM UTC 24 |
| Finished | Oct 15 09:39:35 AM UTC 24 |
| Peak memory | 252852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975226877 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3975226877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.205994251 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 509889494 ps |
| CPU time | 12.12 seconds |
| Started | Oct 15 09:39:26 AM UTC 24 |
| Finished | Oct 15 09:39:40 AM UTC 24 |
| Peak memory | 256780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205994251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.205994251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.1024755107 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 712090944 ps |
| CPU time | 9.98 seconds |
| Started | Oct 15 09:39:26 AM UTC 24 |
| Finished | Oct 15 09:39:37 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024755107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1024755107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.644893018 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 881331777 ps |
| CPU time | 27.48 seconds |
| Started | Oct 15 09:39:26 AM UTC 24 |
| Finished | Oct 15 09:39:55 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644893018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.644893018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.609969565 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 423424477 ps |
| CPU time | 6.3 seconds |
| Started | Oct 15 09:39:24 AM UTC 24 |
| Finished | Oct 15 09:39:32 AM UTC 24 |
| Peak memory | 254800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609969565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.609969565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.2803201694 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2829617570 ps |
| CPU time | 13.64 seconds |
| Started | Oct 15 09:39:28 AM UTC 24 |
| Finished | Oct 15 09:39:43 AM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803201694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2803201694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.3633700537 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2246452409 ps |
| CPU time | 23.47 seconds |
| Started | Oct 15 09:39:29 AM UTC 24 |
| Finished | Oct 15 09:39:54 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633700537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3633700537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.490122072 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2506820183 ps |
| CPU time | 8.8 seconds |
| Started | Oct 15 09:39:25 AM UTC 24 |
| Finished | Oct 15 09:39:35 AM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490122072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.490122072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.2086183982 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 189775958 ps |
| CPU time | 7.06 seconds |
| Started | Oct 15 09:39:24 AM UTC 24 |
| Finished | Oct 15 09:39:33 AM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086183982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2086183982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.1580752547 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2056377455 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 09:39:29 AM UTC 24 |
| Finished | Oct 15 09:39:37 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580752547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1580752547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.753337777 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1271240998 ps |
| CPU time | 8.79 seconds |
| Started | Oct 15 09:39:24 AM UTC 24 |
| Finished | Oct 15 09:39:34 AM UTC 24 |
| Peak memory | 252928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753337777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.753337777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.1649626860 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 10527030279 ps |
| CPU time | 115.11 seconds |
| Started | Oct 15 09:39:32 AM UTC 24 |
| Finished | Oct 15 09:41:29 AM UTC 24 |
| Peak memory | 257016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649626860 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.1649626860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.3981581096 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 147962662 ps |
| CPU time | 4.68 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981581096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3981581096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.153867078 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3033483380 ps |
| CPU time | 21.07 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:31 AM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153867078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.153867078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.2846493752 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 112514794 ps |
| CPU time | 4.58 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846493752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2846493752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.3201368850 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 553927369 ps |
| CPU time | 9.6 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:19 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201368850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3201368850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3071293144 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 168668127 ps |
| CPU time | 4.68 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071293144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3071293144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.1734000758 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 460438120 ps |
| CPU time | 11.54 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:21 AM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734000758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1734000758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.927430562 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 415710256 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:13 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927430562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.927430562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.3983516070 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 1940534986 ps |
| CPU time | 6.03 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:15 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983516070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3983516070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.445067898 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 1918294161 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:15 AM UTC 24 |
| Peak memory | 252984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445067898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.445067898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.3179483817 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 422863916 ps |
| CPU time | 4.89 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179483817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3179483817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.2100524391 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 131571102 ps |
| CPU time | 4.31 seconds |
| Started | Oct 15 09:47:08 AM UTC 24 |
| Finished | Oct 15 09:47:14 AM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100524391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2100524391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.3433462121 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2239235945 ps |
| CPU time | 6 seconds |
| Started | Oct 15 09:47:17 AM UTC 24 |
| Finished | Oct 15 09:47:25 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433462121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3433462121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.3405810410 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 171215385 ps |
| CPU time | 6.61 seconds |
| Started | Oct 15 09:47:17 AM UTC 24 |
| Finished | Oct 15 09:47:25 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405810410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3405810410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.2896453201 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 111955150 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 09:47:17 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896453201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2896453201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.2212591206 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 614451712 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 09:47:17 AM UTC 24 |
| Finished | Oct 15 09:47:24 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212591206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2212591206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.2606572059 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 162442373 ps |
| CPU time | 3.48 seconds |
| Started | Oct 15 09:47:17 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606572059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2606572059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.1302473335 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 626805778 ps |
| CPU time | 2.87 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302473335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1302473335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.1141839073 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 147708743 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141839073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1141839073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.3974732483 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 103832715 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974732483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3974732483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.1765072950 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 177184754 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 09:39:39 AM UTC 24 |
| Finished | Oct 15 09:39:42 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765072950 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1765072950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.3053253458 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 640074702 ps |
| CPU time | 15.72 seconds |
| Started | Oct 15 09:39:35 AM UTC 24 |
| Finished | Oct 15 09:39:52 AM UTC 24 |
| Peak memory | 255084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053253458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3053253458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.834524904 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 241731607 ps |
| CPU time | 18.02 seconds |
| Started | Oct 15 09:39:34 AM UTC 24 |
| Finished | Oct 15 09:39:53 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834524904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.834524904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.323524476 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 527354250 ps |
| CPU time | 11.71 seconds |
| Started | Oct 15 09:39:34 AM UTC 24 |
| Finished | Oct 15 09:39:47 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323524476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.323524476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.3110156152 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1628483783 ps |
| CPU time | 4.48 seconds |
| Started | Oct 15 09:39:34 AM UTC 24 |
| Finished | Oct 15 09:39:39 AM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110156152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3110156152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1536398282 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 741899952 ps |
| CPU time | 16.25 seconds |
| Started | Oct 15 09:39:35 AM UTC 24 |
| Finished | Oct 15 09:39:52 AM UTC 24 |
| Peak memory | 254972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536398282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1536398282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.4231355312 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 708812951 ps |
| CPU time | 16.49 seconds |
| Started | Oct 15 09:39:36 AM UTC 24 |
| Finished | Oct 15 09:39:54 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231355312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.4231355312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.2176018377 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 574949200 ps |
| CPU time | 16.38 seconds |
| Started | Oct 15 09:39:34 AM UTC 24 |
| Finished | Oct 15 09:39:51 AM UTC 24 |
| Peak memory | 252608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176018377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2176018377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.3206549015 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 752953157 ps |
| CPU time | 9.75 seconds |
| Started | Oct 15 09:39:34 AM UTC 24 |
| Finished | Oct 15 09:39:44 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206549015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3206549015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.4016708928 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 305034952 ps |
| CPU time | 9.06 seconds |
| Started | Oct 15 09:39:36 AM UTC 24 |
| Finished | Oct 15 09:39:47 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016708928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.4016708928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.948430320 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2649708533 ps |
| CPU time | 10.34 seconds |
| Started | Oct 15 09:39:32 AM UTC 24 |
| Finished | Oct 15 09:39:43 AM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948430320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.948430320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.2351338382 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 41802090457 ps |
| CPU time | 293.67 seconds |
| Started | Oct 15 09:39:39 AM UTC 24 |
| Finished | Oct 15 09:44:36 AM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351338382 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.2351338382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2595429439 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 21994648577 ps |
| CPU time | 40.9 seconds |
| Started | Oct 15 09:39:39 AM UTC 24 |
| Finished | Oct 15 09:40:21 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2595429439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.2595429439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.3128504561 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 352989095 ps |
| CPU time | 3.81 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:23 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128504561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3128504561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.2740321586 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2685809602 ps |
| CPU time | 8.82 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:28 AM UTC 24 |
| Peak memory | 253012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740321586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2740321586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.3669522406 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 186642235 ps |
| CPU time | 3.43 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669522406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3669522406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.609726118 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 908268069 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:26 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609726118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.609726118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.3099899761 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2813767097 ps |
| CPU time | 5.82 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:25 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099899761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3099899761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.3419597256 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 990832406 ps |
| CPU time | 22.1 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:41 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419597256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3419597256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.2492115466 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 161431648 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492115466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2492115466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.3951414927 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 278152962 ps |
| CPU time | 7.07 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:26 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951414927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3951414927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.1750754488 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 354270541 ps |
| CPU time | 5.65 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:25 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750754488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1750754488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.2597571297 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 313540781 ps |
| CPU time | 4.95 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:24 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597571297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2597571297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.3542150702 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 528581291 ps |
| CPU time | 6.3 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:25 AM UTC 24 |
| Peak memory | 252932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542150702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3542150702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.3499349460 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 263383492 ps |
| CPU time | 3.57 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:23 AM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499349460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3499349460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.838203123 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 15869337094 ps |
| CPU time | 44.89 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:48:05 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838203123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.838203123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.4249739391 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 677091456 ps |
| CPU time | 4.69 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:24 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249739391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.4249739391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.707370686 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 1030768670 ps |
| CPU time | 20.86 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707370686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.707370686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.545359943 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 126789759 ps |
| CPU time | 3.06 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:22 AM UTC 24 |
| Peak memory | 252732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545359943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.545359943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.1900175804 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2566239504 ps |
| CPU time | 10.19 seconds |
| Started | Oct 15 09:47:18 AM UTC 24 |
| Finished | Oct 15 09:47:30 AM UTC 24 |
| Peak memory | 252668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900175804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1900175804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.4040328218 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 545607216 ps |
| CPU time | 4.16 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 254696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040328218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.4040328218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.1970919329 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2973606463 ps |
| CPU time | 6.69 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:31 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970919329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1970919329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.3569607454 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 227990144 ps |
| CPU time | 3.85 seconds |
| Started | Oct 15 09:39:46 AM UTC 24 |
| Finished | Oct 15 09:39:51 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569607454 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3569607454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.157232943 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 8727420150 ps |
| CPU time | 24.34 seconds |
| Started | Oct 15 09:39:43 AM UTC 24 |
| Finished | Oct 15 09:40:09 AM UTC 24 |
| Peak memory | 254984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157232943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.157232943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.3157474475 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3368543233 ps |
| CPU time | 17.35 seconds |
| Started | Oct 15 09:39:41 AM UTC 24 |
| Finished | Oct 15 09:40:00 AM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157474475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3157474475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.1076581153 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 740676912 ps |
| CPU time | 18.41 seconds |
| Started | Oct 15 09:39:41 AM UTC 24 |
| Finished | Oct 15 09:40:01 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076581153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.1076581153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.4098267498 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2635908212 ps |
| CPU time | 19.14 seconds |
| Started | Oct 15 09:39:43 AM UTC 24 |
| Finished | Oct 15 09:40:04 AM UTC 24 |
| Peak memory | 256940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098267498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.4098267498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.650379143 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1139307045 ps |
| CPU time | 12.03 seconds |
| Started | Oct 15 09:39:43 AM UTC 24 |
| Finished | Oct 15 09:39:57 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650379143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.650379143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.2774990356 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 775062256 ps |
| CPU time | 6.78 seconds |
| Started | Oct 15 09:39:41 AM UTC 24 |
| Finished | Oct 15 09:39:49 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774990356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2774990356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.253187794 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 650248900 ps |
| CPU time | 12.05 seconds |
| Started | Oct 15 09:39:41 AM UTC 24 |
| Finished | Oct 15 09:39:55 AM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253187794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.253187794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.1578857219 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4084294563 ps |
| CPU time | 15.61 seconds |
| Started | Oct 15 09:39:46 AM UTC 24 |
| Finished | Oct 15 09:40:03 AM UTC 24 |
| Peak memory | 252804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578857219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1578857219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.2551026513 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3353768610 ps |
| CPU time | 8.63 seconds |
| Started | Oct 15 09:39:41 AM UTC 24 |
| Finished | Oct 15 09:39:51 AM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551026513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2551026513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.699836448 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 19543443269 ps |
| CPU time | 216.3 seconds |
| Started | Oct 15 09:39:46 AM UTC 24 |
| Finished | Oct 15 09:43:26 AM UTC 24 |
| Peak memory | 258864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699836448 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.699836448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.3851312711 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 7737809439 ps |
| CPU time | 24.65 seconds |
| Started | Oct 15 09:39:46 AM UTC 24 |
| Finished | Oct 15 09:40:12 AM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851312711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3851312711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.4283474247 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 283128419 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:28 AM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283474247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4283474247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.2422670445 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1832646185 ps |
| CPU time | 5.03 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:30 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422670445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2422670445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.912682188 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 2153367871 ps |
| CPU time | 5.03 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:30 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912682188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.912682188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.190736094 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 360633534 ps |
| CPU time | 3.81 seconds |
| Started | Oct 15 09:47:23 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190736094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.190736094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.2090441477 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 265748836 ps |
| CPU time | 5.86 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:31 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090441477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2090441477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.23414590 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 116626151 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 255052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23414590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.23414590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.175154184 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 120818228 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175154184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.175154184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.3143110087 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 654815388 ps |
| CPU time | 3.57 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143110087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3143110087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.1489926880 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 1627112009 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:30 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489926880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1489926880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.1795429923 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 240743052 ps |
| CPU time | 3.79 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795429923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1795429923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3859940042 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1310718280 ps |
| CPU time | 3.77 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859940042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3859940042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.3326132385 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 111491341 ps |
| CPU time | 3.8 seconds |
| Started | Oct 15 09:47:24 AM UTC 24 |
| Finished | Oct 15 09:47:29 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326132385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3326132385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.4262643160 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 496249991 ps |
| CPU time | 10.97 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:45 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262643160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.4262643160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.2950265608 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 214980916 ps |
| CPU time | 4.77 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950265608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2950265608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.850282308 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 280834546 ps |
| CPU time | 6.49 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:41 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850282308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.850282308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.1436575735 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 1801743265 ps |
| CPU time | 5.36 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436575735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1436575735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.2977563564 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 115522109 ps |
| CPU time | 2.83 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:37 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977563564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.2977563564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.4122250656 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 1759487782 ps |
| CPU time | 4.58 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122250656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.4122250656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.1648962996 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 377251568 ps |
| CPU time | 9.95 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:44 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648962996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1648962996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.413752537 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 161214210 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:01 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413752537 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.413752537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.2912338382 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 729739945 ps |
| CPU time | 10 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:06 AM UTC 24 |
| Peak memory | 258860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912338382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2912338382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.1774983795 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 14852176704 ps |
| CPU time | 43.18 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:39 AM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774983795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1774983795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.306502186 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2062182996 ps |
| CPU time | 5.86 seconds |
| Started | Oct 15 09:39:48 AM UTC 24 |
| Finished | Oct 15 09:39:55 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306502186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.306502186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.2182949378 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 7751562852 ps |
| CPU time | 21.91 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:18 AM UTC 24 |
| Peak memory | 257308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182949378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.2182949378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.861457500 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 802854214 ps |
| CPU time | 7.72 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:03 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861457500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.861457500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.639039557 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2838615351 ps |
| CPU time | 22.43 seconds |
| Started | Oct 15 09:39:48 AM UTC 24 |
| Finished | Oct 15 09:40:12 AM UTC 24 |
| Peak memory | 253048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639039557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.639039557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.3687262366 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1711679811 ps |
| CPU time | 4.28 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:00 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687262366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3687262366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.4013569066 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3298994838 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 09:39:48 AM UTC 24 |
| Finished | Oct 15 09:39:56 AM UTC 24 |
| Peak memory | 258848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013569066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.4013569066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.1767426201 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 30175939258 ps |
| CPU time | 168.06 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:42:49 AM UTC 24 |
| Peak memory | 275356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767426201 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.1767426201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.760854772 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4365715112 ps |
| CPU time | 47.46 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:44 AM UTC 24 |
| Peak memory | 259152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=760854772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.760854772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.2233449997 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 9168141129 ps |
| CPU time | 16.43 seconds |
| Started | Oct 15 09:39:54 AM UTC 24 |
| Finished | Oct 15 09:40:13 AM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233449997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2233449997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.3566533699 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 462603055 ps |
| CPU time | 3.82 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:38 AM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566533699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3566533699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.1635264482 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 149724623 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:38 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635264482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1635264482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.2929926574 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 1657920777 ps |
| CPU time | 5.12 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929926574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2929926574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.1303419191 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 153364437 ps |
| CPU time | 7.4 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:42 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303419191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.1303419191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.4116656537 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 110474299 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:38 AM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116656537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.4116656537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1078952717 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 233512773 ps |
| CPU time | 10.23 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:45 AM UTC 24 |
| Peak memory | 252468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078952717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1078952717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.96039583 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 301470175 ps |
| CPU time | 3.52 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:38 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96039583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.96039583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.3264296837 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 994227313 ps |
| CPU time | 6 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:41 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264296837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3264296837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.755456526 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 625059286 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 254988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755456526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.755456526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.4258219170 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 546105658 ps |
| CPU time | 12.88 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:48 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258219170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4258219170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.1811325876 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 1722394403 ps |
| CPU time | 6.78 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:42 AM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811325876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1811325876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.3810185375 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 4308001282 ps |
| CPU time | 13.72 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:49 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810185375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3810185375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.4242283134 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 183489574 ps |
| CPU time | 3.59 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:38 AM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242283134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4242283134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.4200372899 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 176000783 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 09:47:33 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200372899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.4200372899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.3079110047 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 130092367 ps |
| CPU time | 4.05 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079110047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3079110047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.3913337183 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 178516869 ps |
| CPU time | 7.51 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:42 AM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913337183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3913337183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.3811094958 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 362390674 ps |
| CPU time | 3.72 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811094958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3811094958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.3648230582 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 1920608484 ps |
| CPU time | 12.53 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:48 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648230582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3648230582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2513219542 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 108508487 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513219542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2513219542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.2555331119 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 349030323 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555331119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2555331119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.1902895699 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 607468768 ps |
| CPU time | 3.25 seconds |
| Started | Oct 15 09:40:04 AM UTC 24 |
| Finished | Oct 15 09:40:08 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902895699 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1902895699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.3539836825 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 6951959638 ps |
| CPU time | 67.57 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:41:07 AM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539836825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3539836825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.4186918415 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 814087340 ps |
| CPU time | 27.13 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:27 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186918415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.4186918415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.3079865408 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1513322354 ps |
| CPU time | 23.98 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:23 AM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079865408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.3079865408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.1028088927 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 582799055 ps |
| CPU time | 5.48 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:04 AM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028088927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1028088927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.3448320109 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1068831095 ps |
| CPU time | 13.76 seconds |
| Started | Oct 15 09:39:59 AM UTC 24 |
| Finished | Oct 15 09:40:14 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448320109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3448320109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.1783742023 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 724861388 ps |
| CPU time | 16.05 seconds |
| Started | Oct 15 09:39:59 AM UTC 24 |
| Finished | Oct 15 09:40:17 AM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783742023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1783742023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.3712995270 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 347504003 ps |
| CPU time | 5.54 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:04 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712995270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3712995270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.3687307801 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 331524144 ps |
| CPU time | 7.26 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:06 AM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687307801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3687307801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.548972892 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 392353438 ps |
| CPU time | 6.11 seconds |
| Started | Oct 15 09:39:59 AM UTC 24 |
| Finished | Oct 15 09:40:06 AM UTC 24 |
| Peak memory | 259108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548972892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.548972892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.1012186744 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 327121252 ps |
| CPU time | 6.36 seconds |
| Started | Oct 15 09:39:57 AM UTC 24 |
| Finished | Oct 15 09:40:05 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012186744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1012186744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.534811488 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 710639528 ps |
| CPU time | 8.48 seconds |
| Started | Oct 15 09:40:02 AM UTC 24 |
| Finished | Oct 15 09:40:11 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534811488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.534811488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.1744094395 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 163763226 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744094395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1744094395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.23301033 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 590542698 ps |
| CPU time | 7.53 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:43 AM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23301033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.23301033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.42204749 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 147383691 ps |
| CPU time | 4.4 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42204749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.42204749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.1330029305 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 656134833 ps |
| CPU time | 10.42 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:46 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330029305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1330029305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.202113278 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 588093923 ps |
| CPU time | 4.02 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:39 AM UTC 24 |
| Peak memory | 254992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202113278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.202113278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.3538868490 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 219234378 ps |
| CPU time | 2.94 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:38 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538868490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3538868490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.3638659268 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 193093302 ps |
| CPU time | 4.97 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638659268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3638659268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.2691023124 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 682481511 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 09:47:34 AM UTC 24 |
| Finished | Oct 15 09:47:40 AM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691023124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2691023124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.2009086098 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 103026951 ps |
| CPU time | 4.45 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009086098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2009086098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.4200475135 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 385421831 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:53 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200475135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.4200475135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1952949948 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 228664315 ps |
| CPU time | 3.85 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952949948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1952949948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.1140471276 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 115243335 ps |
| CPU time | 5.28 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:52 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140471276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1140471276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.4051716521 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 1796835119 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051716521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.4051716521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2942183436 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 187240231 ps |
| CPU time | 3.58 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942183436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2942183436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.618740482 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 197827291 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618740482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.618740482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1700111458 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 17014175922 ps |
| CPU time | 26.63 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:48:13 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700111458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1700111458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.3197006033 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 176162332 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197006033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3197006033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.459344638 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 334508162 ps |
| CPU time | 7.21 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:54 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459344638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.459344638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2306877033 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 238836060 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 09:47:45 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 254360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306877033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2306877033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2797434718 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 1054932306 ps |
| CPU time | 12.42 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797434718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2797434718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.2252927853 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 142651620 ps |
| CPU time | 3.06 seconds |
| Started | Oct 15 09:40:11 AM UTC 24 |
| Finished | Oct 15 09:40:15 AM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252927853 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2252927853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.4141942575 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4642473938 ps |
| CPU time | 40.1 seconds |
| Started | Oct 15 09:40:06 AM UTC 24 |
| Finished | Oct 15 09:40:48 AM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141942575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.4141942575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.794873037 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 21005454322 ps |
| CPU time | 39.88 seconds |
| Started | Oct 15 09:40:05 AM UTC 24 |
| Finished | Oct 15 09:40:46 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794873037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.794873037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.3793878366 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 10735981269 ps |
| CPU time | 19.18 seconds |
| Started | Oct 15 09:40:05 AM UTC 24 |
| Finished | Oct 15 09:40:25 AM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793878366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3793878366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.1304239521 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 665700862 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 09:40:05 AM UTC 24 |
| Finished | Oct 15 09:40:12 AM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304239521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1304239521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.3628769915 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 538966721 ps |
| CPU time | 12.17 seconds |
| Started | Oct 15 09:40:09 AM UTC 24 |
| Finished | Oct 15 09:40:22 AM UTC 24 |
| Peak memory | 253016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628769915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3628769915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.1334479256 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 516991671 ps |
| CPU time | 9.9 seconds |
| Started | Oct 15 09:40:05 AM UTC 24 |
| Finished | Oct 15 09:40:16 AM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334479256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1334479256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.3280406493 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 602773147 ps |
| CPU time | 14.57 seconds |
| Started | Oct 15 09:40:05 AM UTC 24 |
| Finished | Oct 15 09:40:21 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280406493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.3280406493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2219676799 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 867799570 ps |
| CPU time | 14.09 seconds |
| Started | Oct 15 09:40:09 AM UTC 24 |
| Finished | Oct 15 09:40:24 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219676799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2219676799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.3171008710 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2107040274 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 09:40:04 AM UTC 24 |
| Finished | Oct 15 09:40:13 AM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171008710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3171008710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.4124894184 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3295268984 ps |
| CPU time | 101.11 seconds |
| Started | Oct 15 09:40:09 AM UTC 24 |
| Finished | Oct 15 09:41:52 AM UTC 24 |
| Peak memory | 269640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4124894184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.otp_ctrl_stress_all_with_rand_reset.4124894184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.3393745148 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1868130771 ps |
| CPU time | 23.9 seconds |
| Started | Oct 15 09:40:09 AM UTC 24 |
| Finished | Oct 15 09:40:34 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393745148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3393745148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.2726230593 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 159842536 ps |
| CPU time | 3.5 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726230593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2726230593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2577341542 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 143138469 ps |
| CPU time | 4.16 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577341542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2577341542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.567825567 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 1050098505 ps |
| CPU time | 18.64 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:48:05 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567825567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.567825567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.2163956730 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 202139141 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:50 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163956730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2163956730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3475103200 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 1477208181 ps |
| CPU time | 18.67 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:48:06 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475103200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3475103200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.1610795987 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 278176631 ps |
| CPU time | 4.46 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610795987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1610795987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3584089902 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 1055058771 ps |
| CPU time | 6.16 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:53 AM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584089902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3584089902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.579697221 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 165574488 ps |
| CPU time | 4.57 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:52 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579697221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.579697221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.292040748 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 986997391 ps |
| CPU time | 6.32 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:53 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292040748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.292040748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.226731165 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 310683762 ps |
| CPU time | 3.51 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226731165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.226731165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1054532930 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 158792528 ps |
| CPU time | 6.24 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:53 AM UTC 24 |
| Peak memory | 252560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054532930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1054532930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.3982155142 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 435185098 ps |
| CPU time | 3.89 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982155142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3982155142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1219406820 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 298768896 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:54 AM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219406820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1219406820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.1643791018 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 1830481675 ps |
| CPU time | 5.9 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:53 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643791018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1643791018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1996902150 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 475290698 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996902150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1996902150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1359140831 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 160766832 ps |
| CPU time | 4.61 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:52 AM UTC 24 |
| Peak memory | 254352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359140831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1359140831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.3635713240 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 1084099869 ps |
| CPU time | 12.98 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635713240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3635713240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.3403183052 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 126893054 ps |
| CPU time | 3.71 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403183052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3403183052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.2438444991 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 139470788 ps |
| CPU time | 3.85 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438444991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2438444991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.23493604 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 76176856 ps |
| CPU time | 3.14 seconds |
| Started | Oct 15 09:37:56 AM UTC 24 |
| Finished | Oct 15 09:38:00 AM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23493604 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.23493604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.1067039182 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1265315339 ps |
| CPU time | 20.09 seconds |
| Started | Oct 15 09:37:49 AM UTC 24 |
| Finished | Oct 15 09:38:10 AM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067039182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1067039182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.1292359939 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9930983086 ps |
| CPU time | 28.14 seconds |
| Started | Oct 15 09:37:51 AM UTC 24 |
| Finished | Oct 15 09:38:21 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292359939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1292359939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.1072950677 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2643577704 ps |
| CPU time | 9.15 seconds |
| Started | Oct 15 09:37:49 AM UTC 24 |
| Finished | Oct 15 09:37:59 AM UTC 24 |
| Peak memory | 255024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072950677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1072950677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.3104867610 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 163034184 ps |
| CPU time | 4.92 seconds |
| Started | Oct 15 09:37:51 AM UTC 24 |
| Finished | Oct 15 09:37:57 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104867610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3104867610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1258163305 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 989439478 ps |
| CPU time | 10.58 seconds |
| Started | Oct 15 09:37:49 AM UTC 24 |
| Finished | Oct 15 09:38:01 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258163305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1258163305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.3259808786 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 106146451 ps |
| CPU time | 4.91 seconds |
| Started | Oct 15 09:37:52 AM UTC 24 |
| Finished | Oct 15 09:37:58 AM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259808786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3259808786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.3916890481 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 426190161 ps |
| CPU time | 9.21 seconds |
| Started | Oct 15 09:37:48 AM UTC 24 |
| Finished | Oct 15 09:37:58 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916890481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3916890481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.1655189080 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 87110447232 ps |
| CPU time | 362.65 seconds |
| Started | Oct 15 09:37:53 AM UTC 24 |
| Finished | Oct 15 09:44:01 AM UTC 24 |
| Peak memory | 265252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655189080 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.1655189080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.737441246 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2801163297 ps |
| CPU time | 24.47 seconds |
| Started | Oct 15 09:37:53 AM UTC 24 |
| Finished | Oct 15 09:38:19 AM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737441246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.737441246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.1232307394 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 42813140 ps |
| CPU time | 1.68 seconds |
| Started | Oct 15 09:40:19 AM UTC 24 |
| Finished | Oct 15 09:40:22 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232307394 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1232307394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.1125900284 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 420748323 ps |
| CPU time | 4.26 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:19 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125900284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1125900284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.684151230 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1184813749 ps |
| CPU time | 37.14 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:53 AM UTC 24 |
| Peak memory | 254732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684151230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.684151230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.278582318 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 22925835300 ps |
| CPU time | 40.95 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:56 AM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278582318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.278582318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.3167464809 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 222034089 ps |
| CPU time | 5.31 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:20 AM UTC 24 |
| Peak memory | 254964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167464809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3167464809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.721833497 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 548480528 ps |
| CPU time | 11.9 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:27 AM UTC 24 |
| Peak memory | 254860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721833497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.721833497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.1955572845 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 815814422 ps |
| CPU time | 21.36 seconds |
| Started | Oct 15 09:40:15 AM UTC 24 |
| Finished | Oct 15 09:40:38 AM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955572845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1955572845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.1826896542 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 173389612 ps |
| CPU time | 6.97 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:22 AM UTC 24 |
| Peak memory | 259148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826896542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1826896542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.1119914848 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 373387721 ps |
| CPU time | 14.18 seconds |
| Started | Oct 15 09:40:14 AM UTC 24 |
| Finished | Oct 15 09:40:29 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119914848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1119914848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.1975068557 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3760373090 ps |
| CPU time | 19.65 seconds |
| Started | Oct 15 09:40:15 AM UTC 24 |
| Finished | Oct 15 09:40:36 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975068557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1975068557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.66782862 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 650530192 ps |
| CPU time | 13.85 seconds |
| Started | Oct 15 09:40:11 AM UTC 24 |
| Finished | Oct 15 09:40:26 AM UTC 24 |
| Peak memory | 253056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66782862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.66782862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.3231546215 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5680468839 ps |
| CPU time | 95.85 seconds |
| Started | Oct 15 09:40:18 AM UTC 24 |
| Finished | Oct 15 09:41:56 AM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231546215 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.3231546215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1849161279 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 12616996138 ps |
| CPU time | 224.16 seconds |
| Started | Oct 15 09:40:17 AM UTC 24 |
| Finished | Oct 15 09:44:05 AM UTC 24 |
| Peak memory | 269640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1849161279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.otp_ctrl_stress_all_with_rand_reset.1849161279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.1013395387 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 764746556 ps |
| CPU time | 23.8 seconds |
| Started | Oct 15 09:40:17 AM UTC 24 |
| Finished | Oct 15 09:40:42 AM UTC 24 |
| Peak memory | 259124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013395387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1013395387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.3258041658 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 145004233 ps |
| CPU time | 3.66 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258041658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3258041658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.4243660623 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 1990767603 ps |
| CPU time | 5.88 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:53 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243660623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.4243660623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3285221895 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 120030121 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 09:47:46 AM UTC 24 |
| Finished | Oct 15 09:47:51 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285221895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3285221895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.3475769804 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 160024873 ps |
| CPU time | 3.42 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475769804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3475769804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.1335300773 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 151344882 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335300773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1335300773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2158863680 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 2726664961 ps |
| CPU time | 5.5 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158863680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2158863680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.1498091135 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 1743738032 ps |
| CPU time | 5.35 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 254212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498091135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1498091135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1121829799 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2727144906 ps |
| CPU time | 6.33 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:02 AM UTC 24 |
| Peak memory | 254352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121829799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1121829799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.1749003877 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 153481864 ps |
| CPU time | 3.45 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749003877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1749003877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.3366567393 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2522385969 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366567393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3366567393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.2585406071 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 907004668 ps |
| CPU time | 5.19 seconds |
| Started | Oct 15 09:40:28 AM UTC 24 |
| Finished | Oct 15 09:40:34 AM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585406071 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2585406071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.3986276510 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1763488360 ps |
| CPU time | 36.63 seconds |
| Started | Oct 15 09:40:23 AM UTC 24 |
| Finished | Oct 15 09:41:01 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986276510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3986276510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.2066723980 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 23817014690 ps |
| CPU time | 68.2 seconds |
| Started | Oct 15 09:40:23 AM UTC 24 |
| Finished | Oct 15 09:41:33 AM UTC 24 |
| Peak memory | 263440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066723980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.2066723980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.799885665 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1566362093 ps |
| CPU time | 14.56 seconds |
| Started | Oct 15 09:40:23 AM UTC 24 |
| Finished | Oct 15 09:40:39 AM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799885665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.799885665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.2812692264 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 512784196 ps |
| CPU time | 5.54 seconds |
| Started | Oct 15 09:40:22 AM UTC 24 |
| Finished | Oct 15 09:40:29 AM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812692264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2812692264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.1468939551 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 881245635 ps |
| CPU time | 11.86 seconds |
| Started | Oct 15 09:40:25 AM UTC 24 |
| Finished | Oct 15 09:40:38 AM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468939551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1468939551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.1440067161 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1104159701 ps |
| CPU time | 14.64 seconds |
| Started | Oct 15 09:40:25 AM UTC 24 |
| Finished | Oct 15 09:40:41 AM UTC 24 |
| Peak memory | 253076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440067161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1440067161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.286044162 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 307273751 ps |
| CPU time | 7.42 seconds |
| Started | Oct 15 09:40:23 AM UTC 24 |
| Finished | Oct 15 09:40:31 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286044162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.286044162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.3099782215 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 673428890 ps |
| CPU time | 17.44 seconds |
| Started | Oct 15 09:40:23 AM UTC 24 |
| Finished | Oct 15 09:40:41 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099782215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3099782215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.3029071780 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2303326009 ps |
| CPU time | 6.16 seconds |
| Started | Oct 15 09:40:25 AM UTC 24 |
| Finished | Oct 15 09:40:33 AM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029071780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3029071780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.1764413377 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 260994939 ps |
| CPU time | 5.85 seconds |
| Started | Oct 15 09:40:20 AM UTC 24 |
| Finished | Oct 15 09:40:27 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764413377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1764413377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.339259378 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 158250384693 ps |
| CPU time | 237.14 seconds |
| Started | Oct 15 09:40:28 AM UTC 24 |
| Finished | Oct 15 09:44:29 AM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339259378 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.339259378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.626936638 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 8182829162 ps |
| CPU time | 119.6 seconds |
| Started | Oct 15 09:40:28 AM UTC 24 |
| Finished | Oct 15 09:42:30 AM UTC 24 |
| Peak memory | 269388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=626936638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.626936638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.3385609376 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 909503085 ps |
| CPU time | 21.94 seconds |
| Started | Oct 15 09:40:28 AM UTC 24 |
| Finished | Oct 15 09:40:51 AM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385609376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3385609376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1070751983 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 489816260 ps |
| CPU time | 4.27 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070751983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1070751983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1510179708 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 137459641 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 09:47:54 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510179708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1510179708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2117393489 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 123768880 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117393489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2117393489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1419798318 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 247639408 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419798318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1419798318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3741731830 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 122304178 ps |
| CPU time | 5.22 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741731830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3741731830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.1445611759 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 214735683 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445611759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1445611759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3363994375 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 126696463 ps |
| CPU time | 5.35 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363994375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3363994375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.652801237 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 312063293 ps |
| CPU time | 4.02 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652801237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.652801237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3590349549 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 111114165 ps |
| CPU time | 4.23 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590349549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3590349549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.1154362666 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 1764031055 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154362666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1154362666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.2150578101 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 72949680 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 09:40:40 AM UTC 24 |
| Finished | Oct 15 09:40:43 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150578101 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2150578101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.624163690 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 604553009 ps |
| CPU time | 17.44 seconds |
| Started | Oct 15 09:40:34 AM UTC 24 |
| Finished | Oct 15 09:40:53 AM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624163690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.624163690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.3850429994 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1117251705 ps |
| CPU time | 20.7 seconds |
| Started | Oct 15 09:40:34 AM UTC 24 |
| Finished | Oct 15 09:40:56 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850429994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3850429994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.929192358 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 661491786 ps |
| CPU time | 9.5 seconds |
| Started | Oct 15 09:40:33 AM UTC 24 |
| Finished | Oct 15 09:40:43 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929192358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.929192358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.3591131412 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 186814625 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 09:40:28 AM UTC 24 |
| Finished | Oct 15 09:40:33 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591131412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3591131412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2390180209 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1212867759 ps |
| CPU time | 24.87 seconds |
| Started | Oct 15 09:40:34 AM UTC 24 |
| Finished | Oct 15 09:41:00 AM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390180209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2390180209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1337606755 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 828412314 ps |
| CPU time | 14.89 seconds |
| Started | Oct 15 09:40:36 AM UTC 24 |
| Finished | Oct 15 09:40:52 AM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337606755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1337606755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.528065566 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 84938132 ps |
| CPU time | 5.71 seconds |
| Started | Oct 15 09:40:30 AM UTC 24 |
| Finished | Oct 15 09:40:37 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528065566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.528065566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.1765853706 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 189964421 ps |
| CPU time | 6.99 seconds |
| Started | Oct 15 09:40:30 AM UTC 24 |
| Finished | Oct 15 09:40:38 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765853706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1765853706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.1979256351 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 924350534 ps |
| CPU time | 8.37 seconds |
| Started | Oct 15 09:40:36 AM UTC 24 |
| Finished | Oct 15 09:40:45 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979256351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1979256351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.282189795 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2765389989 ps |
| CPU time | 7.1 seconds |
| Started | Oct 15 09:40:28 AM UTC 24 |
| Finished | Oct 15 09:40:36 AM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282189795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.282189795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.3126779023 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1433706288 ps |
| CPU time | 12.29 seconds |
| Started | Oct 15 09:40:40 AM UTC 24 |
| Finished | Oct 15 09:40:53 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126779023 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.3126779023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.181314451 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1564039351 ps |
| CPU time | 19.6 seconds |
| Started | Oct 15 09:40:37 AM UTC 24 |
| Finished | Oct 15 09:40:58 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181314451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.181314451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.3385717625 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 113367505 ps |
| CPU time | 3.22 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385717625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3385717625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1944618184 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 2691068027 ps |
| CPU time | 4.95 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944618184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1944618184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2300400602 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 299815660 ps |
| CPU time | 3.62 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300400602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2300400602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.2785432827 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 333027706 ps |
| CPU time | 4.69 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785432827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2785432827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1051685061 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 145323485 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051685061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1051685061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.3436472469 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 136392973 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436472469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3436472469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.834065199 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 689492906 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834065199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.834065199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.4165284993 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 102566985 ps |
| CPU time | 2.69 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:47:59 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165284993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.4165284993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1355303606 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 496906168 ps |
| CPU time | 4.73 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355303606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1355303606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.1694133495 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 128597918 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694133495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1694133495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.2850117705 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 54338967 ps |
| CPU time | 2.71 seconds |
| Started | Oct 15 09:40:49 AM UTC 24 |
| Finished | Oct 15 09:40:53 AM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850117705 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2850117705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.3829924158 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 309698742 ps |
| CPU time | 5.17 seconds |
| Started | Oct 15 09:40:44 AM UTC 24 |
| Finished | Oct 15 09:40:50 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829924158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3829924158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.1531413577 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1878877217 ps |
| CPU time | 24.83 seconds |
| Started | Oct 15 09:40:44 AM UTC 24 |
| Finished | Oct 15 09:41:10 AM UTC 24 |
| Peak memory | 252996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531413577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1531413577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.2604341464 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2456628027 ps |
| CPU time | 22.76 seconds |
| Started | Oct 15 09:40:41 AM UTC 24 |
| Finished | Oct 15 09:41:05 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604341464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2604341464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.2999056273 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 361552856 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 09:40:40 AM UTC 24 |
| Finished | Oct 15 09:40:45 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999056273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2999056273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.901824833 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 508739378 ps |
| CPU time | 13.81 seconds |
| Started | Oct 15 09:40:44 AM UTC 24 |
| Finished | Oct 15 09:40:59 AM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901824833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.901824833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.3666822658 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1569480426 ps |
| CPU time | 24.41 seconds |
| Started | Oct 15 09:40:44 AM UTC 24 |
| Finished | Oct 15 09:41:10 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666822658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3666822658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.950293006 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1534833637 ps |
| CPU time | 6.91 seconds |
| Started | Oct 15 09:40:40 AM UTC 24 |
| Finished | Oct 15 09:40:48 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950293006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.950293006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.1444811258 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1419775921 ps |
| CPU time | 17.75 seconds |
| Started | Oct 15 09:40:40 AM UTC 24 |
| Finished | Oct 15 09:40:59 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444811258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1444811258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.426585752 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4170956128 ps |
| CPU time | 13.26 seconds |
| Started | Oct 15 09:40:44 AM UTC 24 |
| Finished | Oct 15 09:40:59 AM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426585752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.426585752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.409081510 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 4413617533 ps |
| CPU time | 9.69 seconds |
| Started | Oct 15 09:40:40 AM UTC 24 |
| Finished | Oct 15 09:40:51 AM UTC 24 |
| Peak memory | 259264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409081510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.409081510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1582379612 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 7848675301 ps |
| CPU time | 76.17 seconds |
| Started | Oct 15 09:40:46 AM UTC 24 |
| Finished | Oct 15 09:42:03 AM UTC 24 |
| Peak memory | 269352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1582379612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.1582379612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.2053801570 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 208119652 ps |
| CPU time | 5.88 seconds |
| Started | Oct 15 09:40:45 AM UTC 24 |
| Finished | Oct 15 09:40:52 AM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053801570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2053801570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.1173972577 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 275640973 ps |
| CPU time | 3.71 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173972577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.1173972577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.2898025607 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 246857802 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898025607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2898025607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.153692295 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 1580351667 ps |
| CPU time | 4.11 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153692295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.153692295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2732238683 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 149533997 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732238683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2732238683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.990667383 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 150822756 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:00 AM UTC 24 |
| Peak memory | 254800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990667383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.990667383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.941310433 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 222720081 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 09:47:55 AM UTC 24 |
| Finished | Oct 15 09:48:01 AM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941310433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.941310433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2525691406 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 143344683 ps |
| CPU time | 3.09 seconds |
| Started | Oct 15 09:47:58 AM UTC 24 |
| Finished | Oct 15 09:48:02 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525691406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2525691406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.3258725518 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 167295649 ps |
| CPU time | 4.02 seconds |
| Started | Oct 15 09:47:58 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258725518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3258725518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1946834455 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 301079261 ps |
| CPU time | 3.26 seconds |
| Started | Oct 15 09:47:58 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946834455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1946834455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.2824451460 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 323123422 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 09:47:58 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824451460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2824451460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.3185213273 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 819313075 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 09:40:57 AM UTC 24 |
| Finished | Oct 15 09:41:02 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185213273 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3185213273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.1165037808 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2212111563 ps |
| CPU time | 24.06 seconds |
| Started | Oct 15 09:40:53 AM UTC 24 |
| Finished | Oct 15 09:41:18 AM UTC 24 |
| Peak memory | 254736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165037808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1165037808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.4192386444 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 582475457 ps |
| CPU time | 20.62 seconds |
| Started | Oct 15 09:40:51 AM UTC 24 |
| Finished | Oct 15 09:41:13 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192386444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.4192386444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.1238726810 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 338398778 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 09:40:49 AM UTC 24 |
| Finished | Oct 15 09:40:56 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238726810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1238726810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.1250835267 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 622618284 ps |
| CPU time | 9.35 seconds |
| Started | Oct 15 09:40:53 AM UTC 24 |
| Finished | Oct 15 09:41:04 AM UTC 24 |
| Peak memory | 255100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250835267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1250835267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.3083614818 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1220338797 ps |
| CPU time | 16.03 seconds |
| Started | Oct 15 09:40:55 AM UTC 24 |
| Finished | Oct 15 09:41:12 AM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083614818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3083614818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1510640845 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 527330725 ps |
| CPU time | 13.19 seconds |
| Started | Oct 15 09:40:51 AM UTC 24 |
| Finished | Oct 15 09:41:05 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510640845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1510640845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.3592223875 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1541220624 ps |
| CPU time | 23.91 seconds |
| Started | Oct 15 09:40:51 AM UTC 24 |
| Finished | Oct 15 09:41:16 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592223875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3592223875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.3613241388 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 259173138 ps |
| CPU time | 4.72 seconds |
| Started | Oct 15 09:40:55 AM UTC 24 |
| Finished | Oct 15 09:41:01 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613241388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3613241388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.832022327 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 222755562 ps |
| CPU time | 7.5 seconds |
| Started | Oct 15 09:40:49 AM UTC 24 |
| Finished | Oct 15 09:40:58 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832022327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.832022327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.3152020991 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 29048960472 ps |
| CPU time | 171.01 seconds |
| Started | Oct 15 09:40:57 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 273412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152020991 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.3152020991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.4128707965 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1142687622 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 09:40:55 AM UTC 24 |
| Finished | Oct 15 09:41:05 AM UTC 24 |
| Peak memory | 259180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128707965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.4128707965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.3763145987 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 490668028 ps |
| CPU time | 3.34 seconds |
| Started | Oct 15 09:47:59 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763145987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3763145987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.3384794973 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2171064910 ps |
| CPU time | 3.67 seconds |
| Started | Oct 15 09:47:59 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 254764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384794973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3384794973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.2149318784 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 2136757313 ps |
| CPU time | 6.55 seconds |
| Started | Oct 15 09:47:59 AM UTC 24 |
| Finished | Oct 15 09:48:06 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149318784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2149318784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1022278585 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 112610918 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 09:47:59 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022278585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1022278585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.720383241 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 287579734 ps |
| CPU time | 3.31 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720383241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.720383241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2252577879 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 2810640247 ps |
| CPU time | 5.42 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252577879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2252577879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3375464053 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2421691283 ps |
| CPU time | 6 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:13 AM UTC 24 |
| Peak memory | 254764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375464053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3375464053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.4212704523 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 1750955793 ps |
| CPU time | 5.09 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 254820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212704523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4212704523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1288800468 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 104598885 ps |
| CPU time | 3.21 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288800468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1288800468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.2001739219 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 72651277 ps |
| CPU time | 2.83 seconds |
| Started | Oct 15 09:41:07 AM UTC 24 |
| Finished | Oct 15 09:41:10 AM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001739219 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2001739219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.690281617 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 11641475061 ps |
| CPU time | 37.32 seconds |
| Started | Oct 15 09:41:00 AM UTC 24 |
| Finished | Oct 15 09:41:39 AM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690281617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.690281617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.3452985397 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 13495900508 ps |
| CPU time | 36.88 seconds |
| Started | Oct 15 09:41:00 AM UTC 24 |
| Finished | Oct 15 09:41:38 AM UTC 24 |
| Peak memory | 254160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452985397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3452985397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.870816692 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 20257434029 ps |
| CPU time | 49.72 seconds |
| Started | Oct 15 09:41:00 AM UTC 24 |
| Finished | Oct 15 09:41:51 AM UTC 24 |
| Peak memory | 255180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870816692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.870816692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.1498276202 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 268957432 ps |
| CPU time | 4.99 seconds |
| Started | Oct 15 09:41:00 AM UTC 24 |
| Finished | Oct 15 09:41:06 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498276202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1498276202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.4166171653 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3545861534 ps |
| CPU time | 26.93 seconds |
| Started | Oct 15 09:41:03 AM UTC 24 |
| Finished | Oct 15 09:41:31 AM UTC 24 |
| Peak memory | 254900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166171653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4166171653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.1034172141 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 281921131 ps |
| CPU time | 8.66 seconds |
| Started | Oct 15 09:41:03 AM UTC 24 |
| Finished | Oct 15 09:41:12 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034172141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1034172141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.3976111714 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 328197096 ps |
| CPU time | 6.85 seconds |
| Started | Oct 15 09:41:00 AM UTC 24 |
| Finished | Oct 15 09:41:08 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976111714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3976111714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.3897823227 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 537637667 ps |
| CPU time | 17.71 seconds |
| Started | Oct 15 09:41:00 AM UTC 24 |
| Finished | Oct 15 09:41:19 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897823227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3897823227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.1461123779 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 253989172 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 09:41:03 AM UTC 24 |
| Finished | Oct 15 09:41:11 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461123779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1461123779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.964253374 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 167833646 ps |
| CPU time | 7.49 seconds |
| Started | Oct 15 09:40:57 AM UTC 24 |
| Finished | Oct 15 09:41:06 AM UTC 24 |
| Peak memory | 252916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964253374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.964253374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.4241468520 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 22624903693 ps |
| CPU time | 217 seconds |
| Started | Oct 15 09:41:03 AM UTC 24 |
| Finished | Oct 15 09:44:43 AM UTC 24 |
| Peak memory | 285784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4241468520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.otp_ctrl_stress_all_with_rand_reset.4241468520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.254816891 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1294228443 ps |
| CPU time | 25.47 seconds |
| Started | Oct 15 09:41:03 AM UTC 24 |
| Finished | Oct 15 09:41:30 AM UTC 24 |
| Peak memory | 253072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254816891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.254816891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.844257933 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 107390301 ps |
| CPU time | 3.85 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844257933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.844257933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1337797871 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2127305098 ps |
| CPU time | 5.45 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337797871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1337797871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.3123511763 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 98162701 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123511763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3123511763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.665308323 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 182863464 ps |
| CPU time | 4.13 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665308323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.665308323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.894249382 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 121190360 ps |
| CPU time | 2.94 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894249382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.894249382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1256326629 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 426868326 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256326629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1256326629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1721912693 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 103441807 ps |
| CPU time | 2.76 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721912693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1721912693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.37663933 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 1832910890 ps |
| CPU time | 3.58 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37663933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.37663933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.1051305012 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 153462101 ps |
| CPU time | 3.51 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051305012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1051305012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2619714400 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 242111042 ps |
| CPU time | 2.57 seconds |
| Started | Oct 15 09:41:18 AM UTC 24 |
| Finished | Oct 15 09:41:21 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619714400 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2619714400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.2368040244 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 285938576 ps |
| CPU time | 20.55 seconds |
| Started | Oct 15 09:41:09 AM UTC 24 |
| Finished | Oct 15 09:41:31 AM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368040244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2368040244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.2086913727 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 554525653 ps |
| CPU time | 17.57 seconds |
| Started | Oct 15 09:41:09 AM UTC 24 |
| Finished | Oct 15 09:41:27 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086913727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2086913727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.3796369211 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 112007980 ps |
| CPU time | 3.88 seconds |
| Started | Oct 15 09:41:07 AM UTC 24 |
| Finished | Oct 15 09:41:12 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796369211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3796369211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.3725822328 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1447426103 ps |
| CPU time | 24.02 seconds |
| Started | Oct 15 09:41:17 AM UTC 24 |
| Finished | Oct 15 09:41:43 AM UTC 24 |
| Peak memory | 255088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725822328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3725822328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.3870262622 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1773775514 ps |
| CPU time | 21.67 seconds |
| Started | Oct 15 09:41:17 AM UTC 24 |
| Finished | Oct 15 09:41:40 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870262622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3870262622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.2901039772 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 727467946 ps |
| CPU time | 12.03 seconds |
| Started | Oct 15 09:41:07 AM UTC 24 |
| Finished | Oct 15 09:41:20 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901039772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2901039772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.526349829 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 10497856236 ps |
| CPU time | 34.11 seconds |
| Started | Oct 15 09:41:07 AM UTC 24 |
| Finished | Oct 15 09:41:42 AM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526349829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.526349829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.532654713 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4535309240 ps |
| CPU time | 12.2 seconds |
| Started | Oct 15 09:41:17 AM UTC 24 |
| Finished | Oct 15 09:41:31 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532654713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.532654713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.3892438455 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 477369674 ps |
| CPU time | 10.43 seconds |
| Started | Oct 15 09:41:07 AM UTC 24 |
| Finished | Oct 15 09:41:18 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892438455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3892438455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.4256197971 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7876598173 ps |
| CPU time | 74.01 seconds |
| Started | Oct 15 09:41:18 AM UTC 24 |
| Finished | Oct 15 09:42:33 AM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256197971 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.4256197971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1910887081 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 21592754647 ps |
| CPU time | 104.13 seconds |
| Started | Oct 15 09:41:18 AM UTC 24 |
| Finished | Oct 15 09:43:04 AM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1910887081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.otp_ctrl_stress_all_with_rand_reset.1910887081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.374928509 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 305268391 ps |
| CPU time | 5.86 seconds |
| Started | Oct 15 09:41:18 AM UTC 24 |
| Finished | Oct 15 09:41:24 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374928509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.374928509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.849521097 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 1659070942 ps |
| CPU time | 3.74 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849521097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.849521097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3423192621 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 299379482 ps |
| CPU time | 3.8 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423192621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3423192621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1955299688 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 87074378 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955299688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1955299688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3986742304 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 244975073 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986742304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3986742304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1191575840 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 270112987 ps |
| CPU time | 3.09 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191575840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1191575840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.614874181 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 126294625 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614874181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.614874181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.1568796759 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 104491950 ps |
| CPU time | 3.32 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 254744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568796759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1568796759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.518794166 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 270277529 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518794166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.518794166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.1945428590 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 1999090775 ps |
| CPU time | 5.66 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:13 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945428590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1945428590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.2581116086 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 134934284 ps |
| CPU time | 4.44 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 254744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581116086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2581116086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2467541025 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 126447500 ps |
| CPU time | 3.59 seconds |
| Started | Oct 15 09:41:32 AM UTC 24 |
| Finished | Oct 15 09:41:37 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467541025 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2467541025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.4092830775 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 4784363933 ps |
| CPU time | 18.19 seconds |
| Started | Oct 15 09:41:21 AM UTC 24 |
| Finished | Oct 15 09:41:41 AM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092830775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.4092830775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.3273664589 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 476650836 ps |
| CPU time | 16.67 seconds |
| Started | Oct 15 09:41:20 AM UTC 24 |
| Finished | Oct 15 09:41:38 AM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273664589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3273664589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.3104251332 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1171193288 ps |
| CPU time | 18.39 seconds |
| Started | Oct 15 09:41:20 AM UTC 24 |
| Finished | Oct 15 09:41:40 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104251332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3104251332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.3032099880 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 289969673 ps |
| CPU time | 6.16 seconds |
| Started | Oct 15 09:41:18 AM UTC 24 |
| Finished | Oct 15 09:41:25 AM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032099880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3032099880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.2113588501 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 169183848 ps |
| CPU time | 6.61 seconds |
| Started | Oct 15 09:41:22 AM UTC 24 |
| Finished | Oct 15 09:41:30 AM UTC 24 |
| Peak memory | 252828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113588501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2113588501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.710999601 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1339590520 ps |
| CPU time | 14.89 seconds |
| Started | Oct 15 09:41:27 AM UTC 24 |
| Finished | Oct 15 09:41:43 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710999601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.710999601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.1164268946 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 427595674 ps |
| CPU time | 12.25 seconds |
| Started | Oct 15 09:41:20 AM UTC 24 |
| Finished | Oct 15 09:41:34 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164268946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1164268946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.418404781 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 595766178 ps |
| CPU time | 16.1 seconds |
| Started | Oct 15 09:41:20 AM UTC 24 |
| Finished | Oct 15 09:41:38 AM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418404781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.418404781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.1926305595 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 176040720 ps |
| CPU time | 4.65 seconds |
| Started | Oct 15 09:41:27 AM UTC 24 |
| Finished | Oct 15 09:41:33 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926305595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1926305595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.76871828 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3587597083 ps |
| CPU time | 14.17 seconds |
| Started | Oct 15 09:41:18 AM UTC 24 |
| Finished | Oct 15 09:41:33 AM UTC 24 |
| Peak memory | 253088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76871828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.76871828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.2049456982 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2960308719 ps |
| CPU time | 60.78 seconds |
| Started | Oct 15 09:41:29 AM UTC 24 |
| Finished | Oct 15 09:42:31 AM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049456982 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.2049456982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.756592843 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 32060799713 ps |
| CPU time | 65.07 seconds |
| Started | Oct 15 09:41:29 AM UTC 24 |
| Finished | Oct 15 09:42:35 AM UTC 24 |
| Peak memory | 269388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=756592843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.756592843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.330760784 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 483030903 ps |
| CPU time | 9.2 seconds |
| Started | Oct 15 09:41:27 AM UTC 24 |
| Finished | Oct 15 09:41:37 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330760784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.330760784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2386242911 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 554899803 ps |
| CPU time | 2.93 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:10 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386242911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2386242911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2229983047 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 345015499 ps |
| CPU time | 3.5 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229983047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2229983047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3477832644 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 315394114 ps |
| CPU time | 3.84 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477832644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3477832644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3382153314 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 169527052 ps |
| CPU time | 4.08 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382153314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3382153314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.565626968 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 2355773266 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565626968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.565626968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1642618355 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 236253024 ps |
| CPU time | 4.75 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 254784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642618355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1642618355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.585586069 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 568452845 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 09:48:06 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585586069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.585586069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3354181048 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 213909235 ps |
| CPU time | 4 seconds |
| Started | Oct 15 09:48:07 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354181048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3354181048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.731200217 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 3057532223 ps |
| CPU time | 6.94 seconds |
| Started | Oct 15 09:48:07 AM UTC 24 |
| Finished | Oct 15 09:48:15 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731200217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.731200217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4255180928 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 536744457 ps |
| CPU time | 4.56 seconds |
| Started | Oct 15 09:48:07 AM UTC 24 |
| Finished | Oct 15 09:48:12 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255180928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.4255180928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.4063937685 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 152245303 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 09:41:39 AM UTC 24 |
| Finished | Oct 15 09:41:43 AM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063937685 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.4063937685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.2179266965 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 677789983 ps |
| CPU time | 21.43 seconds |
| Started | Oct 15 09:41:36 AM UTC 24 |
| Finished | Oct 15 09:41:59 AM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179266965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2179266965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.1620945460 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1172632970 ps |
| CPU time | 19.18 seconds |
| Started | Oct 15 09:41:33 AM UTC 24 |
| Finished | Oct 15 09:41:53 AM UTC 24 |
| Peak memory | 254860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620945460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1620945460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.2436872258 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2153827729 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 09:41:33 AM UTC 24 |
| Finished | Oct 15 09:41:39 AM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436872258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2436872258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.490217289 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4674573331 ps |
| CPU time | 30.54 seconds |
| Started | Oct 15 09:41:36 AM UTC 24 |
| Finished | Oct 15 09:42:08 AM UTC 24 |
| Peak memory | 259280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490217289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.490217289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2363397403 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2120312427 ps |
| CPU time | 14.92 seconds |
| Started | Oct 15 09:41:36 AM UTC 24 |
| Finished | Oct 15 09:41:53 AM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363397403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2363397403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.4225736725 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 148227990 ps |
| CPU time | 8.06 seconds |
| Started | Oct 15 09:41:33 AM UTC 24 |
| Finished | Oct 15 09:41:42 AM UTC 24 |
| Peak memory | 252736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225736725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.4225736725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.1450669611 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 309747012 ps |
| CPU time | 8.03 seconds |
| Started | Oct 15 09:41:33 AM UTC 24 |
| Finished | Oct 15 09:41:42 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450669611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1450669611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.4176186396 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 231883508 ps |
| CPU time | 6.94 seconds |
| Started | Oct 15 09:41:37 AM UTC 24 |
| Finished | Oct 15 09:41:45 AM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176186396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.4176186396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.425279383 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 753348106 ps |
| CPU time | 8.24 seconds |
| Started | Oct 15 09:41:32 AM UTC 24 |
| Finished | Oct 15 09:41:42 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425279383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.425279383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.2244115000 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 30275357594 ps |
| CPU time | 241.85 seconds |
| Started | Oct 15 09:41:39 AM UTC 24 |
| Finished | Oct 15 09:45:45 AM UTC 24 |
| Peak memory | 269532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244115000 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.2244115000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.2175074613 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 3144382299 ps |
| CPU time | 33.07 seconds |
| Started | Oct 15 09:41:37 AM UTC 24 |
| Finished | Oct 15 09:42:11 AM UTC 24 |
| Peak memory | 258932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175074613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2175074613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2750725450 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 146694597 ps |
| CPU time | 3.48 seconds |
| Started | Oct 15 09:48:07 AM UTC 24 |
| Finished | Oct 15 09:48:11 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750725450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2750725450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.2352189840 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 264016784 ps |
| CPU time | 4.52 seconds |
| Started | Oct 15 09:48:16 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352189840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2352189840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.572682088 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 258744588 ps |
| CPU time | 4.19 seconds |
| Started | Oct 15 09:48:16 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572682088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.572682088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1127029702 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 180682113 ps |
| CPU time | 4.35 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127029702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1127029702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.745954111 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 231236777 ps |
| CPU time | 4 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745954111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.745954111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3059102057 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 530320488 ps |
| CPU time | 4.8 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:23 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059102057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3059102057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.492156468 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 158266561 ps |
| CPU time | 4.65 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 254732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492156468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.492156468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.111470581 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 111347858 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111470581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.111470581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.3342243766 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 271442690 ps |
| CPU time | 3.16 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:21 AM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342243766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3342243766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2131405867 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 1480498591 ps |
| CPU time | 6.08 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:24 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131405867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2131405867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.1187843306 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 705208991 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 09:41:45 AM UTC 24 |
| Finished | Oct 15 09:41:49 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187843306 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1187843306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.3072112505 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1326285066 ps |
| CPU time | 14.9 seconds |
| Started | Oct 15 09:41:42 AM UTC 24 |
| Finished | Oct 15 09:41:59 AM UTC 24 |
| Peak memory | 255020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072112505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3072112505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.904626404 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 5543515634 ps |
| CPU time | 15.14 seconds |
| Started | Oct 15 09:41:42 AM UTC 24 |
| Finished | Oct 15 09:41:59 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904626404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.904626404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.4076298518 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 638130419 ps |
| CPU time | 6.82 seconds |
| Started | Oct 15 09:41:42 AM UTC 24 |
| Finished | Oct 15 09:41:51 AM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076298518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.4076298518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.669351046 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 186498136 ps |
| CPU time | 5.69 seconds |
| Started | Oct 15 09:41:39 AM UTC 24 |
| Finished | Oct 15 09:41:46 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669351046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.669351046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.117831564 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 935758192 ps |
| CPU time | 28.46 seconds |
| Started | Oct 15 09:41:42 AM UTC 24 |
| Finished | Oct 15 09:42:13 AM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117831564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.117831564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.203290252 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 844751486 ps |
| CPU time | 10.06 seconds |
| Started | Oct 15 09:41:42 AM UTC 24 |
| Finished | Oct 15 09:41:54 AM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203290252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.203290252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.4245333866 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 762700420 ps |
| CPU time | 10.93 seconds |
| Started | Oct 15 09:41:39 AM UTC 24 |
| Finished | Oct 15 09:41:52 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245333866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.4245333866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.1197425246 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5159036537 ps |
| CPU time | 11.36 seconds |
| Started | Oct 15 09:41:39 AM UTC 24 |
| Finished | Oct 15 09:41:52 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197425246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1197425246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.4236422434 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 144415845 ps |
| CPU time | 7 seconds |
| Started | Oct 15 09:41:42 AM UTC 24 |
| Finished | Oct 15 09:41:51 AM UTC 24 |
| Peak memory | 258856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236422434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.4236422434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.3339500766 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 829409714 ps |
| CPU time | 6.28 seconds |
| Started | Oct 15 09:41:39 AM UTC 24 |
| Finished | Oct 15 09:41:47 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339500766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3339500766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.1871579644 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 107804637788 ps |
| CPU time | 186.07 seconds |
| Started | Oct 15 09:41:45 AM UTC 24 |
| Finished | Oct 15 09:44:54 AM UTC 24 |
| Peak memory | 322596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871579644 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.1871579644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3732195400 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 15533712985 ps |
| CPU time | 72.72 seconds |
| Started | Oct 15 09:41:45 AM UTC 24 |
| Finished | Oct 15 09:42:59 AM UTC 24 |
| Peak memory | 259044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3732195400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.otp_ctrl_stress_all_with_rand_reset.3732195400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.2912363596 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 19894465453 ps |
| CPU time | 24.72 seconds |
| Started | Oct 15 09:41:43 AM UTC 24 |
| Finished | Oct 15 09:42:09 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912363596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2912363596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3322857835 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 357848138 ps |
| CPU time | 3.3 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:21 AM UTC 24 |
| Peak memory | 254696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322857835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3322857835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.1239830912 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 1833019950 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:24 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239830912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1239830912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.1700531923 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 2614792065 ps |
| CPU time | 4.99 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:23 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700531923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1700531923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1115978845 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 1329164552 ps |
| CPU time | 4.25 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115978845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1115978845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.317361308 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 179557595 ps |
| CPU time | 4.02 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317361308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.317361308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.4026153985 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 154414977 ps |
| CPU time | 4.03 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026153985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.4026153985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3443667526 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 167978264 ps |
| CPU time | 3.31 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:21 AM UTC 24 |
| Peak memory | 254540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443667526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3443667526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.758394424 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 224841753 ps |
| CPU time | 5.12 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:23 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758394424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.758394424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2651246405 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 244099827 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 09:48:17 AM UTC 24 |
| Finished | Oct 15 09:48:22 AM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651246405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2651246405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.3661963245 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 105877360 ps |
| CPU time | 2.06 seconds |
| Started | Oct 15 09:38:04 AM UTC 24 |
| Finished | Oct 15 09:38:07 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661963245 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.3661963245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.2026578727 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5211230756 ps |
| CPU time | 33.48 seconds |
| Started | Oct 15 09:38:00 AM UTC 24 |
| Finished | Oct 15 09:38:35 AM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026578727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2026578727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.1212193152 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2587144369 ps |
| CPU time | 18.88 seconds |
| Started | Oct 15 09:38:02 AM UTC 24 |
| Finished | Oct 15 09:38:22 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212193152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1212193152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.2916098732 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 9063870709 ps |
| CPU time | 19.85 seconds |
| Started | Oct 15 09:38:00 AM UTC 24 |
| Finished | Oct 15 09:38:21 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916098732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2916098732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.946912909 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1385084041 ps |
| CPU time | 5.49 seconds |
| Started | Oct 15 09:37:58 AM UTC 24 |
| Finished | Oct 15 09:38:04 AM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946912909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.946912909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.909150126 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 255604792 ps |
| CPU time | 6.95 seconds |
| Started | Oct 15 09:38:02 AM UTC 24 |
| Finished | Oct 15 09:38:10 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909150126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.909150126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.1101379372 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 727311789 ps |
| CPU time | 19.71 seconds |
| Started | Oct 15 09:38:02 AM UTC 24 |
| Finished | Oct 15 09:38:23 AM UTC 24 |
| Peak memory | 253052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101379372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1101379372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.2899231247 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2390812375 ps |
| CPU time | 11.49 seconds |
| Started | Oct 15 09:38:00 AM UTC 24 |
| Finished | Oct 15 09:38:12 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899231247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2899231247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.1026800380 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2718746820 ps |
| CPU time | 27.18 seconds |
| Started | Oct 15 09:38:00 AM UTC 24 |
| Finished | Oct 15 09:38:28 AM UTC 24 |
| Peak memory | 259304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026800380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1026800380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.736416899 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 191564062 ps |
| CPU time | 7.29 seconds |
| Started | Oct 15 09:38:02 AM UTC 24 |
| Finished | Oct 15 09:38:10 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736416899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.736416899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.2907979621 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 159493004612 ps |
| CPU time | 167.93 seconds |
| Started | Oct 15 09:38:04 AM UTC 24 |
| Finished | Oct 15 09:40:55 AM UTC 24 |
| Peak memory | 289116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907979621 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2907979621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2070744802 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 483869887 ps |
| CPU time | 6.46 seconds |
| Started | Oct 15 09:37:57 AM UTC 24 |
| Finished | Oct 15 09:38:05 AM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070744802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2070744802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2191674177 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1959809218 ps |
| CPU time | 37.29 seconds |
| Started | Oct 15 09:38:02 AM UTC 24 |
| Finished | Oct 15 09:38:41 AM UTC 24 |
| Peak memory | 252800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191674177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2191674177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.1841983550 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 793203474 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:42:00 AM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841983550 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1841983550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1555965056 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 421599989 ps |
| CPU time | 3.98 seconds |
| Started | Oct 15 09:41:50 AM UTC 24 |
| Finished | Oct 15 09:41:55 AM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555965056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1555965056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.2193607877 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1069370224 ps |
| CPU time | 18.21 seconds |
| Started | Oct 15 09:41:50 AM UTC 24 |
| Finished | Oct 15 09:42:10 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193607877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2193607877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.3170118096 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2823627923 ps |
| CPU time | 18.09 seconds |
| Started | Oct 15 09:41:48 AM UTC 24 |
| Finished | Oct 15 09:42:08 AM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170118096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3170118096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.1579409578 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 276131203 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 09:41:45 AM UTC 24 |
| Finished | Oct 15 09:41:50 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579409578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1579409578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.2507156929 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1605303340 ps |
| CPU time | 17.62 seconds |
| Started | Oct 15 09:41:52 AM UTC 24 |
| Finished | Oct 15 09:42:11 AM UTC 24 |
| Peak memory | 257148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507156929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2507156929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.4006091769 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3041229201 ps |
| CPU time | 38.38 seconds |
| Started | Oct 15 09:41:52 AM UTC 24 |
| Finished | Oct 15 09:42:32 AM UTC 24 |
| Peak memory | 255052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006091769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.4006091769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.1212439503 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 725713692 ps |
| CPU time | 5.36 seconds |
| Started | Oct 15 09:41:47 AM UTC 24 |
| Finished | Oct 15 09:41:53 AM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212439503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1212439503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3156495927 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 547054629 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 09:41:46 AM UTC 24 |
| Finished | Oct 15 09:41:59 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156495927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3156495927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.4152744440 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 208346442 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 09:41:45 AM UTC 24 |
| Finished | Oct 15 09:41:51 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152744440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.4152744440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.1238738837 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 12870308498 ps |
| CPU time | 119.31 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:43:56 AM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238738837 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.1238738837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.1066694790 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5014041110 ps |
| CPU time | 133.96 seconds |
| Started | Oct 15 09:41:52 AM UTC 24 |
| Finished | Oct 15 09:44:09 AM UTC 24 |
| Peak memory | 275812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1066694790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.otp_ctrl_stress_all_with_rand_reset.1066694790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.3832132527 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4827270378 ps |
| CPU time | 31.53 seconds |
| Started | Oct 15 09:41:52 AM UTC 24 |
| Finished | Oct 15 09:42:25 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832132527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3832132527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.2613806255 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 77515452 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 09:42:02 AM UTC 24 |
| Finished | Oct 15 09:42:06 AM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613806255 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2613806255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3963968840 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 685229240 ps |
| CPU time | 10.13 seconds |
| Started | Oct 15 09:41:58 AM UTC 24 |
| Finished | Oct 15 09:42:09 AM UTC 24 |
| Peak memory | 254764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963968840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3963968840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.2226702528 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1235993273 ps |
| CPU time | 23.13 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:42:19 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226702528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2226702528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.4218385091 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 12360166938 ps |
| CPU time | 92.09 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:43:29 AM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218385091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.4218385091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.946964176 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2178817203 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:42:01 AM UTC 24 |
| Peak memory | 254808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946964176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.946964176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.3864200473 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5961118060 ps |
| CPU time | 38.37 seconds |
| Started | Oct 15 09:41:58 AM UTC 24 |
| Finished | Oct 15 09:42:38 AM UTC 24 |
| Peak memory | 269228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864200473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3864200473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.1659710141 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1059618475 ps |
| CPU time | 21.63 seconds |
| Started | Oct 15 09:42:01 AM UTC 24 |
| Finished | Oct 15 09:42:24 AM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659710141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1659710141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.931828094 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 11566088654 ps |
| CPU time | 29.56 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:42:26 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931828094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.931828094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.4172916328 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 956538983 ps |
| CPU time | 25.31 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:42:22 AM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172916328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.4172916328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.2918529152 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 299894624 ps |
| CPU time | 11.31 seconds |
| Started | Oct 15 09:42:01 AM UTC 24 |
| Finished | Oct 15 09:42:13 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918529152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2918529152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.1740312667 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 935469804 ps |
| CPU time | 13.75 seconds |
| Started | Oct 15 09:41:55 AM UTC 24 |
| Finished | Oct 15 09:42:10 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740312667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.1740312667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.1154019618 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 27684477431 ps |
| CPU time | 157.58 seconds |
| Started | Oct 15 09:42:01 AM UTC 24 |
| Finished | Oct 15 09:44:41 AM UTC 24 |
| Peak memory | 269224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154019618 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.1154019618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.1740063593 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1042427632 ps |
| CPU time | 10.4 seconds |
| Started | Oct 15 09:42:01 AM UTC 24 |
| Finished | Oct 15 09:42:12 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740063593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1740063593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.1059098613 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 78048949 ps |
| CPU time | 2.56 seconds |
| Started | Oct 15 09:42:15 AM UTC 24 |
| Finished | Oct 15 09:42:18 AM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059098613 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1059098613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.3065672246 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 154624090 ps |
| CPU time | 6.12 seconds |
| Started | Oct 15 09:42:12 AM UTC 24 |
| Finished | Oct 15 09:42:19 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065672246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3065672246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.2766444143 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 334352623 ps |
| CPU time | 22.4 seconds |
| Started | Oct 15 09:42:12 AM UTC 24 |
| Finished | Oct 15 09:42:35 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766444143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2766444143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.350317220 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2921215804 ps |
| CPU time | 27.99 seconds |
| Started | Oct 15 09:42:11 AM UTC 24 |
| Finished | Oct 15 09:42:41 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350317220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.350317220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.3431194033 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 319109609 ps |
| CPU time | 6.82 seconds |
| Started | Oct 15 09:42:06 AM UTC 24 |
| Finished | Oct 15 09:42:14 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431194033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3431194033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.2363691258 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 4593955948 ps |
| CPU time | 15.52 seconds |
| Started | Oct 15 09:42:12 AM UTC 24 |
| Finished | Oct 15 09:42:28 AM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363691258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2363691258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.3582371041 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2115569420 ps |
| CPU time | 6.4 seconds |
| Started | Oct 15 09:42:12 AM UTC 24 |
| Finished | Oct 15 09:42:19 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582371041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3582371041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.2006780072 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 376755817 ps |
| CPU time | 5.18 seconds |
| Started | Oct 15 09:42:09 AM UTC 24 |
| Finished | Oct 15 09:42:15 AM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006780072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2006780072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.4025699021 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 707079703 ps |
| CPU time | 26.49 seconds |
| Started | Oct 15 09:42:07 AM UTC 24 |
| Finished | Oct 15 09:42:35 AM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025699021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.4025699021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.1795455036 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 636344485 ps |
| CPU time | 13.49 seconds |
| Started | Oct 15 09:42:12 AM UTC 24 |
| Finished | Oct 15 09:42:26 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795455036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1795455036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.3320017042 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 272062413 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 09:42:06 AM UTC 24 |
| Finished | Oct 15 09:42:15 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320017042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3320017042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3296781258 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4147152803 ps |
| CPU time | 71.09 seconds |
| Started | Oct 15 09:42:15 AM UTC 24 |
| Finished | Oct 15 09:43:28 AM UTC 24 |
| Peak memory | 269248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3296781258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.otp_ctrl_stress_all_with_rand_reset.3296781258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.3430723530 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 168470657 ps |
| CPU time | 5.75 seconds |
| Started | Oct 15 09:42:15 AM UTC 24 |
| Finished | Oct 15 09:42:22 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430723530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3430723530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.4136086822 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 62240027 ps |
| CPU time | 2.46 seconds |
| Started | Oct 15 09:42:26 AM UTC 24 |
| Finished | Oct 15 09:42:29 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136086822 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.4136086822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.2467240244 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 741318955 ps |
| CPU time | 9.06 seconds |
| Started | Oct 15 09:42:19 AM UTC 24 |
| Finished | Oct 15 09:42:29 AM UTC 24 |
| Peak memory | 259076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467240244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2467240244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.379859173 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 925765094 ps |
| CPU time | 28.09 seconds |
| Started | Oct 15 09:42:19 AM UTC 24 |
| Finished | Oct 15 09:42:49 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379859173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.379859173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3244447304 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1369149000 ps |
| CPU time | 30.92 seconds |
| Started | Oct 15 09:42:18 AM UTC 24 |
| Finished | Oct 15 09:42:50 AM UTC 24 |
| Peak memory | 259024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244447304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3244447304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2800507582 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 316201338 ps |
| CPU time | 6.46 seconds |
| Started | Oct 15 09:42:15 AM UTC 24 |
| Finished | Oct 15 09:42:22 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800507582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2800507582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.1431533017 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3908252438 ps |
| CPU time | 15.38 seconds |
| Started | Oct 15 09:42:21 AM UTC 24 |
| Finished | Oct 15 09:42:37 AM UTC 24 |
| Peak memory | 253164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431533017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1431533017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.358784869 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 3117482921 ps |
| CPU time | 11.05 seconds |
| Started | Oct 15 09:42:21 AM UTC 24 |
| Finished | Oct 15 09:42:33 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358784869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.358784869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.3893849346 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 134435962 ps |
| CPU time | 5.3 seconds |
| Started | Oct 15 09:42:16 AM UTC 24 |
| Finished | Oct 15 09:42:23 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893849346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3893849346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.1061897140 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 906097988 ps |
| CPU time | 21.21 seconds |
| Started | Oct 15 09:42:16 AM UTC 24 |
| Finished | Oct 15 09:42:39 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061897140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1061897140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.2530179959 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 117882046 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 09:42:23 AM UTC 24 |
| Finished | Oct 15 09:42:27 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530179959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2530179959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.4060737745 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 463718912 ps |
| CPU time | 14.43 seconds |
| Started | Oct 15 09:42:15 AM UTC 24 |
| Finished | Oct 15 09:42:31 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060737745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.4060737745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.1202141428 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 9651923516 ps |
| CPU time | 193.61 seconds |
| Started | Oct 15 09:42:24 AM UTC 24 |
| Finished | Oct 15 09:45:41 AM UTC 24 |
| Peak memory | 271324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202141428 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.1202141428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.1628353187 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 11195224772 ps |
| CPU time | 79.49 seconds |
| Started | Oct 15 09:42:24 AM UTC 24 |
| Finished | Oct 15 09:43:45 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1628353187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.otp_ctrl_stress_all_with_rand_reset.1628353187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.4286479909 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 11184587385 ps |
| CPU time | 14.83 seconds |
| Started | Oct 15 09:42:23 AM UTC 24 |
| Finished | Oct 15 09:42:39 AM UTC 24 |
| Peak memory | 254836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286479909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.4286479909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.4257255812 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 208687422 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:44 AM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257255812 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.4257255812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.518920751 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3098779067 ps |
| CPU time | 18.53 seconds |
| Started | Oct 15 09:42:30 AM UTC 24 |
| Finished | Oct 15 09:42:50 AM UTC 24 |
| Peak memory | 254924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518920751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.518920751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.2775751350 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2071545026 ps |
| CPU time | 19.6 seconds |
| Started | Oct 15 09:42:30 AM UTC 24 |
| Finished | Oct 15 09:42:51 AM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775751350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2775751350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.2629309813 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1359900009 ps |
| CPU time | 17.24 seconds |
| Started | Oct 15 09:42:29 AM UTC 24 |
| Finished | Oct 15 09:42:48 AM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629309813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2629309813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.3114439235 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 285183374 ps |
| CPU time | 6.31 seconds |
| Started | Oct 15 09:42:28 AM UTC 24 |
| Finished | Oct 15 09:42:35 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114439235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3114439235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.3495778183 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1244360514 ps |
| CPU time | 9.51 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:52 AM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495778183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3495778183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.2380791280 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1339385874 ps |
| CPU time | 17.96 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:43:00 AM UTC 24 |
| Peak memory | 255152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380791280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2380791280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.1315845278 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1371275633 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 09:42:28 AM UTC 24 |
| Finished | Oct 15 09:42:33 AM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315845278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1315845278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.373034368 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 399510412 ps |
| CPU time | 6.43 seconds |
| Started | Oct 15 09:42:28 AM UTC 24 |
| Finished | Oct 15 09:42:35 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373034368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.373034368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.2564364861 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 267797671 ps |
| CPU time | 6.98 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:49 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564364861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2564364861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1517653027 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 430904817 ps |
| CPU time | 6.32 seconds |
| Started | Oct 15 09:42:28 AM UTC 24 |
| Finished | Oct 15 09:42:35 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517653027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1517653027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.3175631377 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 16549267058 ps |
| CPU time | 160.68 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:45:24 AM UTC 24 |
| Peak memory | 260952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175631377 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.3175631377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.399383705 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4101533025 ps |
| CPU time | 53.11 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:43:36 AM UTC 24 |
| Peak memory | 259360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=399383705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.399383705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.3032706736 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2422239574 ps |
| CPU time | 14.24 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:57 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032706736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3032706736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.76554004 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 63446620 ps |
| CPU time | 2.21 seconds |
| Started | Oct 15 09:42:46 AM UTC 24 |
| Finished | Oct 15 09:42:49 AM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76554004 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.76554004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.3730823760 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 550540173 ps |
| CPU time | 9.92 seconds |
| Started | Oct 15 09:42:42 AM UTC 24 |
| Finished | Oct 15 09:42:53 AM UTC 24 |
| Peak memory | 259048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730823760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3730823760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.1348219656 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 12721845303 ps |
| CPU time | 33.44 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:43:16 AM UTC 24 |
| Peak memory | 254812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348219656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1348219656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.106956678 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 285814225 ps |
| CPU time | 7.7 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:50 AM UTC 24 |
| Peak memory | 253136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106956678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.106956678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.2097919184 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 97738327 ps |
| CPU time | 4.57 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:47 AM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097919184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2097919184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.2929159593 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 4825371643 ps |
| CPU time | 12.56 seconds |
| Started | Oct 15 09:42:42 AM UTC 24 |
| Finished | Oct 15 09:42:55 AM UTC 24 |
| Peak memory | 255276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929159593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2929159593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.4079318714 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 411350763 ps |
| CPU time | 5.52 seconds |
| Started | Oct 15 09:42:42 AM UTC 24 |
| Finished | Oct 15 09:42:48 AM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079318714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.4079318714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.1443882366 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2717730587 ps |
| CPU time | 18.7 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:43:01 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443882366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1443882366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.2005217892 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1397415972 ps |
| CPU time | 13.14 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:56 AM UTC 24 |
| Peak memory | 258888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005217892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2005217892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.496964850 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 214298653 ps |
| CPU time | 4.8 seconds |
| Started | Oct 15 09:42:42 AM UTC 24 |
| Finished | Oct 15 09:42:48 AM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496964850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.496964850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.3559687516 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 268980708 ps |
| CPU time | 10.27 seconds |
| Started | Oct 15 09:42:41 AM UTC 24 |
| Finished | Oct 15 09:42:53 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559687516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3559687516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.3501693318 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 808136688 ps |
| CPU time | 12.56 seconds |
| Started | Oct 15 09:42:46 AM UTC 24 |
| Finished | Oct 15 09:43:00 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501693318 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.3501693318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.23216382 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 40603123247 ps |
| CPU time | 195.73 seconds |
| Started | Oct 15 09:42:46 AM UTC 24 |
| Finished | Oct 15 09:46:05 AM UTC 24 |
| Peak memory | 289848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=23216382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.23216382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.679301451 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 313107870 ps |
| CPU time | 8.14 seconds |
| Started | Oct 15 09:42:42 AM UTC 24 |
| Finished | Oct 15 09:42:51 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679301451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.679301451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.3348947186 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 284741311 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:42:59 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348947186 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3348947186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.1152111074 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 158880908 ps |
| CPU time | 5.57 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:42:59 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152111074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1152111074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.887421395 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 902325896 ps |
| CPU time | 33.74 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:43:28 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887421395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.887421395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.430060404 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2554894464 ps |
| CPU time | 20.14 seconds |
| Started | Oct 15 09:42:49 AM UTC 24 |
| Finished | Oct 15 09:43:10 AM UTC 24 |
| Peak memory | 259088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430060404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.430060404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.196035085 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2236019675 ps |
| CPU time | 5.54 seconds |
| Started | Oct 15 09:42:46 AM UTC 24 |
| Finished | Oct 15 09:42:53 AM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196035085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.196035085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3155397102 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 13092725156 ps |
| CPU time | 36.88 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:43:31 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155397102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3155397102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3440738935 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 264162064 ps |
| CPU time | 6.67 seconds |
| Started | Oct 15 09:42:49 AM UTC 24 |
| Finished | Oct 15 09:42:56 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440738935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3440738935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.859361093 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2051655615 ps |
| CPU time | 6.09 seconds |
| Started | Oct 15 09:42:49 AM UTC 24 |
| Finished | Oct 15 09:42:56 AM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859361093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.859361093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.448195947 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2208989783 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:42:58 AM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448195947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.448195947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.3290098862 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 300472850 ps |
| CPU time | 4.54 seconds |
| Started | Oct 15 09:42:46 AM UTC 24 |
| Finished | Oct 15 09:42:52 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290098862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3290098862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3426363201 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 21292113066 ps |
| CPU time | 249.42 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:47:06 AM UTC 24 |
| Peak memory | 259108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426363201 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3426363201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.3918040929 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2722880860 ps |
| CPU time | 29.73 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:43:24 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918040929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3918040929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3316154738 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 61095522 ps |
| CPU time | 2.54 seconds |
| Started | Oct 15 09:43:01 AM UTC 24 |
| Finished | Oct 15 09:43:05 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316154738 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3316154738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.4110666553 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1226221585 ps |
| CPU time | 9.81 seconds |
| Started | Oct 15 09:42:56 AM UTC 24 |
| Finished | Oct 15 09:43:07 AM UTC 24 |
| Peak memory | 253064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110666553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4110666553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.4097093921 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 791945921 ps |
| CPU time | 26.5 seconds |
| Started | Oct 15 09:42:55 AM UTC 24 |
| Finished | Oct 15 09:43:23 AM UTC 24 |
| Peak memory | 254716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097093921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.4097093921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.531970636 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2425779206 ps |
| CPU time | 39.24 seconds |
| Started | Oct 15 09:42:55 AM UTC 24 |
| Finished | Oct 15 09:43:35 AM UTC 24 |
| Peak memory | 253076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531970636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.531970636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2876300361 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 115001463 ps |
| CPU time | 4.44 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:42:59 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876300361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2876300361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2781119118 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1298148612 ps |
| CPU time | 16.68 seconds |
| Started | Oct 15 09:42:56 AM UTC 24 |
| Finished | Oct 15 09:43:14 AM UTC 24 |
| Peak memory | 255100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781119118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2781119118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.1371368329 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 911255552 ps |
| CPU time | 15.69 seconds |
| Started | Oct 15 09:42:58 AM UTC 24 |
| Finished | Oct 15 09:43:15 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371368329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1371368329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.1133910348 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 743267075 ps |
| CPU time | 15.75 seconds |
| Started | Oct 15 09:42:55 AM UTC 24 |
| Finished | Oct 15 09:43:12 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133910348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1133910348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.3250067574 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 921973138 ps |
| CPU time | 22.18 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:43:17 AM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250067574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3250067574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.1997002966 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 614600709 ps |
| CPU time | 9.15 seconds |
| Started | Oct 15 09:42:58 AM UTC 24 |
| Finished | Oct 15 09:43:09 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997002966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1997002966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.1356831150 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 252291750 ps |
| CPU time | 5.83 seconds |
| Started | Oct 15 09:42:53 AM UTC 24 |
| Finished | Oct 15 09:43:00 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356831150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1356831150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2085729345 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 7607174745 ps |
| CPU time | 74.47 seconds |
| Started | Oct 15 09:43:01 AM UTC 24 |
| Finished | Oct 15 09:44:18 AM UTC 24 |
| Peak memory | 259292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085729345 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.2085729345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.474790410 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4534350672 ps |
| CPU time | 29.39 seconds |
| Started | Oct 15 09:42:58 AM UTC 24 |
| Finished | Oct 15 09:43:29 AM UTC 24 |
| Peak memory | 255180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474790410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.474790410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.399377363 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 728135876 ps |
| CPU time | 2.69 seconds |
| Started | Oct 15 09:43:12 AM UTC 24 |
| Finished | Oct 15 09:43:15 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399377363 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.399377363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.866481951 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1402803995 ps |
| CPU time | 23.34 seconds |
| Started | Oct 15 09:43:09 AM UTC 24 |
| Finished | Oct 15 09:43:34 AM UTC 24 |
| Peak memory | 256904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866481951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.866481951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.455418102 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 585916050 ps |
| CPU time | 16.68 seconds |
| Started | Oct 15 09:43:03 AM UTC 24 |
| Finished | Oct 15 09:43:21 AM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455418102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.455418102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.4063192639 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 273693120 ps |
| CPU time | 11.57 seconds |
| Started | Oct 15 09:43:02 AM UTC 24 |
| Finished | Oct 15 09:43:15 AM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063192639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.4063192639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.1401361935 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 123460446 ps |
| CPU time | 5.57 seconds |
| Started | Oct 15 09:43:01 AM UTC 24 |
| Finished | Oct 15 09:43:08 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401361935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1401361935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.1022750613 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1529452613 ps |
| CPU time | 13.77 seconds |
| Started | Oct 15 09:43:09 AM UTC 24 |
| Finished | Oct 15 09:43:24 AM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022750613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1022750613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.2386992654 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 12401519453 ps |
| CPU time | 25.3 seconds |
| Started | Oct 15 09:43:09 AM UTC 24 |
| Finished | Oct 15 09:43:36 AM UTC 24 |
| Peak memory | 259284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386992654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2386992654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2184340854 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 983251108 ps |
| CPU time | 25.48 seconds |
| Started | Oct 15 09:43:02 AM UTC 24 |
| Finished | Oct 15 09:43:29 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184340854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2184340854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.2150584817 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 356627865 ps |
| CPU time | 12.01 seconds |
| Started | Oct 15 09:43:02 AM UTC 24 |
| Finished | Oct 15 09:43:15 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150584817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2150584817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.2494083497 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 457234777 ps |
| CPU time | 9.69 seconds |
| Started | Oct 15 09:43:09 AM UTC 24 |
| Finished | Oct 15 09:43:20 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494083497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2494083497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3146558812 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 458104465 ps |
| CPU time | 8.93 seconds |
| Started | Oct 15 09:43:01 AM UTC 24 |
| Finished | Oct 15 09:43:12 AM UTC 24 |
| Peak memory | 253048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146558812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3146558812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.3476609899 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 13018210461 ps |
| CPU time | 56.74 seconds |
| Started | Oct 15 09:43:09 AM UTC 24 |
| Finished | Oct 15 09:44:08 AM UTC 24 |
| Peak memory | 256872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476609899 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.3476609899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.284443316 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1116761793 ps |
| CPU time | 24.23 seconds |
| Started | Oct 15 09:43:09 AM UTC 24 |
| Finished | Oct 15 09:43:35 AM UTC 24 |
| Peak memory | 253132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284443316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.284443316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.3000193449 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 846918848 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:43:29 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000193449 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3000193449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.1770101230 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 656419686 ps |
| CPU time | 14.03 seconds |
| Started | Oct 15 09:43:17 AM UTC 24 |
| Finished | Oct 15 09:43:32 AM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770101230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1770101230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1316510317 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1571374090 ps |
| CPU time | 17.97 seconds |
| Started | Oct 15 09:43:17 AM UTC 24 |
| Finished | Oct 15 09:43:36 AM UTC 24 |
| Peak memory | 254676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316510317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1316510317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1084337571 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1358313300 ps |
| CPU time | 28.15 seconds |
| Started | Oct 15 09:43:15 AM UTC 24 |
| Finished | Oct 15 09:43:44 AM UTC 24 |
| Peak memory | 259152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084337571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1084337571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2732784917 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 175346471 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 09:43:12 AM UTC 24 |
| Finished | Oct 15 09:43:17 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732784917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2732784917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.179126543 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1096382070 ps |
| CPU time | 14.86 seconds |
| Started | Oct 15 09:43:17 AM UTC 24 |
| Finished | Oct 15 09:43:33 AM UTC 24 |
| Peak memory | 254800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179126543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.179126543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.1231846975 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2103189742 ps |
| CPU time | 6.84 seconds |
| Started | Oct 15 09:43:17 AM UTC 24 |
| Finished | Oct 15 09:43:25 AM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231846975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1231846975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.1914259863 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3892684492 ps |
| CPU time | 25.65 seconds |
| Started | Oct 15 09:43:13 AM UTC 24 |
| Finished | Oct 15 09:43:41 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914259863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1914259863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.147959200 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 639471087 ps |
| CPU time | 10.76 seconds |
| Started | Oct 15 09:43:13 AM UTC 24 |
| Finished | Oct 15 09:43:26 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147959200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.147959200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.2841956819 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 554564312 ps |
| CPU time | 10.82 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:43:36 AM UTC 24 |
| Peak memory | 258856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841956819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.2841956819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.1722672573 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 494739795 ps |
| CPU time | 8.61 seconds |
| Started | Oct 15 09:43:12 AM UTC 24 |
| Finished | Oct 15 09:43:21 AM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722672573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1722672573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3652415360 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 7687934616 ps |
| CPU time | 115.86 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:45:22 AM UTC 24 |
| Peak memory | 275812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3652415360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.otp_ctrl_stress_all_with_rand_reset.3652415360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.4062885131 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 967516987 ps |
| CPU time | 14.98 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:43:40 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062885131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.4062885131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1053763293 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3504317451 ps |
| CPU time | 6.64 seconds |
| Started | Oct 15 09:38:06 AM UTC 24 |
| Finished | Oct 15 09:38:13 AM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053763293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1053763293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.1714842928 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 372693290 ps |
| CPU time | 11.75 seconds |
| Started | Oct 15 09:38:09 AM UTC 24 |
| Finished | Oct 15 09:38:22 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714842928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1714842928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.3715084709 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3462923216 ps |
| CPU time | 10.99 seconds |
| Started | Oct 15 09:38:11 AM UTC 24 |
| Finished | Oct 15 09:38:23 AM UTC 24 |
| Peak memory | 253072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715084709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3715084709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.2659982671 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 283280530 ps |
| CPU time | 7.26 seconds |
| Started | Oct 15 09:38:07 AM UTC 24 |
| Finished | Oct 15 09:38:15 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659982671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2659982671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.532161179 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 236660752 ps |
| CPU time | 3.86 seconds |
| Started | Oct 15 09:38:11 AM UTC 24 |
| Finished | Oct 15 09:38:16 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532161179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.532161179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.375211444 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 21816218011 ps |
| CPU time | 216.19 seconds |
| Started | Oct 15 09:38:13 AM UTC 24 |
| Finished | Oct 15 09:41:52 AM UTC 24 |
| Peak memory | 295320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375211444 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.375211444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.381601343 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1473046818 ps |
| CPU time | 7.08 seconds |
| Started | Oct 15 09:38:06 AM UTC 24 |
| Finished | Oct 15 09:38:14 AM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381601343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.381601343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.662264210 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2264931854 ps |
| CPU time | 22.09 seconds |
| Started | Oct 15 09:38:11 AM UTC 24 |
| Finished | Oct 15 09:38:34 AM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662264210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.662264210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.2221060711 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 51419682 ps |
| CPU time | 2.61 seconds |
| Started | Oct 15 09:43:32 AM UTC 24 |
| Finished | Oct 15 09:43:35 AM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221060711 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2221060711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.210439593 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1302288071 ps |
| CPU time | 11.43 seconds |
| Started | Oct 15 09:43:27 AM UTC 24 |
| Finished | Oct 15 09:43:39 AM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210439593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.210439593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.925156157 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2258155206 ps |
| CPU time | 17.11 seconds |
| Started | Oct 15 09:43:27 AM UTC 24 |
| Finished | Oct 15 09:43:45 AM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925156157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.925156157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.4269876991 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1883951543 ps |
| CPU time | 22.81 seconds |
| Started | Oct 15 09:43:27 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269876991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.4269876991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.4000283917 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 253335315 ps |
| CPU time | 5.74 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:43:31 AM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000283917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.4000283917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.3494659722 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5288678398 ps |
| CPU time | 32.61 seconds |
| Started | Oct 15 09:43:27 AM UTC 24 |
| Finished | Oct 15 09:44:01 AM UTC 24 |
| Peak memory | 259196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494659722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3494659722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.1362499302 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3595643120 ps |
| CPU time | 27.62 seconds |
| Started | Oct 15 09:43:31 AM UTC 24 |
| Finished | Oct 15 09:44:00 AM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362499302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1362499302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.2870894925 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2275610843 ps |
| CPU time | 6.84 seconds |
| Started | Oct 15 09:43:25 AM UTC 24 |
| Finished | Oct 15 09:43:32 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870894925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2870894925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.3224150599 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 410757179 ps |
| CPU time | 8.01 seconds |
| Started | Oct 15 09:43:25 AM UTC 24 |
| Finished | Oct 15 09:43:34 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224150599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3224150599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.3099012556 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3619629957 ps |
| CPU time | 12.89 seconds |
| Started | Oct 15 09:43:31 AM UTC 24 |
| Finished | Oct 15 09:43:46 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099012556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3099012556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3681500616 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1472482309 ps |
| CPU time | 10.31 seconds |
| Started | Oct 15 09:43:24 AM UTC 24 |
| Finished | Oct 15 09:43:36 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681500616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3681500616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.3183649048 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 8426367087 ps |
| CPU time | 151.58 seconds |
| Started | Oct 15 09:43:32 AM UTC 24 |
| Finished | Oct 15 09:46:06 AM UTC 24 |
| Peak memory | 269532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183649048 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.3183649048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1245946440 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1125578115 ps |
| CPU time | 30.62 seconds |
| Started | Oct 15 09:43:31 AM UTC 24 |
| Finished | Oct 15 09:44:04 AM UTC 24 |
| Peak memory | 269528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1245946440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.otp_ctrl_stress_all_with_rand_reset.1245946440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2861302543 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 10470639665 ps |
| CPU time | 24.75 seconds |
| Started | Oct 15 09:43:31 AM UTC 24 |
| Finished | Oct 15 09:43:57 AM UTC 24 |
| Peak memory | 254716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861302543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2861302543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.759173341 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 68237910 ps |
| CPU time | 2.9 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:43 AM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759173341 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.759173341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.3439518071 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 856800745 ps |
| CPU time | 10.52 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439518071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3439518071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1946986983 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5656377467 ps |
| CPU time | 21.74 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:44:02 AM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946986983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1946986983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.3529344190 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1379052817 ps |
| CPU time | 22.34 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:44:02 AM UTC 24 |
| Peak memory | 253072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529344190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3529344190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.2575637975 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2412413054 ps |
| CPU time | 34.94 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:44:15 AM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575637975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2575637975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.851845856 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 806369217 ps |
| CPU time | 21.6 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:44:02 AM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851845856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.851845856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.3300161900 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 199377334 ps |
| CPU time | 13.95 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:54 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300161900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3300161900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.4122263240 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2266306505 ps |
| CPU time | 17.63 seconds |
| Started | Oct 15 09:43:32 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122263240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.4122263240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.1688909683 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 112199560 ps |
| CPU time | 4.23 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:44 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688909683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1688909683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.3915404118 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1251569957 ps |
| CPU time | 9.94 seconds |
| Started | Oct 15 09:43:32 AM UTC 24 |
| Finished | Oct 15 09:43:43 AM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915404118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3915404118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.3360888720 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 21674687114 ps |
| CPU time | 133.71 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:45:55 AM UTC 24 |
| Peak memory | 256856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360888720 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.3360888720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.4108174042 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 50393414745 ps |
| CPU time | 122.16 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:45:44 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4108174042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.otp_ctrl_stress_all_with_rand_reset.4108174042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.2475903585 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3822998419 ps |
| CPU time | 22.77 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:44:03 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475903585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2475903585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.2498748961 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 666796878 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 09:43:47 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498748961 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2498748961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.3078909017 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1364005015 ps |
| CPU time | 26.28 seconds |
| Started | Oct 15 09:43:41 AM UTC 24 |
| Finished | Oct 15 09:44:09 AM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078909017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3078909017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.332515811 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5742538790 ps |
| CPU time | 30.93 seconds |
| Started | Oct 15 09:43:40 AM UTC 24 |
| Finished | Oct 15 09:44:12 AM UTC 24 |
| Peak memory | 252736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332515811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.332515811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.3005903393 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 700528988 ps |
| CPU time | 11.96 seconds |
| Started | Oct 15 09:43:40 AM UTC 24 |
| Finished | Oct 15 09:43:53 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005903393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3005903393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.4034575272 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 559088053 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:45 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034575272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4034575272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.1705875906 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3145300926 ps |
| CPU time | 24.82 seconds |
| Started | Oct 15 09:43:41 AM UTC 24 |
| Finished | Oct 15 09:44:07 AM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705875906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1705875906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.3321534485 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 335570399 ps |
| CPU time | 8.39 seconds |
| Started | Oct 15 09:43:41 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321534485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3321534485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.3565191407 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 193289770 ps |
| CPU time | 7.59 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:48 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565191407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.3565191407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.3795430072 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1226492855 ps |
| CPU time | 10.84 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795430072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3795430072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.81056228 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 157173989 ps |
| CPU time | 5.4 seconds |
| Started | Oct 15 09:43:43 AM UTC 24 |
| Finished | Oct 15 09:43:49 AM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81056228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.81056228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.1434990150 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 501404916 ps |
| CPU time | 5.96 seconds |
| Started | Oct 15 09:43:39 AM UTC 24 |
| Finished | Oct 15 09:43:46 AM UTC 24 |
| Peak memory | 258848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434990150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1434990150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.1775716673 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 15191877595 ps |
| CPU time | 117.77 seconds |
| Started | Oct 15 09:43:47 AM UTC 24 |
| Finished | Oct 15 09:45:47 AM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775716673 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.1775716673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.1262777254 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 6299603879 ps |
| CPU time | 117.63 seconds |
| Started | Oct 15 09:43:44 AM UTC 24 |
| Finished | Oct 15 09:45:44 AM UTC 24 |
| Peak memory | 269668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1262777254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.otp_ctrl_stress_all_with_rand_reset.1262777254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.3499884211 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 364216829 ps |
| CPU time | 11.83 seconds |
| Started | Oct 15 09:43:44 AM UTC 24 |
| Finished | Oct 15 09:43:57 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499884211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3499884211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.1450335723 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 204953948 ps |
| CPU time | 4.49 seconds |
| Started | Oct 15 09:43:54 AM UTC 24 |
| Finished | Oct 15 09:43:59 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450335723 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1450335723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.1321597338 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1087521576 ps |
| CPU time | 22 seconds |
| Started | Oct 15 09:43:50 AM UTC 24 |
| Finished | Oct 15 09:44:14 AM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321597338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1321597338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.2537317447 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 12399206661 ps |
| CPU time | 26.48 seconds |
| Started | Oct 15 09:43:50 AM UTC 24 |
| Finished | Oct 15 09:44:18 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537317447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2537317447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.4216244042 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1185965893 ps |
| CPU time | 14.83 seconds |
| Started | Oct 15 09:43:50 AM UTC 24 |
| Finished | Oct 15 09:44:06 AM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216244042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.4216244042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.505408632 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 142909197 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 09:43:47 AM UTC 24 |
| Finished | Oct 15 09:43:51 AM UTC 24 |
| Peak memory | 254704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505408632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.505408632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.1246335104 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2144642796 ps |
| CPU time | 24.7 seconds |
| Started | Oct 15 09:43:50 AM UTC 24 |
| Finished | Oct 15 09:44:16 AM UTC 24 |
| Peak memory | 259180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246335104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1246335104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.1475229368 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 218315771 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 09:43:53 AM UTC 24 |
| Finished | Oct 15 09:44:02 AM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475229368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1475229368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.2406770013 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 474104919 ps |
| CPU time | 10.54 seconds |
| Started | Oct 15 09:43:50 AM UTC 24 |
| Finished | Oct 15 09:44:02 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406770013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2406770013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.1024552626 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5100030640 ps |
| CPU time | 14.07 seconds |
| Started | Oct 15 09:43:47 AM UTC 24 |
| Finished | Oct 15 09:44:02 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024552626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1024552626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.1712157656 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 308499854 ps |
| CPU time | 12 seconds |
| Started | Oct 15 09:43:53 AM UTC 24 |
| Finished | Oct 15 09:44:06 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712157656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1712157656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.4239986423 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 184238377 ps |
| CPU time | 5.12 seconds |
| Started | Oct 15 09:43:47 AM UTC 24 |
| Finished | Oct 15 09:43:53 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239986423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4239986423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.313915720 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4787305362 ps |
| CPU time | 70.13 seconds |
| Started | Oct 15 09:43:53 AM UTC 24 |
| Finished | Oct 15 09:45:05 AM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313915720 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.313915720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.1201279261 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2125231821 ps |
| CPU time | 38.34 seconds |
| Started | Oct 15 09:43:53 AM UTC 24 |
| Finished | Oct 15 09:44:33 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201279261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1201279261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.3824134101 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 229780662 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:11 AM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824134101 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3824134101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.1219222803 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 987659367 ps |
| CPU time | 13.23 seconds |
| Started | Oct 15 09:44:00 AM UTC 24 |
| Finished | Oct 15 09:44:14 AM UTC 24 |
| Peak memory | 259156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219222803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1219222803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.3698585471 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1170583842 ps |
| CPU time | 25.89 seconds |
| Started | Oct 15 09:44:00 AM UTC 24 |
| Finished | Oct 15 09:44:27 AM UTC 24 |
| Peak memory | 254860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698585471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3698585471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.17663511 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1887335716 ps |
| CPU time | 17.16 seconds |
| Started | Oct 15 09:43:55 AM UTC 24 |
| Finished | Oct 15 09:44:13 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17663511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.17663511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.2632615967 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 107121130 ps |
| CPU time | 6.17 seconds |
| Started | Oct 15 09:43:54 AM UTC 24 |
| Finished | Oct 15 09:44:01 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632615967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2632615967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.2672706151 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 6853026256 ps |
| CPU time | 25.62 seconds |
| Started | Oct 15 09:44:00 AM UTC 24 |
| Finished | Oct 15 09:44:27 AM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672706151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2672706151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.225577593 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1931685309 ps |
| CPU time | 27.11 seconds |
| Started | Oct 15 09:44:00 AM UTC 24 |
| Finished | Oct 15 09:44:28 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225577593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.225577593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.2230832337 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 161508373 ps |
| CPU time | 8.44 seconds |
| Started | Oct 15 09:43:54 AM UTC 24 |
| Finished | Oct 15 09:44:03 AM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230832337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.2230832337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.2636333708 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1718760562 ps |
| CPU time | 20.73 seconds |
| Started | Oct 15 09:43:54 AM UTC 24 |
| Finished | Oct 15 09:44:16 AM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636333708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2636333708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.4200707541 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1095896415 ps |
| CPU time | 8.64 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:17 AM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200707541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.4200707541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.3981424041 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 305493048 ps |
| CPU time | 9.27 seconds |
| Started | Oct 15 09:43:54 AM UTC 24 |
| Finished | Oct 15 09:44:04 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981424041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3981424041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.433910652 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 64446567999 ps |
| CPU time | 551.93 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:53:26 AM UTC 24 |
| Peak memory | 285884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433910652 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.433910652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2594562110 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2507020203 ps |
| CPU time | 87.63 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:45:37 AM UTC 24 |
| Peak memory | 269380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2594562110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.otp_ctrl_stress_all_with_rand_reset.2594562110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.3978373381 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 559266699 ps |
| CPU time | 12.76 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:21 AM UTC 24 |
| Peak memory | 252572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978373381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3978373381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3058218745 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 837755453 ps |
| CPU time | 2.9 seconds |
| Started | Oct 15 09:44:13 AM UTC 24 |
| Finished | Oct 15 09:44:17 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058218745 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3058218745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.3568002033 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 17960386579 ps |
| CPU time | 26.68 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:35 AM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568002033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3568002033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.3195112383 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 12939171828 ps |
| CPU time | 42.34 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:51 AM UTC 24 |
| Peak memory | 256972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195112383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.3195112383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.1934853991 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 24196401073 ps |
| CPU time | 44.65 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:53 AM UTC 24 |
| Peak memory | 259020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934853991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1934853991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.145441578 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1264904768 ps |
| CPU time | 7.04 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:15 AM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145441578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.145441578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.2013830111 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 8661488214 ps |
| CPU time | 43.35 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:52 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013830111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2013830111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.3023394827 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 304858847 ps |
| CPU time | 13.54 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:22 AM UTC 24 |
| Peak memory | 254932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023394827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3023394827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3883197793 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 343827255 ps |
| CPU time | 6.35 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:15 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883197793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3883197793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.287282333 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 413870106 ps |
| CPU time | 8.7 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:17 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287282333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.287282333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.1553275007 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 209768219 ps |
| CPU time | 4.8 seconds |
| Started | Oct 15 09:44:12 AM UTC 24 |
| Finished | Oct 15 09:44:18 AM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553275007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1553275007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3227935053 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1432545583 ps |
| CPU time | 19.6 seconds |
| Started | Oct 15 09:44:07 AM UTC 24 |
| Finished | Oct 15 09:44:28 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227935053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3227935053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.3528594797 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 47715193862 ps |
| CPU time | 248.85 seconds |
| Started | Oct 15 09:44:13 AM UTC 24 |
| Finished | Oct 15 09:48:25 AM UTC 24 |
| Peak memory | 295976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528594797 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.3528594797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.4048493929 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 694783555 ps |
| CPU time | 11.2 seconds |
| Started | Oct 15 09:44:12 AM UTC 24 |
| Finished | Oct 15 09:44:25 AM UTC 24 |
| Peak memory | 255148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048493929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4048493929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.3312675901 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 56000297 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:24 AM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312675901 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3312675901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.2320870537 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 6994431906 ps |
| CPU time | 17.67 seconds |
| Started | Oct 15 09:44:16 AM UTC 24 |
| Finished | Oct 15 09:44:35 AM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320870537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2320870537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.915470135 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1794581016 ps |
| CPU time | 13.9 seconds |
| Started | Oct 15 09:44:16 AM UTC 24 |
| Finished | Oct 15 09:44:31 AM UTC 24 |
| Peak memory | 254676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915470135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.915470135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.240320859 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 489061724 ps |
| CPU time | 10.97 seconds |
| Started | Oct 15 09:44:16 AM UTC 24 |
| Finished | Oct 15 09:44:28 AM UTC 24 |
| Peak memory | 253076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240320859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.240320859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.3794618259 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 510003138 ps |
| CPU time | 4.79 seconds |
| Started | Oct 15 09:44:13 AM UTC 24 |
| Finished | Oct 15 09:44:19 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794618259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3794618259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.2064415643 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1368064389 ps |
| CPU time | 7.12 seconds |
| Started | Oct 15 09:44:16 AM UTC 24 |
| Finished | Oct 15 09:44:25 AM UTC 24 |
| Peak memory | 259216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064415643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2064415643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1692751885 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 286335976 ps |
| CPU time | 7.28 seconds |
| Started | Oct 15 09:44:16 AM UTC 24 |
| Finished | Oct 15 09:44:25 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692751885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1692751885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.3789174882 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 216395143 ps |
| CPU time | 9.79 seconds |
| Started | Oct 15 09:44:16 AM UTC 24 |
| Finished | Oct 15 09:44:27 AM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789174882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3789174882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.3544702816 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 423269242 ps |
| CPU time | 7.85 seconds |
| Started | Oct 15 09:44:13 AM UTC 24 |
| Finished | Oct 15 09:44:22 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544702816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3544702816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.2477275047 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3177974546 ps |
| CPU time | 9.62 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:31 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477275047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2477275047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1790400079 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 994075570 ps |
| CPU time | 15.05 seconds |
| Started | Oct 15 09:44:13 AM UTC 24 |
| Finished | Oct 15 09:44:29 AM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790400079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1790400079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2161377076 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 16172202093 ps |
| CPU time | 37.71 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:59 AM UTC 24 |
| Peak memory | 254752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161377076 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.2161377076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.3052520888 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5917071377 ps |
| CPU time | 31.63 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:53 AM UTC 24 |
| Peak memory | 254324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052520888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3052520888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.4185563073 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 192775199 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:44:35 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185563073 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.4185563073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1829753587 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 798079646 ps |
| CPU time | 11.84 seconds |
| Started | Oct 15 09:44:26 AM UTC 24 |
| Finished | Oct 15 09:44:38 AM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829753587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1829753587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.2774368945 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 358066114 ps |
| CPU time | 9.21 seconds |
| Started | Oct 15 09:44:26 AM UTC 24 |
| Finished | Oct 15 09:44:36 AM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774368945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2774368945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.1209317890 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2610632197 ps |
| CPU time | 27.34 seconds |
| Started | Oct 15 09:44:25 AM UTC 24 |
| Finished | Oct 15 09:44:54 AM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209317890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1209317890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.745181391 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 110420374 ps |
| CPU time | 5.61 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:27 AM UTC 24 |
| Peak memory | 255124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745181391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.745181391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.3680968877 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 19130082968 ps |
| CPU time | 106.37 seconds |
| Started | Oct 15 09:44:26 AM UTC 24 |
| Finished | Oct 15 09:46:14 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680968877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3680968877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.3959839715 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 190178629 ps |
| CPU time | 5.3 seconds |
| Started | Oct 15 09:44:26 AM UTC 24 |
| Finished | Oct 15 09:44:32 AM UTC 24 |
| Peak memory | 259124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959839715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3959839715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.3847151947 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 229832398 ps |
| CPU time | 5.13 seconds |
| Started | Oct 15 09:44:25 AM UTC 24 |
| Finished | Oct 15 09:44:32 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847151947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.3847151947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.2042116693 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 967401929 ps |
| CPU time | 10.77 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:32 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042116693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2042116693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.2708713892 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 302414282 ps |
| CPU time | 9.45 seconds |
| Started | Oct 15 09:44:26 AM UTC 24 |
| Finished | Oct 15 09:44:36 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708713892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2708713892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.2690850080 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 827227562 ps |
| CPU time | 14.66 seconds |
| Started | Oct 15 09:44:20 AM UTC 24 |
| Finished | Oct 15 09:44:36 AM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690850080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.2690850080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1147857918 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 48339649004 ps |
| CPU time | 256.17 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:48:50 AM UTC 24 |
| Peak memory | 308200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147857918 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.1147857918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.3013047047 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 6367610278 ps |
| CPU time | 19.39 seconds |
| Started | Oct 15 09:44:26 AM UTC 24 |
| Finished | Oct 15 09:44:46 AM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013047047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3013047047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.462396515 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 175214615 ps |
| CPU time | 2.71 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:42 AM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462396515 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.462396515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.1052706303 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 886775581 ps |
| CPU time | 16.03 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:55 AM UTC 24 |
| Peak memory | 254800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052706303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1052706303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.1528598485 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 2156870300 ps |
| CPU time | 28.61 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:45:00 AM UTC 24 |
| Peak memory | 254992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528598485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1528598485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.1603750006 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 31694623654 ps |
| CPU time | 238 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:48:31 AM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603750006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1603750006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.2599009252 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1910097541 ps |
| CPU time | 7.79 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:44:39 AM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599009252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2599009252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.568402688 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4739305829 ps |
| CPU time | 22.36 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:45:02 AM UTC 24 |
| Peak memory | 256988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568402688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.568402688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.2240837953 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 948084357 ps |
| CPU time | 27.52 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:45:07 AM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240837953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2240837953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.1788029697 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 186034890 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:44:39 AM UTC 24 |
| Peak memory | 252932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788029697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1788029697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.1431580819 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1272967432 ps |
| CPU time | 20.45 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:44:52 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431580819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1431580819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.2124680348 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 715007436 ps |
| CPU time | 6.8 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:46 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124680348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2124680348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.4122785969 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1051218631 ps |
| CPU time | 11.37 seconds |
| Started | Oct 15 09:44:30 AM UTC 24 |
| Finished | Oct 15 09:44:42 AM UTC 24 |
| Peak memory | 258932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122785969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.4122785969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.460537713 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 72976827081 ps |
| CPU time | 113.33 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:46:34 AM UTC 24 |
| Peak memory | 263176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460537713 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.460537713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.1093642702 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 9316944715 ps |
| CPU time | 79.19 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:46:00 AM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1093642702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.1093642702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.2726207878 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 387913576 ps |
| CPU time | 9.27 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:49 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726207878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2726207878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.1526720823 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 655246239 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:55 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526720823 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1526720823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.614772179 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1996032908 ps |
| CPU time | 17.4 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:10 AM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614772179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.614772179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.1708336313 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 14292000159 ps |
| CPU time | 45.6 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:38 AM UTC 24 |
| Peak memory | 256780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708336313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1708336313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.3828744081 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1522196457 ps |
| CPU time | 23.48 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:16 AM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828744081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3828744081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.756813308 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 165357714 ps |
| CPU time | 5.85 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:46 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756813308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.756813308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.1324197729 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 233270372 ps |
| CPU time | 6.65 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:59 AM UTC 24 |
| Peak memory | 253164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324197729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1324197729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.149890728 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 5334975637 ps |
| CPU time | 21.2 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:14 AM UTC 24 |
| Peak memory | 259148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149890728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.149890728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.2282627368 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 258082359 ps |
| CPU time | 7.34 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:59 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282627368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2282627368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2228711557 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 732418338 ps |
| CPU time | 7.07 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:47 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228711557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2228711557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.2785044330 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 284313062 ps |
| CPU time | 5.5 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:58 AM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785044330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2785044330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.734544461 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 337522098 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 09:44:38 AM UTC 24 |
| Finished | Oct 15 09:44:46 AM UTC 24 |
| Peak memory | 252800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734544461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.734544461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.2550850730 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 22243937004 ps |
| CPU time | 122.76 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:46:56 AM UTC 24 |
| Peak memory | 269604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550850730 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.2550850730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.238945025 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 8798570511 ps |
| CPU time | 102.96 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:46:36 AM UTC 24 |
| Peak memory | 269300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=238945025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.238945025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.423668361 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 296670261 ps |
| CPU time | 9.03 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:01 AM UTC 24 |
| Peak memory | 254920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423668361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.423668361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.2638030214 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 187200447 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 09:38:25 AM UTC 24 |
| Finished | Oct 15 09:38:29 AM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638030214 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2638030214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.1823283976 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1006606850 ps |
| CPU time | 9.01 seconds |
| Started | Oct 15 09:38:14 AM UTC 24 |
| Finished | Oct 15 09:38:24 AM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823283976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1823283976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3116449131 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 6383412382 ps |
| CPU time | 36.96 seconds |
| Started | Oct 15 09:38:18 AM UTC 24 |
| Finished | Oct 15 09:38:56 AM UTC 24 |
| Peak memory | 259248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116449131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3116449131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.3323811194 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 729456589 ps |
| CPU time | 27.75 seconds |
| Started | Oct 15 09:38:17 AM UTC 24 |
| Finished | Oct 15 09:38:46 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323811194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3323811194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.2917010867 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2188217836 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 09:38:14 AM UTC 24 |
| Finished | Oct 15 09:38:23 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917010867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2917010867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.440941213 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1039384019 ps |
| CPU time | 15.22 seconds |
| Started | Oct 15 09:38:21 AM UTC 24 |
| Finished | Oct 15 09:38:37 AM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440941213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.440941213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.3232590485 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1042429622 ps |
| CPU time | 12.86 seconds |
| Started | Oct 15 09:38:21 AM UTC 24 |
| Finished | Oct 15 09:38:35 AM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232590485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3232590485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.1609178301 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 997378625 ps |
| CPU time | 9.57 seconds |
| Started | Oct 15 09:38:16 AM UTC 24 |
| Finished | Oct 15 09:38:26 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609178301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1609178301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.4083224948 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 176428675 ps |
| CPU time | 7.52 seconds |
| Started | Oct 15 09:38:23 AM UTC 24 |
| Finished | Oct 15 09:38:31 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083224948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.4083224948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1387294372 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 258551459 ps |
| CPU time | 8.46 seconds |
| Started | Oct 15 09:38:14 AM UTC 24 |
| Finished | Oct 15 09:38:24 AM UTC 24 |
| Peak memory | 258812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387294372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1387294372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1023572927 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 60412857320 ps |
| CPU time | 252.36 seconds |
| Started | Oct 15 09:38:23 AM UTC 24 |
| Finished | Oct 15 09:42:39 AM UTC 24 |
| Peak memory | 275548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1023572927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.otp_ctrl_stress_all_with_rand_reset.1023572927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.3246883021 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 14366830410 ps |
| CPU time | 44.21 seconds |
| Started | Oct 15 09:38:23 AM UTC 24 |
| Finished | Oct 15 09:39:09 AM UTC 24 |
| Peak memory | 254924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246883021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3246883021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.3387720495 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 197920138 ps |
| CPU time | 5.77 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:58 AM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387720495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3387720495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.695748061 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 196868467 ps |
| CPU time | 5.53 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:58 AM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695748061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.695748061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3443855581 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2816938404 ps |
| CPU time | 83.03 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:46:17 AM UTC 24 |
| Peak memory | 275784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3443855581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.3443855581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.3632781490 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2848784737 ps |
| CPU time | 10.22 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:03 AM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632781490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3632781490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.2200792311 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 597461022 ps |
| CPU time | 6.22 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:59 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200792311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2200792311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.2343096033 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 148770834 ps |
| CPU time | 4.16 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:44:57 AM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343096033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2343096033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.1938378813 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 506369849 ps |
| CPU time | 8.29 seconds |
| Started | Oct 15 09:44:51 AM UTC 24 |
| Finished | Oct 15 09:45:01 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938378813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1938378813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.663572102 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 46179220537 ps |
| CPU time | 147.03 seconds |
| Started | Oct 15 09:44:54 AM UTC 24 |
| Finished | Oct 15 09:47:24 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=663572102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.663572102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.2735959291 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 320376012 ps |
| CPU time | 5.1 seconds |
| Started | Oct 15 09:44:54 AM UTC 24 |
| Finished | Oct 15 09:45:00 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735959291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2735959291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.2954487039 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 195060461 ps |
| CPU time | 6.23 seconds |
| Started | Oct 15 09:44:54 AM UTC 24 |
| Finished | Oct 15 09:45:01 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954487039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2954487039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.2840446977 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 7361649522 ps |
| CPU time | 119.29 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:47:00 AM UTC 24 |
| Peak memory | 269336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2840446977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 53.otp_ctrl_stress_all_with_rand_reset.2840446977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.447534857 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 455352754 ps |
| CPU time | 5.11 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:45:05 AM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447534857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.447534857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.642238171 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 560431217 ps |
| CPU time | 4.44 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:45:05 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642238171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.642238171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.2331050251 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 432437332 ps |
| CPU time | 3.42 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:45:04 AM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331050251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2331050251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2581333905 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1259892587 ps |
| CPU time | 8.49 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:45:09 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581333905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2581333905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.2415169459 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 20244440766 ps |
| CPU time | 95.52 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:46:37 AM UTC 24 |
| Peak memory | 269576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2415169459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 55.otp_ctrl_stress_all_with_rand_reset.2415169459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.2536549847 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 162621691 ps |
| CPU time | 5.91 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:45:06 AM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536549847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2536549847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.2107224741 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2246297192 ps |
| CPU time | 11.7 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:45:12 AM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107224741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2107224741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1581178699 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1994279214 ps |
| CPU time | 68.05 seconds |
| Started | Oct 15 09:44:59 AM UTC 24 |
| Finished | Oct 15 09:46:09 AM UTC 24 |
| Peak memory | 269344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1581178699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 56.otp_ctrl_stress_all_with_rand_reset.1581178699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.3021279588 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 108924628 ps |
| CPU time | 5.13 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:09 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021279588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3021279588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.3188695842 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 10565136256 ps |
| CPU time | 25.99 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:30 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188695842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3188695842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.94373699 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 6692339198 ps |
| CPU time | 39.87 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:44 AM UTC 24 |
| Peak memory | 269672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=94373699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.94373699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.1553491724 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1766691256 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:10 AM UTC 24 |
| Peak memory | 252976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553491724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1553491724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.3846156391 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 162427288 ps |
| CPU time | 4.77 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:09 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846156391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3846156391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1221706969 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4940425663 ps |
| CPU time | 85.04 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:46:30 AM UTC 24 |
| Peak memory | 269272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1221706969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 58.otp_ctrl_stress_all_with_rand_reset.1221706969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.3235430781 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2878485040 ps |
| CPU time | 7.77 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:12 AM UTC 24 |
| Peak memory | 253048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235430781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3235430781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.2702991658 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2278778802 ps |
| CPU time | 12.27 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:45:16 AM UTC 24 |
| Peak memory | 252996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702991658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2702991658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3003645075 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 27745128428 ps |
| CPU time | 178.35 seconds |
| Started | Oct 15 09:45:03 AM UTC 24 |
| Finished | Oct 15 09:48:04 AM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3003645075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 59.otp_ctrl_stress_all_with_rand_reset.3003645075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.952018254 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 662350911 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 09:38:32 AM UTC 24 |
| Finished | Oct 15 09:38:36 AM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952018254 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.952018254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.47215910 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 828987827 ps |
| CPU time | 9.2 seconds |
| Started | Oct 15 09:38:25 AM UTC 24 |
| Finished | Oct 15 09:38:36 AM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47215910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.47215910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.1796364226 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 828083024 ps |
| CPU time | 10.59 seconds |
| Started | Oct 15 09:38:28 AM UTC 24 |
| Finished | Oct 15 09:38:39 AM UTC 24 |
| Peak memory | 252976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796364226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1796364226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.2217675132 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 838585103 ps |
| CPU time | 11.83 seconds |
| Started | Oct 15 09:38:28 AM UTC 24 |
| Finished | Oct 15 09:38:41 AM UTC 24 |
| Peak memory | 252668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217675132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2217675132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.1024697934 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3503230613 ps |
| CPU time | 9.72 seconds |
| Started | Oct 15 09:38:26 AM UTC 24 |
| Finished | Oct 15 09:38:37 AM UTC 24 |
| Peak memory | 259052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024697934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1024697934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.48807472 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1236153659 ps |
| CPU time | 12.58 seconds |
| Started | Oct 15 09:38:29 AM UTC 24 |
| Finished | Oct 15 09:38:43 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48807472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.48807472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.2640480432 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 565440355 ps |
| CPU time | 11.1 seconds |
| Started | Oct 15 09:38:26 AM UTC 24 |
| Finished | Oct 15 09:38:38 AM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640480432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2640480432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.108490045 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 454990661 ps |
| CPU time | 10.91 seconds |
| Started | Oct 15 09:38:25 AM UTC 24 |
| Finished | Oct 15 09:38:37 AM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108490045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.108490045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.3522599632 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2663994009 ps |
| CPU time | 8.44 seconds |
| Started | Oct 15 09:38:30 AM UTC 24 |
| Finished | Oct 15 09:38:39 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522599632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3522599632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3130513228 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 6767405531 ps |
| CPU time | 65.7 seconds |
| Started | Oct 15 09:38:31 AM UTC 24 |
| Finished | Oct 15 09:39:39 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3130513228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.otp_ctrl_stress_all_with_rand_reset.3130513228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.2114100247 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 7956966751 ps |
| CPU time | 46.46 seconds |
| Started | Oct 15 09:38:30 AM UTC 24 |
| Finished | Oct 15 09:39:18 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114100247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2114100247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.3872881790 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1501435235 ps |
| CPU time | 6.67 seconds |
| Started | Oct 15 09:45:06 AM UTC 24 |
| Finished | Oct 15 09:45:14 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872881790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3872881790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.160669195 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5753260646 ps |
| CPU time | 11.8 seconds |
| Started | Oct 15 09:45:06 AM UTC 24 |
| Finished | Oct 15 09:45:19 AM UTC 24 |
| Peak memory | 253024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160669195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.160669195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.513152806 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 559640975 ps |
| CPU time | 5.23 seconds |
| Started | Oct 15 09:45:06 AM UTC 24 |
| Finished | Oct 15 09:45:12 AM UTC 24 |
| Peak memory | 252952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513152806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.513152806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.2968119506 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1210178074 ps |
| CPU time | 15.36 seconds |
| Started | Oct 15 09:45:06 AM UTC 24 |
| Finished | Oct 15 09:45:22 AM UTC 24 |
| Peak memory | 252960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968119506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2968119506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.1601536071 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 452282334 ps |
| CPU time | 5.03 seconds |
| Started | Oct 15 09:45:10 AM UTC 24 |
| Finished | Oct 15 09:45:16 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601536071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1601536071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.2004287356 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1131275588 ps |
| CPU time | 13.1 seconds |
| Started | Oct 15 09:45:10 AM UTC 24 |
| Finished | Oct 15 09:45:24 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004287356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2004287356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.830416611 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 10026586209 ps |
| CPU time | 32.21 seconds |
| Started | Oct 15 09:45:10 AM UTC 24 |
| Finished | Oct 15 09:45:44 AM UTC 24 |
| Peak memory | 259296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=830416611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.830416611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.1547597250 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 570698161 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 09:45:10 AM UTC 24 |
| Finished | Oct 15 09:45:18 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547597250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1547597250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.3086268103 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 309890268 ps |
| CPU time | 4.76 seconds |
| Started | Oct 15 09:45:10 AM UTC 24 |
| Finished | Oct 15 09:45:16 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086268103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3086268103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.3087207432 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 154118221 ps |
| CPU time | 4.62 seconds |
| Started | Oct 15 09:45:12 AM UTC 24 |
| Finished | Oct 15 09:45:18 AM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087207432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.3087207432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.1487620234 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 171033975 ps |
| CPU time | 6.6 seconds |
| Started | Oct 15 09:45:12 AM UTC 24 |
| Finished | Oct 15 09:45:20 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487620234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1487620234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2365765832 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2215066538 ps |
| CPU time | 34.89 seconds |
| Started | Oct 15 09:45:15 AM UTC 24 |
| Finished | Oct 15 09:45:51 AM UTC 24 |
| Peak memory | 259092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2365765832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 64.otp_ctrl_stress_all_with_rand_reset.2365765832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3649930297 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 558170825 ps |
| CPU time | 4.33 seconds |
| Started | Oct 15 09:45:15 AM UTC 24 |
| Finished | Oct 15 09:45:20 AM UTC 24 |
| Peak memory | 252984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649930297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3649930297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.1001242248 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 264498014 ps |
| CPU time | 14.81 seconds |
| Started | Oct 15 09:45:15 AM UTC 24 |
| Finished | Oct 15 09:45:31 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001242248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1001242248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.73728644 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3862048939 ps |
| CPU time | 58 seconds |
| Started | Oct 15 09:45:15 AM UTC 24 |
| Finished | Oct 15 09:46:15 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=73728644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.73728644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.4090558334 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 496197967 ps |
| CPU time | 6.02 seconds |
| Started | Oct 15 09:45:15 AM UTC 24 |
| Finished | Oct 15 09:45:22 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090558334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.4090558334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.1205033061 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2886622754 ps |
| CPU time | 10.67 seconds |
| Started | Oct 15 09:45:18 AM UTC 24 |
| Finished | Oct 15 09:45:30 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205033061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1205033061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.3083639040 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 286670484 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 09:45:18 AM UTC 24 |
| Finished | Oct 15 09:45:24 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083639040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3083639040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.4091696216 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1813143554 ps |
| CPU time | 5.77 seconds |
| Started | Oct 15 09:45:18 AM UTC 24 |
| Finished | Oct 15 09:45:25 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091696216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.4091696216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.1975513008 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 137354577 ps |
| CPU time | 5.82 seconds |
| Started | Oct 15 09:45:20 AM UTC 24 |
| Finished | Oct 15 09:45:27 AM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975513008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1975513008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.4180274807 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 9375442075 ps |
| CPU time | 129.04 seconds |
| Started | Oct 15 09:45:20 AM UTC 24 |
| Finished | Oct 15 09:47:31 AM UTC 24 |
| Peak memory | 275480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4180274807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.4180274807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.733522325 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 241365140 ps |
| CPU time | 3.49 seconds |
| Started | Oct 15 09:45:20 AM UTC 24 |
| Finished | Oct 15 09:45:25 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733522325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.733522325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.3003766296 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 232058259 ps |
| CPU time | 4.49 seconds |
| Started | Oct 15 09:45:22 AM UTC 24 |
| Finished | Oct 15 09:45:27 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003766296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.3003766296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.979431461 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 71489978 ps |
| CPU time | 2.93 seconds |
| Started | Oct 15 09:38:39 AM UTC 24 |
| Finished | Oct 15 09:38:43 AM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979431461 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.979431461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.3886550558 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2628919764 ps |
| CPU time | 26.97 seconds |
| Started | Oct 15 09:38:34 AM UTC 24 |
| Finished | Oct 15 09:39:02 AM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886550558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3886550558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.3553967169 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 840618330 ps |
| CPU time | 23.1 seconds |
| Started | Oct 15 09:38:37 AM UTC 24 |
| Finished | Oct 15 09:39:01 AM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553967169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3553967169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.4249147224 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1521876861 ps |
| CPU time | 27.31 seconds |
| Started | Oct 15 09:38:37 AM UTC 24 |
| Finished | Oct 15 09:39:05 AM UTC 24 |
| Peak memory | 254804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249147224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.4249147224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.2044554290 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 101735865 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 09:38:34 AM UTC 24 |
| Finished | Oct 15 09:38:39 AM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044554290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2044554290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.2257075326 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 12818174814 ps |
| CPU time | 39.18 seconds |
| Started | Oct 15 09:38:39 AM UTC 24 |
| Finished | Oct 15 09:39:19 AM UTC 24 |
| Peak memory | 259052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257075326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2257075326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.2355292231 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2203213951 ps |
| CPU time | 9.4 seconds |
| Started | Oct 15 09:38:39 AM UTC 24 |
| Finished | Oct 15 09:38:49 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355292231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2355292231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3327189227 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 209008050 ps |
| CPU time | 4.78 seconds |
| Started | Oct 15 09:38:36 AM UTC 24 |
| Finished | Oct 15 09:38:42 AM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327189227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3327189227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.3750437384 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1147191687 ps |
| CPU time | 8.02 seconds |
| Started | Oct 15 09:38:36 AM UTC 24 |
| Finished | Oct 15 09:38:46 AM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750437384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3750437384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.247184923 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 319084910 ps |
| CPU time | 5.23 seconds |
| Started | Oct 15 09:38:39 AM UTC 24 |
| Finished | Oct 15 09:38:45 AM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247184923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.247184923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.3534096539 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 574183188 ps |
| CPU time | 8.27 seconds |
| Started | Oct 15 09:38:32 AM UTC 24 |
| Finished | Oct 15 09:38:42 AM UTC 24 |
| Peak memory | 253052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534096539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3534096539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.1317936500 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 653201084 ps |
| CPU time | 4.3 seconds |
| Started | Oct 15 09:38:39 AM UTC 24 |
| Finished | Oct 15 09:38:44 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317936500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1317936500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.2941994365 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2526675542 ps |
| CPU time | 8.06 seconds |
| Started | Oct 15 09:45:23 AM UTC 24 |
| Finished | Oct 15 09:45:32 AM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941994365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2941994365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.2032869861 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1906507549 ps |
| CPU time | 17.48 seconds |
| Started | Oct 15 09:45:26 AM UTC 24 |
| Finished | Oct 15 09:45:44 AM UTC 24 |
| Peak memory | 253092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032869861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2032869861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.4237083233 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 455703280 ps |
| CPU time | 5.32 seconds |
| Started | Oct 15 09:45:26 AM UTC 24 |
| Finished | Oct 15 09:45:32 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237083233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.4237083233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.4213443898 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 259708031 ps |
| CPU time | 8.24 seconds |
| Started | Oct 15 09:45:26 AM UTC 24 |
| Finished | Oct 15 09:45:35 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213443898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.4213443898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.954610487 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 4949306790 ps |
| CPU time | 62.04 seconds |
| Started | Oct 15 09:45:26 AM UTC 24 |
| Finished | Oct 15 09:46:30 AM UTC 24 |
| Peak memory | 269736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=954610487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.954610487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.192627727 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 538620378 ps |
| CPU time | 4.65 seconds |
| Started | Oct 15 09:45:26 AM UTC 24 |
| Finished | Oct 15 09:45:32 AM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192627727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.192627727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.1560846183 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 424963056 ps |
| CPU time | 7.34 seconds |
| Started | Oct 15 09:45:32 AM UTC 24 |
| Finished | Oct 15 09:45:41 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560846183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1560846183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.2770818525 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 359675644 ps |
| CPU time | 5 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:45:39 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770818525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2770818525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.3565702667 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 260208000 ps |
| CPU time | 12.28 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:45:46 AM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565702667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3565702667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3137289418 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3820582771 ps |
| CPU time | 58.3 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:46:33 AM UTC 24 |
| Peak memory | 269332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3137289418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.3137289418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1850390006 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 385564140 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:45:38 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850390006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1850390006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.118430322 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 117249223 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:45:40 AM UTC 24 |
| Peak memory | 252868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118430322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.118430322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1814055538 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5487863766 ps |
| CPU time | 61.16 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:46:36 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1814055538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 74.otp_ctrl_stress_all_with_rand_reset.1814055538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.1805405333 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 135190516 ps |
| CPU time | 4.99 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:45:39 AM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805405333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1805405333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3911977125 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 190272016 ps |
| CPU time | 9.21 seconds |
| Started | Oct 15 09:45:33 AM UTC 24 |
| Finished | Oct 15 09:45:43 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911977125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3911977125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.3221324811 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 127064582 ps |
| CPU time | 4.76 seconds |
| Started | Oct 15 09:45:34 AM UTC 24 |
| Finished | Oct 15 09:45:40 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221324811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3221324811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.1115146863 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 314994210 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 09:45:37 AM UTC 24 |
| Finished | Oct 15 09:45:43 AM UTC 24 |
| Peak memory | 252400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115146863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1115146863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.3407167106 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 158788935 ps |
| CPU time | 3.86 seconds |
| Started | Oct 15 09:45:42 AM UTC 24 |
| Finished | Oct 15 09:45:47 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407167106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3407167106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.1920608994 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 10219516191 ps |
| CPU time | 86.8 seconds |
| Started | Oct 15 09:45:43 AM UTC 24 |
| Finished | Oct 15 09:47:11 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1920608994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 77.otp_ctrl_stress_all_with_rand_reset.1920608994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.1692423989 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 478197091 ps |
| CPU time | 4.04 seconds |
| Started | Oct 15 09:45:43 AM UTC 24 |
| Finished | Oct 15 09:45:48 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692423989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1692423989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.4128661606 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 299929297 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 09:45:43 AM UTC 24 |
| Finished | Oct 15 09:45:48 AM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128661606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.4128661606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1686792854 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2724772726 ps |
| CPU time | 41.07 seconds |
| Started | Oct 15 09:45:43 AM UTC 24 |
| Finished | Oct 15 09:46:25 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1686792854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 78.otp_ctrl_stress_all_with_rand_reset.1686792854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2896344643 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 129590599 ps |
| CPU time | 3.84 seconds |
| Started | Oct 15 09:45:43 AM UTC 24 |
| Finished | Oct 15 09:45:48 AM UTC 24 |
| Peak memory | 254484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896344643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2896344643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.1724630739 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 223147666 ps |
| CPU time | 4.4 seconds |
| Started | Oct 15 09:45:43 AM UTC 24 |
| Finished | Oct 15 09:45:48 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724630739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1724630739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.1245348266 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 753321081 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 09:38:45 AM UTC 24 |
| Finished | Oct 15 09:38:48 AM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245348266 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1245348266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.951201931 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6201341324 ps |
| CPU time | 41.02 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:39:24 AM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951201931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.951201931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.4199490975 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 392094639 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 09:38:44 AM UTC 24 |
| Finished | Oct 15 09:38:50 AM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199490975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.4199490975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.2640003766 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4504758403 ps |
| CPU time | 32.98 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:39:16 AM UTC 24 |
| Peak memory | 257008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640003766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2640003766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.2046258766 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 17101219613 ps |
| CPU time | 29.16 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:39:12 AM UTC 24 |
| Peak memory | 254964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046258766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2046258766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.3704509944 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 237880805 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:38:46 AM UTC 24 |
| Peak memory | 252916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704509944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3704509944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.1811382065 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 270404127 ps |
| CPU time | 6.56 seconds |
| Started | Oct 15 09:38:44 AM UTC 24 |
| Finished | Oct 15 09:38:52 AM UTC 24 |
| Peak memory | 259248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811382065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1811382065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.2728112649 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2320808527 ps |
| CPU time | 16.72 seconds |
| Started | Oct 15 09:38:44 AM UTC 24 |
| Finished | Oct 15 09:39:03 AM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728112649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2728112649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.3486808175 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 314804229 ps |
| CPU time | 7.06 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:38:49 AM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486808175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.3486808175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.441745614 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 231393149 ps |
| CPU time | 8.97 seconds |
| Started | Oct 15 09:38:44 AM UTC 24 |
| Finished | Oct 15 09:38:55 AM UTC 24 |
| Peak memory | 252548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441745614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.441745614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.3938855663 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 287024938 ps |
| CPU time | 6.99 seconds |
| Started | Oct 15 09:38:41 AM UTC 24 |
| Finished | Oct 15 09:38:49 AM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938855663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3938855663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.362414417 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 4070102469 ps |
| CPU time | 31 seconds |
| Started | Oct 15 09:38:45 AM UTC 24 |
| Finished | Oct 15 09:39:17 AM UTC 24 |
| Peak memory | 257260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362414417 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.362414417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.2205530329 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2083612807 ps |
| CPU time | 27.92 seconds |
| Started | Oct 15 09:38:44 AM UTC 24 |
| Finished | Oct 15 09:39:14 AM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205530329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2205530329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.247447409 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 232407127 ps |
| CPU time | 7.39 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:59 AM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247447409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.247447409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.2424221933 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 271824272 ps |
| CPU time | 6.99 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:59 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424221933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2424221933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.308174157 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2155675763 ps |
| CPU time | 4.67 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:57 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308174157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.308174157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.2434994333 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 552963285 ps |
| CPU time | 10.29 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:46:02 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434994333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2434994333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1635678508 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3616046074 ps |
| CPU time | 49.63 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:46:42 AM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1635678508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.1635678508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.3813810587 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1711213269 ps |
| CPU time | 5.29 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:57 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813810587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3813810587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.308558493 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 302607914 ps |
| CPU time | 10.97 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:46:03 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308558493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.308558493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.606718025 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 5661548794 ps |
| CPU time | 57.49 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:46:50 AM UTC 24 |
| Peak memory | 259432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=606718025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.606718025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.391209860 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 516708040 ps |
| CPU time | 6.78 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:59 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391209860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.391209860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.3091915622 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 407082326 ps |
| CPU time | 4.74 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:57 AM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091915622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3091915622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1990277104 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2604406662 ps |
| CPU time | 47.97 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:46:41 AM UTC 24 |
| Peak memory | 269332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1990277104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 83.otp_ctrl_stress_all_with_rand_reset.1990277104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2555519454 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 129622691 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:45:56 AM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555519454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2555519454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2148168348 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1120049942 ps |
| CPU time | 9.12 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:46:02 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148168348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2148168348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2028161180 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 6525018766 ps |
| CPU time | 91.92 seconds |
| Started | Oct 15 09:45:51 AM UTC 24 |
| Finished | Oct 15 09:47:25 AM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2028161180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 84.otp_ctrl_stress_all_with_rand_reset.2028161180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.6143766 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 467609449 ps |
| CPU time | 7.12 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:46:15 AM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6143766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.6143766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3156663932 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 1972087616 ps |
| CPU time | 77.99 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:47:27 AM UTC 24 |
| Peak memory | 269272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3156663932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 85.otp_ctrl_stress_all_with_rand_reset.3156663932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.1077631164 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2176464567 ps |
| CPU time | 5.16 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:46:13 AM UTC 24 |
| Peak memory | 254776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077631164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1077631164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.4043719205 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 545934035 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:46:13 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043719205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4043719205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.1492376044 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 106949336 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:46:12 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492376044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1492376044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.1609458738 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 107747000 ps |
| CPU time | 3.99 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:46:12 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609458738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1609458738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.259153572 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 14430586060 ps |
| CPU time | 113.15 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:48:03 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=259153572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.259153572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.2184723536 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 190259756 ps |
| CPU time | 4.25 seconds |
| Started | Oct 15 09:46:07 AM UTC 24 |
| Finished | Oct 15 09:46:13 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184723536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2184723536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.4117575051 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 806833383 ps |
| CPU time | 23.57 seconds |
| Started | Oct 15 09:46:08 AM UTC 24 |
| Finished | Oct 15 09:46:32 AM UTC 24 |
| Peak memory | 252228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117575051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.4117575051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.3587933249 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 154162923 ps |
| CPU time | 5.3 seconds |
| Started | Oct 15 09:46:08 AM UTC 24 |
| Finished | Oct 15 09:46:14 AM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587933249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3587933249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.379024252 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 168682452 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 09:46:08 AM UTC 24 |
| Finished | Oct 15 09:46:13 AM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379024252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.379024252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3344863219 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2978573574 ps |
| CPU time | 76.46 seconds |
| Started | Oct 15 09:46:08 AM UTC 24 |
| Finished | Oct 15 09:47:26 AM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3344863219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 89.otp_ctrl_stress_all_with_rand_reset.3344863219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.3151760693 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 117487863 ps |
| CPU time | 2.22 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:38:55 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151760693 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3151760693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.2009463796 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2899657968 ps |
| CPU time | 43.73 seconds |
| Started | Oct 15 09:38:46 AM UTC 24 |
| Finished | Oct 15 09:39:31 AM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009463796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2009463796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.4133955247 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2159586132 ps |
| CPU time | 12.08 seconds |
| Started | Oct 15 09:38:49 AM UTC 24 |
| Finished | Oct 15 09:39:03 AM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133955247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.4133955247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3676198471 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 7978060373 ps |
| CPU time | 29.1 seconds |
| Started | Oct 15 09:38:48 AM UTC 24 |
| Finished | Oct 15 09:39:19 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676198471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3676198471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.793792709 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 9475391058 ps |
| CPU time | 23.09 seconds |
| Started | Oct 15 09:38:48 AM UTC 24 |
| Finished | Oct 15 09:39:13 AM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793792709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.793792709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.752104033 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 247795181 ps |
| CPU time | 4.15 seconds |
| Started | Oct 15 09:38:46 AM UTC 24 |
| Finished | Oct 15 09:38:51 AM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752104033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.752104033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.2035446733 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 145769910 ps |
| CPU time | 6.77 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:38:59 AM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035446733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.2035446733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.3773518651 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 161838170 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:38:59 AM UTC 24 |
| Peak memory | 258844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773518651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3773518651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.3965190699 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 363592748 ps |
| CPU time | 9.04 seconds |
| Started | Oct 15 09:38:48 AM UTC 24 |
| Finished | Oct 15 09:38:58 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965190699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3965190699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.2251037364 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 6130663183 ps |
| CPU time | 15.07 seconds |
| Started | Oct 15 09:38:48 AM UTC 24 |
| Finished | Oct 15 09:39:05 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251037364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2251037364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.2596633959 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 855607449 ps |
| CPU time | 7.4 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:39:00 AM UTC 24 |
| Peak memory | 252996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596633959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2596633959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2628136012 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2108311035 ps |
| CPU time | 25.9 seconds |
| Started | Oct 15 09:38:46 AM UTC 24 |
| Finished | Oct 15 09:39:13 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628136012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2628136012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.87321848 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2017863042 ps |
| CPU time | 12.83 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:39:05 AM UTC 24 |
| Peak memory | 256828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87321848 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.87321848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3696754493 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 13387362461 ps |
| CPU time | 116.2 seconds |
| Started | Oct 15 09:38:51 AM UTC 24 |
| Finished | Oct 15 09:40:50 AM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3696754493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.otp_ctrl_stress_all_with_rand_reset.3696754493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3501681291 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 292260409 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 09:46:08 AM UTC 24 |
| Finished | Oct 15 09:46:15 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501681291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3501681291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.1991863294 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1209147003 ps |
| CPU time | 13.22 seconds |
| Started | Oct 15 09:46:12 AM UTC 24 |
| Finished | Oct 15 09:46:26 AM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991863294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1991863294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.187493724 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2964302051 ps |
| CPU time | 39.78 seconds |
| Started | Oct 15 09:46:12 AM UTC 24 |
| Finished | Oct 15 09:46:53 AM UTC 24 |
| Peak memory | 259372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=187493724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.187493724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.3837976962 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 434469433 ps |
| CPU time | 9.6 seconds |
| Started | Oct 15 09:46:12 AM UTC 24 |
| Finished | Oct 15 09:46:23 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837976962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3837976962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.756454091 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 18595347167 ps |
| CPU time | 141.04 seconds |
| Started | Oct 15 09:46:12 AM UTC 24 |
| Finished | Oct 15 09:48:36 AM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=756454091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.756454091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.1754184488 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 562658576 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 09:46:15 AM UTC 24 |
| Finished | Oct 15 09:46:23 AM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754184488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1754184488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.852057004 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 274499161 ps |
| CPU time | 6.4 seconds |
| Started | Oct 15 09:46:15 AM UTC 24 |
| Finished | Oct 15 09:46:23 AM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852057004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.852057004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.2757193278 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 157545326 ps |
| CPU time | 4.91 seconds |
| Started | Oct 15 09:46:15 AM UTC 24 |
| Finished | Oct 15 09:46:21 AM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757193278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2757193278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.2289959030 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 965575275 ps |
| CPU time | 10.41 seconds |
| Started | Oct 15 09:46:15 AM UTC 24 |
| Finished | Oct 15 09:46:27 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289959030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2289959030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3086872937 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 8863412432 ps |
| CPU time | 73.74 seconds |
| Started | Oct 15 09:46:15 AM UTC 24 |
| Finished | Oct 15 09:47:31 AM UTC 24 |
| Peak memory | 275480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3086872937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 93.otp_ctrl_stress_all_with_rand_reset.3086872937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.1490613083 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 601195809 ps |
| CPU time | 5.22 seconds |
| Started | Oct 15 09:46:16 AM UTC 24 |
| Finished | Oct 15 09:46:22 AM UTC 24 |
| Peak memory | 252984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490613083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1490613083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.4182167135 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 125754332 ps |
| CPU time | 5.33 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:46:27 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182167135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.4182167135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.832906556 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 476515070 ps |
| CPU time | 4.12 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:46:25 AM UTC 24 |
| Peak memory | 254932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832906556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.832906556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.1712654734 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 566892672 ps |
| CPU time | 13.16 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:46:35 AM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712654734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1712654734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.3214061010 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 43043987975 ps |
| CPU time | 78.92 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:47:41 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3214061010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 95.otp_ctrl_stress_all_with_rand_reset.3214061010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.2330653687 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 188380783 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:46:26 AM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330653687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2330653687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.3955227510 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 215191593 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 09:46:20 AM UTC 24 |
| Finished | Oct 15 09:46:26 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955227510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3955227510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2795596840 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3050172485 ps |
| CPU time | 8.71 seconds |
| Started | Oct 15 09:46:23 AM UTC 24 |
| Finished | Oct 15 09:46:33 AM UTC 24 |
| Peak memory | 255092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795596840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2795596840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.3658174370 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 59519350 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 09:46:23 AM UTC 24 |
| Finished | Oct 15 09:46:28 AM UTC 24 |
| Peak memory | 254664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658174370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3658174370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3995373207 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 120170195 ps |
| CPU time | 4.05 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:46:33 AM UTC 24 |
| Peak memory | 254708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995373207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3995373207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.2255267828 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 294110146 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:46:35 AM UTC 24 |
| Peak memory | 252868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255267828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2255267828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1607697990 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 6867394327 ps |
| CPU time | 71.18 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:47:41 AM UTC 24 |
| Peak memory | 259080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1607697990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.1607697990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.1915354746 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 154019303 ps |
| CPU time | 5.17 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:46:35 AM UTC 24 |
| Peak memory | 254708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915354746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1915354746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.3280949975 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 132041699 ps |
| CPU time | 4.49 seconds |
| Started | Oct 15 09:46:28 AM UTC 24 |
| Finished | Oct 15 09:46:34 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280949975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3280949975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
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