PATTGEN Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 5.000s 2.239ms 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 34.749us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 13.531us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 569.793us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 4.000s 161.472us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 31.916us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 13.531us 20 20 100.00
pattgen_csr_aliasing 4.000s 161.472us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.550m 3.947ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.867m 2.657ms 50 50 100.00
V2 error pattgen_error 4.000s 56.519us 50 50 100.00
V2 stress_all pattgen_stress_all 2.000m 10.983ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 73.153us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 47.378us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 6.000s 684.612us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 6.000s 684.612us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 34.749us 5 5 100.00
pattgen_csr_rw 3.000s 13.531us 20 20 100.00
pattgen_csr_aliasing 4.000s 161.472us 5 5 100.00
pattgen_same_csr_outstanding 4.000s 68.252us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 34.749us 5 5 100.00
pattgen_csr_rw 3.000s 13.531us 20 20 100.00
pattgen_csr_aliasing 4.000s 161.472us 5 5 100.00
pattgen_same_csr_outstanding 4.000s 68.252us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 478.831us 20 20 100.00
pattgen_sec_cm 4.000s 176.039us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 478.831us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 46.500m 410.415ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 514 520 98.85

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.81 100.00 100.00 100.00 99.06 96.13 -- 100.00 90.43

Failure Buckets

Past Results