671f2b57e2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 27.000s | 149.320us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 7.000s | 51.907us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 24.320us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 8.000s | 36.000us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 7.000s | 30.156us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 14.000s | 89.382us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 24.320us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 7.000s | 30.156us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.800m | 8.052ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.917m | 2.635ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 10.000s | 72.329us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 1.917m | 20.604ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 8.000s | 64.619us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 11.000s | 20.523us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 14.000s | 31.778us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 14.000s | 31.778us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 7.000s | 51.907us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 24.320us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 30.156us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 9.000s | 20.525us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 7.000s | 51.907us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 24.320us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 30.156us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 9.000s | 20.525us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 10.000s | 87.615us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 191.684us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 10.000s | 87.615us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 36.000m | 83.341ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 515 | 520 | 99.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
7.pattgen_stress_all_with_rand_reset.20627225720341621724273233679943613817101074573454721815356450195653468027813
Line 788, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 142269039892 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
21.pattgen_stress_all_with_rand_reset.113262370535982716092797348359358359292355291527061039839556122526979137839716
Line 508, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13155162058 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
-------------------------------------
Name Type Size Value
... and 3 more failures.