Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T10
1	0	Covered	T11

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T12,T13	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T14,T15,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T17,T18,T19
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T20,T10

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	138488	104879	0	146
AlertKnownO_A	139111	106378	0	0
InBandInitRequest_A	139111	4032	0	0
InBandInitSequence_A	139111	404	0	0
InitReq_A	139111	737	0	0
IntegFailKnownO_A	139111	106378	0	0
NoSpuriousAlertsDuringInit_A	139111	15006	0	0
NoSpuriousPingOksDuringInit_A	139111	14642	0	0
PingDiffOk_A	138287	105554	0	0
PingOkBypassDuringInit_A	139111	45	0	38
PingOkKnownO_A	139111	106378	0	0
PingPKnownO_A	139111	106378	0	0
PingPending_A	139111	764	0	111
PingRequest0_A	139111	0	0	73
PingResponse0_A	139111	715	0	0
gen_async_assert.Alert_A	67374	1016	0	0
gen_async_assert.PingResponse1_A	67374	279	0	0
gen_async_assert.SigInt_A	67374	216	0	81
gen_sync_assert.Alert_A	71737	3136	0	0
gen_sync_assert.PingResponse1_A	71737	336	0	0
gen_sync_assert.SigInt_A	71737	38	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138488	104879	0	146
T1	1212	1058	0	2
T2	1132	1053	0	2
T3	1118	1033	0	2
T7	1038	959	0	2
T9	1014	955	0	2
T10	1081	1009	0	2
T17	1124	1030	0	2
T20	1099	1003	0	2
T21	1131	1044	0	2
T22	1148	1052	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	106378	0	0
T1	1226	1076	0	0
T2	1146	1069	0	0
T3	1134	1051	0	0
T7	1052	975	0	0
T9	1029	972	0	0
T10	1097	1027	0	0
T17	1140	1048	0	0
T20	1114	1020	0	0
T21	1146	1061	0	0
T22	1162	1068	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	4032	0	0
T1	1226	69	0	0
T2	1146	59	0	0
T3	1134	49	0	0
T7	1052	44	0	0
T9	1029	63	0	0
T10	1097	49	0	0
T17	1140	54	0	0
T20	1114	53	0	0
T21	1146	75	0	0
T22	1162	69	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	404	0	0
T1	1226	2	0	0
T2	1146	2	0	0
T3	1134	3	0	0
T7	1052	4	0	0
T9	1029	1	0	0
T10	1097	1	0	0
T17	1140	3	0	0
T20	1114	1	0	0
T21	1146	4	0	0
T22	1162	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	737	0	0
T1	1226	12	0	0
T2	1146	12	0	0
T3	1134	11	0	0
T7	1052	8	0	0
T9	1029	9	0	0
T10	1097	8	0	0
T17	1140	8	0	0
T20	1114	9	0	0
T21	1146	11	0	0
T22	1162	12	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	106378	0	0
T1	1226	1076	0	0
T2	1146	1069	0	0
T3	1134	1051	0	0
T7	1052	975	0	0
T9	1029	972	0	0
T10	1097	1027	0	0
T17	1140	1048	0	0
T20	1114	1020	0	0
T21	1146	1061	0	0
T22	1162	1068	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	15006	0	0
T1	1226	245	0	0
T2	1146	232	0	0
T3	1134	214	0	0
T7	1052	167	0	0
T9	1029	179	0	0
T10	1097	161	0	0
T17	1140	167	0	0
T20	1114	189	0	0
T21	1146	217	0	0
T22	1162	229	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	14642	0	0
T1	1226	240	0	0
T2	1146	228	0	0
T3	1134	199	0	0
T7	1052	164	0	0
T9	1029	164	0	0
T10	1097	147	0	0
T17	1140	167	0	0
T20	1114	184	0	0
T21	1146	212	0	0
T22	1162	225	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138287	105554	0	0
T1	1209	1059	0	0
T2	1129	1052	0	0
T3	1117	1034	0	0
T7	1039	962	0	0
T9	1024	967	0	0
T10	1084	1014	0	0
T17	1123	1031	0	0
T20	1095	1001	0	0
T21	1131	1046	0	0
T22	1147	1053	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	45	0	38
T1	1226	1	0	0
T2	1146	0	0	0
T3	1134	0	0	0
T7	1052	0	0	0
T9	1029	2	0	0
T10	1097	0	0	0
T15	0	0	0	1
T17	1140	0	0	0
T19	0	2	0	0
T20	1114	1	0	0
T21	1146	1	0	0
T22	1162	2	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	1
T26	0	1	0	0
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	106378	0	0
T1	1226	1076	0	0
T2	1146	1069	0	0
T3	1134	1051	0	0
T7	1052	975	0	0
T9	1029	972	0	0
T10	1097	1027	0	0
T17	1140	1048	0	0
T20	1114	1020	0	0
T21	1146	1061	0	0
T22	1162	1068	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	106378	0	0
T1	1226	1076	0	0
T2	1146	1069	0	0
T3	1134	1051	0	0
T7	1052	975	0	0
T9	1029	972	0	0
T10	1097	1027	0	0
T17	1140	1048	0	0
T20	1114	1020	0	0
T21	1146	1061	0	0
T22	1162	1068	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	764	0	111
T1	1226	11	0	1
T2	1146	11	0	1
T3	1134	11	0	1
T7	1052	11	0	1
T9	1029	10	0	1
T10	1097	11	0	1
T17	1140	11	0	1
T20	1114	11	0	1
T21	1146	11	0	1
T22	1162	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	0	0	73

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139111	715	0	0
T1	1226	10	0	0
T2	1146	10	0	0
T3	1134	9	0	0
T7	1052	8	0	0
T9	1029	10	0	0
T10	1097	10	0	0
T17	1140	10	0	0
T20	1114	10	0	0
T21	1146	10	0	0
T22	1162	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67374	1016	0	0
T1	1226	7	0	0
T2	1146	7	0	0
T3	1134	9	0	0
T7	1052	9	0	0
T9	1029	8	0	0
T10	1097	7	0	0
T17	1140	6	0	0
T20	1114	8	0	0
T21	1146	8	0	0
T22	1162	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67374	279	0	0
T1	1226	7	0	0
T2	1146	8	0	0
T3	1134	7	0	0
T7	1052	8	0	0
T9	1029	6	0	0
T10	1097	9	0	0
T17	1140	10	0	0
T20	1114	7	0	0
T21	1146	7	0	0
T22	1162	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67374	216	0	81
T1	1226	5	0	3
T2	1146	5	0	3
T3	1134	7	0	2
T7	1052	6	0	2
T9	1029	8	0	0
T10	1097	8	0	1
T12	0	0	0	2
T17	1140	6	0	2
T20	1114	7	0	3
T21	1146	8	0	2
T22	1162	7	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71737	3136	0	0
T15	1042	10	0	0
T27	898	10	0	0
T28	891	9	0	0
T29	1047	8	0	0
T30	979	10	0	0
T31	893	11	0	0
T32	853	11	0	0
T33	991	9	0	0
T34	967	7	0	0
T35	834	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71737	336	0	0
T15	1042	9	0	0
T27	898	8	0	0
T28	891	9	0	0
T29	1047	8	0	0
T30	979	9	0	0
T31	893	9	0	0
T32	853	10	0	0
T33	991	9	0	0
T34	967	9	0	0
T35	834	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71737	38	0	0
T15	1042	1	0	0
T27	898	1	0	0
T28	891	1	0	0
T29	1047	1	0	0
T30	979	1	0	0
T31	893	1	0	0
T32	853	1	0	0
T33	991	1	0	0
T34	967	1	0	0
T35	834	1	0	0