Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T10,T11

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T12,T13,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T15
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T12,T16,T14
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T2,T3,T13

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	152747	115310	0	158
AlertKnownO_A	153449	116982	0	0
InBandInitRequest_A	153449	4194	0	0
InBandInitSequence_A	153449	431	0	0
InitReq_A	153449	790	0	0
IntegFailKnownO_A	153449	116982	0	0
NoSpuriousAlertsDuringInit_A	153449	16444	0	0
NoSpuriousPingOksDuringInit_A	153449	16148	0	0
PingDiffOk_A	152567	116100	0	0
PingOkBypassDuringInit_A	153449	49	0	40
PingOkKnownO_A	153449	116982	0	0
PingPKnownO_A	153449	116982	0	0
PingPending_A	153449	826	0	119
PingRequest0_A	153449	0	0	79
PingResponse0_A	153449	767	0	0
gen_async_assert.Alert_A	79292	1301	0	0
gen_async_assert.PingResponse1_A	79292	312	0	0
gen_async_assert.SigInt_A	79292	245	0	84
gen_sync_assert.Alert_A	74157	3175	0	0
gen_sync_assert.PingResponse1_A	74157	358	0	0
gen_sync_assert.SigInt_A	74157	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152747	115310	0	158
T1	1087	995	0	2
T2	1073	1010	0	2
T3	1181	1107	0	2
T7	1102	1001	0	2
T8	1021	926	0	2
T9	1051	958	0	2
T12	1255	1128	0	2
T16	1135	1035	0	2
T17	1087	1019	0	2
T18	1076	1009	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	116982	0	0
T1	1102	1012	0	0
T2	1088	1027	0	0
T3	1196	1124	0	0
T7	1117	1018	0	0
T8	1036	943	0	0
T9	1066	975	0	0
T12	1271	1148	0	0
T16	1151	1053	0	0
T17	1101	1035	0	0
T18	1092	1027	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	4194	0	0
T1	1102	61	0	0
T2	1088	44	0	0
T3	1196	70	0	0
T7	1117	61	0	0
T8	1036	34	0	0
T9	1066	47	0	0
T12	1271	65	0	0
T16	1151	62	0	0
T17	1101	36	0	0
T18	1092	24	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	431	0	0
T1	1102	3	0	0
T2	1088	2	0	0
T3	1196	3	0	0
T7	1117	3	0	0
T8	1036	1	0	0
T9	1066	1	0	0
T12	1271	2	0	0
T16	1151	1	0	0
T17	1101	0	0	0
T18	1092	1	0	0
T19	0	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	790	0	0
T1	1102	11	0	0
T2	1088	9	0	0
T3	1196	13	0	0
T7	1117	10	0	0
T8	1036	7	0	0
T9	1066	9	0	0
T12	1271	12	0	0
T16	1151	12	0	0
T17	1101	9	0	0
T18	1092	7	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	116982	0	0
T1	1102	1012	0	0
T2	1088	1027	0	0
T3	1196	1124	0	0
T7	1117	1018	0	0
T8	1036	943	0	0
T9	1066	975	0	0
T12	1271	1148	0	0
T16	1151	1053	0	0
T17	1101	1035	0	0
T18	1092	1027	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	16444	0	0
T1	1102	206	0	0
T2	1088	179	0	0
T3	1196	256	0	0
T7	1117	198	0	0
T8	1036	146	0	0
T9	1066	183	0	0
T12	1271	256	0	0
T16	1151	239	0	0
T17	1101	179	0	0
T18	1092	147	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	16148	0	0
T1	1102	201	0	0
T2	1088	167	0	0
T3	1196	254	0	0
T7	1117	179	0	0
T8	1036	130	0	0
T9	1066	178	0	0
T12	1271	256	0	0
T16	1151	224	0	0
T17	1101	177	0	0
T18	1092	145	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152567	116100	0	0
T1	1085	995	0	0
T2	1072	1011	0	0
T3	1178	1106	0	0
T7	1100	1001	0	0
T8	1019	926	0	0
T9	1054	963	0	0
T12	1253	1130	0	0
T16	1136	1038	0	0
T17	1087	1021	0	0
T18	1075	1010	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	49	0	40
T1	1102	3	0	1
T2	1088	0	0	0
T3	1196	0	0	0
T7	1117	1	0	0
T8	1036	1	0	0
T9	1066	2	0	0
T12	1271	0	0	0
T16	1151	0	0	0
T17	1101	0	0	0
T18	1092	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	2	0	0
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	116982	0	0
T1	1102	1012	0	0
T2	1088	1027	0	0
T3	1196	1124	0	0
T7	1117	1018	0	0
T8	1036	943	0	0
T9	1066	975	0	0
T12	1271	1148	0	0
T16	1151	1053	0	0
T17	1101	1035	0	0
T18	1092	1027	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	116982	0	0
T1	1102	1012	0	0
T2	1088	1027	0	0
T3	1196	1124	0	0
T7	1117	1018	0	0
T8	1036	943	0	0
T9	1066	975	0	0
T12	1271	1148	0	0
T16	1151	1053	0	0
T17	1101	1035	0	0
T18	1092	1027	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	826	0	119
T1	1102	11	0	1
T2	1088	11	0	1
T3	1196	11	0	1
T7	1117	11	0	1
T8	1036	11	0	1
T9	1066	11	0	1
T12	1271	11	0	1
T16	1151	11	0	1
T17	1101	11	0	1
T18	1092	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	0	0	79

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153449	767	0	0
T1	1102	10	0	0
T2	1088	10	0	0
T3	1196	10	0	0
T7	1117	9	0	0
T8	1036	8	0	0
T9	1066	9	0	0
T12	1271	10	0	0
T16	1151	10	0	0
T17	1101	10	0	0
T18	1092	9	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79292	1301	0	0
T1	1102	8	0	0
T2	1088	7	0	0
T3	1196	4	0	0
T7	1117	6	0	0
T8	1036	11	0	0
T9	1066	8	0	0
T12	1271	4	0	0
T16	1151	8	0	0
T17	1101	8	0	0
T18	1092	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79292	312	0	0
T1	1102	6	0	0
T2	1088	9	0	0
T3	1196	9	0	0
T7	1117	8	0	0
T8	1036	7	0	0
T9	1066	6	0	0
T12	1271	10	0	0
T16	1151	6	0	0
T17	1101	9	0	0
T18	1092	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79292	245	0	84
T1	1102	7	0	2
T2	1088	7	0	2
T3	1196	7	0	3
T7	1117	7	0	3
T8	1036	5	0	3
T9	1066	6	0	2
T12	1271	6	0	3
T16	1151	6	0	2
T17	1101	6	0	2
T18	1092	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74157	3175	0	0
T10	1000	8	0	0
T25	894	11	0	0
T26	898	9	0	0
T27	1008	10	0	0
T34	955	8	0	0
T35	971	9	0	0
T36	952	10	0	0
T37	1036	12	0	0
T38	939	9	0	0
T39	885	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74157	358	0	0
T10	1000	7	0	0
T25	894	9	0	0
T26	898	8	0	0
T27	1008	9	0	0
T34	955	8	0	0
T35	971	10	0	0
T36	952	10	0	0
T37	1036	10	0	0
T38	939	9	0	0
T39	885	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74157	40	0	0
T10	1000	1	0	0
T25	894	1	0	0
T26	898	1	0	0
T27	1008	1	0	0
T34	955	1	0	0
T35	971	1	0	0
T36	952	1	0	0
T37	1036	1	0	0
T38	939	1	0	0
T39	885	1	0	0