Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	1	1
145	1	1
146	1	1
163	1	1
167	1	1
171	1	1
172	1	1
175	1	1
177	1	1
178	1	1
182	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
226	1	1
227	1	1
229	1	1
230	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
242	1	1
246	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T11,T8	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T2,T3,T19
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T5,T18,T32
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T1,T2,T3
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T1,T2,T3
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(ping_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	case (state_q)
-2-:	202	if ((alert_trigger || ping_trigger))
-3-:	203	(alert_trigger) ? 
-4-:	210	if (ack_level)
-5-:	219	if ((!ack_level))
-6-:	226	if (ack_level)
-7-:	235	if ((!ack_level))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	255	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	156572	1103	0	0
AlertPKnownO_A	156572	118609	0	0
AlertState0_A	156572	118609	0	0
AlertTest1_A	156572	79	0	0
AlertTestHs_A	156572	79	0	0
gen_async_assert.DiffEncoding_A	82026	55667	0	5
gen_async_assert.InBandInitFsm_A	82026	112	0	149
gen_async_assert.InBandInitPing_A	82026	112	0	149
gen_async_assert.PingHs_A	82026	369	0	2
gen_async_assert.SigIntAck_A	82026	112	0	188
gen_async_assert.SigIntPing_A	82026	112	0	188
gen_fatal_assert.AlertState1_A	116724	6520	0	0
gen_fatal_assert.AlertState2_A	116724	46862	0	0
gen_fatal_assert.AlertState3_A	116724	4319	0	0
gen_recov_assert.AlertState1_A	39848	6396	0	0
gen_recov_assert.AlertState2_A	39848	0	0	0
gen_sync_assert.DiffEncoding_A	74546	51866	0	0
gen_sync_assert.InBandInitFsm_A	74546	0	0	0
gen_sync_assert.InBandInitPing_A	74546	0	0	0
gen_sync_assert.PingHs_A	74546	364	0	0
gen_sync_assert.SigIntAck_A	74546	0	0	0
gen_sync_assert.SigIntPing_A	74546	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156572	1103	0	0
T1	1203	15	0	0
T2	1112	18	0	0
T3	1049	15	0	0
T7	1086	17	0	0
T9	1163	17	0	0
T11	1187	14	0	0
T17	1042	14	0	0
T19	1081	15	0	0
T20	1080	17	0	0
T21	1114	14	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156572	118609	0	0
T1	1203	1029	0	0
T2	1112	1032	0	0
T3	1049	989	0	0
T7	1086	1021	0	0
T9	1163	1091	0	0
T11	1187	1017	0	0
T17	1042	978	0	0
T19	1081	982	0	0
T20	1080	1023	0	0
T21	1114	1021	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156572	118609	0	0
T1	1203	1029	0	0
T2	1112	1032	0	0
T3	1049	989	0	0
T7	1086	1021	0	0
T9	1163	1091	0	0
T11	1187	1017	0	0
T17	1042	978	0	0
T19	1081	982	0	0
T20	1080	1023	0	0
T21	1114	1021	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156572	79	0	0
T1	1203	1	0	0
T2	1112	1	0	0
T3	1049	1	0	0
T7	1086	1	0	0
T9	1163	1	0	0
T11	1187	1	0	0
T17	1042	1	0	0
T19	1081	1	0	0
T20	1080	1	0	0
T21	1114	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156572	79	0	0
T1	1203	1	0	0
T2	1112	1	0	0
T3	1049	1	0	0
T7	1086	1	0	0
T9	1163	1	0	0
T11	1187	1	0	0
T17	1042	1	0	0
T19	1081	1	0	0
T20	1080	1	0	0
T21	1114	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82026	55667	0	5
T1	1203	917	0	0
T2	1112	896	0	0
T3	1049	883	0	0
T7	1086	876	0	0
T9	1163	935	0	0
T11	1187	897	0	0
T17	1042	901	0	0
T19	1081	887	0	0
T20	1080	901	0	0
T21	1114	906	0	0
T35	0	0	0	3
T36	0	0	0	2

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82026	112	0	149
T1	1203	3	0	4
T2	1112	4	0	4
T3	1049	2	0	4
T7	1086	4	0	4
T9	1163	3	0	4
T11	1187	3	0	4
T17	1042	4	0	4
T19	1081	2	0	4
T20	1080	4	0	4
T21	1114	3	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82026	112	0	149
T1	1203	3	0	4
T2	1112	4	0	4
T3	1049	2	0	4
T7	1086	4	0	4
T9	1163	3	0	4
T11	1187	3	0	4
T17	1042	4	0	4
T19	1081	2	0	4
T20	1080	4	0	4
T21	1114	3	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82026	369	0	2
T1	1203	10	0	0
T2	1112	9	0	0
T3	1049	10	0	0
T7	1086	8	0	0
T9	1163	9	0	0
T11	1187	9	0	0
T17	1042	10	0	0
T19	1081	9	0	0
T20	1080	8	0	0
T21	1114	8	0	0
T35	0	0	0	1
T36	0	0	0	1

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82026	112	0	188
T1	1203	3	0	5
T2	1112	4	0	5
T3	1049	2	0	5
T7	1086	4	0	5
T9	1163	3	0	5
T11	1187	3	0	5
T17	1042	4	0	5
T19	1081	2	0	5
T20	1080	4	0	5
T21	1114	3	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82026	112	0	188
T1	1203	3	0	5
T2	1112	4	0	5
T3	1049	2	0	5
T7	1086	4	0	5
T9	1163	3	0	5
T11	1187	3	0	5
T17	1042	4	0	5
T19	1081	2	0	5
T20	1080	4	0	5
T21	1114	3	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116724	6520	0	0
T4	3023	189	0	0
T5	2943	267	0	0
T16	3042	256	0	0
T18	2970	269	0	0
T37	3250	213	0	0
T38	3076	245	0	0
T39	3016	248	0	0
T40	3232	257	0	0
T41	2926	195	0	0
T42	2984	266	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116724	46862	0	0
T4	3023	1220	0	0
T5	2943	1172	0	0
T16	3042	1331	0	0
T18	2970	1200	0	0
T37	3250	1418	0	0
T38	3076	1249	0	0
T39	3016	1270	0	0
T40	3232	1452	0	0
T41	2926	1122	0	0
T42	2984	1278	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116724	4319	0	0
T4	3023	66	0	0
T5	2943	60	0	0
T16	3042	67	0	0
T18	2970	61	0	0
T37	3250	76	0	0
T38	3076	63	0	0
T39	3016	64	0	0
T40	3232	74	0	0
T41	2926	59	0	0
T42	2984	64	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39848	6396	0	0
T1	1203	237	0	0
T2	1112	302	0	0
T3	1049	242	0	0
T7	1086	289	0	0
T9	1163	249	0	0
T11	1187	236	0	0
T17	1042	222	0	0
T19	1081	233	0	0
T20	1080	275	0	0
T21	1114	222	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39848	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74546	51866	0	0
T10	906	764	0	0
T13	1029	804	0	0
T24	914	755	0	0
T25	999	796	0	0
T26	879	752	0	0
T27	903	731	0	0
T28	903	753	0	0
T32	1085	842	0	0
T33	937	794	0	0
T34	905	793	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74546	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74546	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74546	364	0	0
T10	906	10	0	0
T13	1029	8	0	0
T24	914	9	0	0
T25	999	9	0	0
T26	879	9	0	0
T27	903	8	0	0
T28	903	7	0	0
T32	1085	9	0	0
T33	937	10	0	0
T34	905	10	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74546	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74546	0	0	0