Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T13

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T14,T9	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T14,T15,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T8,T14,T17
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T18,T19,T20

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	149067	112325	0	156
AlertKnownO_A	149753	113958	0	0
InBandInitRequest_A	149753	4128	0	0
InBandInitSequence_A	149753	405	0	0
InitReq_A	149753	768	0	0
IntegFailKnownO_A	149753	113958	0	0
NoSpuriousAlertsDuringInit_A	149753	16051	0	0
NoSpuriousPingOksDuringInit_A	149753	15740	0	0
PingDiffOk_A	148909	113114	0	0
PingOkBypassDuringInit_A	149753	41	0	40
PingOkKnownO_A	149753	113958	0	0
PingPKnownO_A	149753	113958	0	0
PingPending_A	149753	817	0	118
PingRequest0_A	149753	0	0	0
PingResponse0_A	149753	748	0	0
gen_async_assert.Alert_A	76779	1254	0	0
gen_async_assert.PingResponse1_A	76779	311	0	0
gen_async_assert.SigInt_A	76779	244	0	88
gen_sync_assert.Alert_A	72974	3086	0	0
gen_sync_assert.PingResponse1_A	72974	347	0	0
gen_sync_assert.SigInt_A	72974	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149067	112325	0	156
T1	1078	1021	0	2
T2	1194	1116	0	2
T3	1158	1009	0	2
T7	1117	1025	0	2
T8	1178	1114	0	2
T9	1138	998	0	2
T14	1170	989	0	2
T15	1104	974	0	2
T17	1143	1041	0	2
T21	1094	996	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	113958	0	0
T1	1093	1038	0	0
T2	1208	1132	0	0
T3	1172	1027	0	0
T7	1133	1043	0	0
T8	1192	1130	0	0
T9	1153	1017	0	0
T14	1185	1008	0	0
T15	1120	994	0	0
T17	1158	1058	0	0
T21	1109	1013	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	4128	0	0
T1	1093	51	0	0
T2	1208	74	0	0
T3	1172	53	0	0
T7	1133	48	0	0
T8	1192	86	0	0
T9	1153	44	0	0
T14	1185	48	0	0
T15	1120	35	0	0
T17	1158	46	0	0
T21	1109	44	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	405	0	0
T1	1093	1	0	0
T2	1208	3	0	0
T3	1172	1	0	0
T7	1133	2	0	0
T8	1192	4	0	0
T9	1153	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T14	1185	3	0	0
T15	1120	0	0	0
T17	1158	2	0	0
T21	1109	0	0	0
T22	0	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	768	0	0
T1	1093	9	0	0
T2	1208	14	0	0
T3	1172	10	0	0
T7	1133	11	0	0
T8	1192	14	0	0
T9	1153	8	0	0
T14	1185	7	0	0
T15	1120	8	0	0
T17	1158	10	0	0
T21	1109	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	113958	0	0
T1	1093	1038	0	0
T2	1208	1132	0	0
T3	1172	1027	0	0
T7	1133	1043	0	0
T8	1192	1130	0	0
T9	1153	1017	0	0
T14	1185	1008	0	0
T15	1120	994	0	0
T17	1158	1058	0	0
T21	1109	1013	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	16051	0	0
T1	1093	184	0	0
T2	1208	267	0	0
T3	1172	208	0	0
T7	1133	213	0	0
T8	1192	262	0	0
T9	1153	169	0	0
T14	1185	161	0	0
T15	1120	180	0	0
T17	1158	200	0	0
T21	1109	179	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	15740	0	0
T1	1093	181	0	0
T2	1208	266	0	0
T3	1172	202	0	0
T7	1133	209	0	0
T8	1192	257	0	0
T9	1153	168	0	0
T14	1185	159	0	0
T15	1120	175	0	0
T17	1158	198	0	0
T21	1109	177	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148909	113114	0	0
T1	1079	1024	0	0
T2	1195	1119	0	0
T3	1158	1013	0	0
T7	1116	1026	0	0
T8	1176	1114	0	0
T9	1135	999	0	0
T14	1172	995	0	0
T15	1102	976	0	0
T17	1142	1042	0	0
T21	1094	998	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	41	0	40
T1	1093	1	0	0
T2	1208	1	0	0
T3	1172	2	0	0
T4	0	1	0	0
T7	1133	1	0	0
T8	1192	0	0	0
T9	1153	0	0	0
T14	1185	0	0	0
T15	1120	2	0	0
T17	1158	0	0	0
T20	0	1	0	0
T21	1109	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	113958	0	0
T1	1093	1038	0	0
T2	1208	1132	0	0
T3	1172	1027	0	0
T7	1133	1043	0	0
T8	1192	1130	0	0
T9	1153	1017	0	0
T14	1185	1008	0	0
T15	1120	994	0	0
T17	1158	1058	0	0
T21	1109	1013	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	113958	0	0
T1	1093	1038	0	0
T2	1208	1132	0	0
T3	1172	1027	0	0
T7	1133	1043	0	0
T8	1192	1130	0	0
T9	1153	1017	0	0
T14	1185	1008	0	0
T15	1120	994	0	0
T17	1158	1058	0	0
T21	1109	1013	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	817	0	118
T1	1093	11	0	1
T2	1208	11	0	1
T3	1172	11	0	1
T7	1133	11	0	1
T8	1192	11	0	1
T9	1153	11	0	1
T14	1185	11	0	1
T15	1120	11	0	1
T17	1158	11	0	1
T21	1109	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149753	748	0	0
T1	1093	10	0	0
T2	1208	10	0	0
T3	1172	10	0	0
T7	1133	8	0	0
T8	1192	9	0	0
T9	1153	9	0	0
T14	1185	10	0	0
T15	1120	9	0	0
T17	1158	10	0	0
T21	1109	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76779	1254	0	0
T1	1093	9	0	0
T2	1208	6	0	0
T3	1172	8	0	0
T7	1133	7	0	0
T8	1192	7	0	0
T9	1153	7	0	0
T14	1185	10	0	0
T15	1120	10	0	0
T17	1158	6	0	0
T21	1109	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76779	311	0	0
T1	1093	8	0	0
T2	1208	9	0	0
T3	1172	6	0	0
T7	1133	7	0	0
T8	1192	7	0	0
T9	1153	9	0	0
T14	1185	9	0	0
T15	1120	6	0	0
T17	1158	9	0	0
T21	1109	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76779	244	0	88
T1	1093	5	0	2
T2	1208	7	0	2
T3	1172	5	0	3
T7	1133	7	0	2
T8	1192	5	0	2
T9	1153	7	0	3
T14	1185	5	0	3
T15	1120	8	0	3
T17	1158	7	0	2
T21	1109	7	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72974	3086	0	0
T26	908	10	0	0
T27	905	9	0	0
T28	879	12	0	0
T29	1034	12	0	0
T30	846	9	0	0
T36	919	8	0	0
T37	862	8	0	0
T38	901	10	0	0
T39	828	12	0	0
T40	875	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72974	347	0	0
T26	908	8	0	0
T27	905	9	0	0
T28	879	8	0	0
T29	1034	7	0	0
T30	846	9	0	0
T36	919	9	0	0
T37	862	10	0	0
T38	901	10	0	0
T39	828	10	0	0
T40	875	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72974	40	0	0
T26	908	1	0	0
T27	905	1	0	0
T28	879	1	0	0
T29	1034	1	0	0
T30	846	1	0	0
T36	919	1	0	0
T37	862	1	0	0
T38	901	1	0	0
T39	828	1	0	0
T40	875	1	0	0