Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.12	100.00	86.67	100.00	90.91	93.33	81.82

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_receiver	92.12	100.00	86.67	100.00	90.91	93.33	81.82

---

Module Instance : prim_esc_tb.i_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.12	100.00	86.67	100.00	90.91	93.33	81.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.12	100.00	86.67	100.00	90.91	93.33	81.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
ALWAYS	159	39	39	100.00
ALWAYS	239	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
99	1	1
100	1	1
154	1	1
155	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
165	1	1
168	1	1
169	1	1
170	1	1
171	1	1
			MISSING_ELSE
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
			MISSING_ELSE
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
239	1	1
240	1	1
242	1	1

---

Cond Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION ((timeout_cnt > '0) && ((!(&timeout_cnt))))
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       226
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       226
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_esc_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Check	169	Covered	T1,T2,T3
EscResp	181	Covered	T1,T2,T3
Idle	188	Covered	T1,T2,T3
PingResp	177	Covered	T1,T2,T3
SigInt	217	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Check->EscResp	181	Covered	T1,T2,T3
Check->PingResp	177	Covered	T1,T2,T3
Check->SigInt	227	Covered	T1,T15,T17
EscResp->Idle	200	Covered	T1,T2,T3
EscResp->SigInt	227	Covered	T1,T3,T8
Idle->Check	169	Covered	T1,T2,T3
Idle->SigInt	227	Covered	T2,T3,T8
PingResp->EscResp	193	Covered	T4
PingResp->Idle	188	Covered	T1,T2,T3
PingResp->SigInt	227	Not Covered
SigInt->Idle	214	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
Branches		15	14	93.33
CASE	165	11	10	90.91
IF	226	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	165	case (state_q)
-2-:	168	if (esc_level)
-3-:	180	if (esc_level)
-4-:	192	if (esc_level)
-5-:	201	if (esc_level)
-6-:	216	if (sigint_detected)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Idle	1	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	Covered	T1,T2,T3
Check	-	1	-	-	-	Covered	T1,T2,T3
Check	-	0	-	-	-	Covered	T1,T2,T3
PingResp	-	-	1	-	-	Covered	T4
PingResp	-	-	0	-	-	Covered	T1,T2,T3
EscResp	-	-	-	1	-	Covered	T1,T2,T3
EscResp	-	-	-	0	-	Covered	T1,T2,T3
SigInt	-	-	-	-	1	Covered	T1,T2,T3
SigInt	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	226	if ((sigint_detected && (state_q != SigInt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	9	81.82
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	9	81.82

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9555	5095	0	0
EscCntEsc_A	9555	0	0	0
EscCntWrap_A	9555	0	0	0
EscEnCheck_A	9555	314	0	0
EscEnKnownO_A	9555	5195	0	0
EscRespCheck_A	9555	315	0	20
PingRespCheck_A	9555	50	0	20
RespPKnownO_A	9555	5195	0	0
SigIntCheck0_A	9555	40	0	0
SigIntCheck1_A	9555	40	0	0
SigIntCheck2_A	9555	40	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	5095	0	0
T1	470	213	0	0
T2	432	238	0	0
T3	465	255	0	0
T4	448	222	0	0
T5	466	281	0	0
T6	505	265	0	0
T7	495	293	0	0
T8	486	244	0	0
T9	484	277	0	0
T16	487	261	0	0

EscCntEsc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	0	0	0

EscCntWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	0	0	0

EscEnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	314	0	0
T1	470	12	0	0
T2	432	16	0	0
T3	465	22	0	0
T4	448	10	0	0
T5	466	9	0	0
T6	505	21	0	0
T7	495	18	0	0
T8	486	16	0	0
T9	484	22	0	0
T16	487	24	0	0

EscEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	5195	0	0
T1	470	218	0	0
T2	432	243	0	0
T3	465	260	0	0
T4	448	227	0	0
T5	466	286	0	0
T6	505	270	0	0
T7	495	298	0	0
T8	486	249	0	0
T9	484	282	0	0
T16	487	266	0	0

EscRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	315	0	20
T1	470	12	0	1
T2	432	16	0	1
T3	465	22	0	1
T4	448	10	0	1
T5	466	9	0	1
T6	505	21	0	1
T7	495	19	0	1
T8	486	16	0	1
T9	484	22	0	1
T16	487	24	0	1

PingRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	50	0	20
T1	470	2	0	1
T2	432	3	0	1
T3	465	2	0	1
T4	448	3	0	1
T5	466	2	0	1
T6	505	2	0	1
T7	495	2	0	1
T8	486	2	0	1
T9	484	3	0	1
T16	487	3	0	1

RespPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	5195	0	0
T1	470	218	0	0
T2	432	243	0	0
T3	465	260	0	0
T4	448	227	0	0
T5	466	286	0	0
T6	505	270	0	0
T7	495	298	0	0
T8	486	249	0	0
T9	484	282	0	0
T16	487	266	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	40	0	0
T1	470	2	0	0
T2	432	2	0	0
T3	465	2	0	0
T4	448	2	0	0
T5	466	2	0	0
T6	505	2	0	0
T7	495	2	0	0
T8	486	2	0	0
T9	484	2	0	0
T16	487	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	40	0	0
T1	470	2	0	0
T2	432	2	0	0
T3	465	2	0	0
T4	448	2	0	0
T5	466	2	0	0
T6	505	2	0	0
T7	495	2	0	0
T8	486	2	0	0
T9	484	2	0	0
T16	487	2	0	0

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9555	40	0	0
T1	470	2	0	0
T2	432	2	0	0
T3	465	2	0	0
T4	448	2	0	0
T5	466	2	0	0
T6	505	2	0	0
T7	495	2	0	0
T8	486	2	0	0
T9	484	2	0	0
T16	487	2	0	0