Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_receiver	94.60	100.00	91.67	100.00	90.91	94.12	90.91

---

Module Instance : prim_esc_tb.i_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
ALWAYS	172	39	39	100.00
ALWAYS	252	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
99	1	1
100	1	1
131	1	1
133	1	1
134	1	1
136	1	1
167	1	1
168	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
178	1	1
181	1	1
182	1	1
183	1	1
184	1	1
			MISSING_ELSE
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE
252	1	1
253	1	1
255	1	1

---

Cond Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_esc_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Check	182	Covered	T1,T2,T3
EscResp	194	Covered	T1,T2,T3
Idle	201	Covered	T1,T2,T3
PingResp	190	Covered	T1,T2,T3
SigInt	230	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Check->EscResp	194	Covered	T1,T2,T3
Check->PingResp	190	Covered	T1,T2,T3
Check->SigInt	240	Covered	T5,T11,T15
EscResp->Idle	213	Covered	T1,T2,T3
EscResp->SigInt	240	Covered	T3,T16,T7
Idle->Check	182	Covered	T1,T2,T3
Idle->SigInt	240	Covered	T1,T2,T3
PingResp->EscResp	206	Covered	T4,T8,T9
PingResp->Idle	201	Covered	T1,T2,T3
PingResp->SigInt	240	Not Covered
SigInt->Idle	227	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
Branches		17	16	94.12
IF	133	2	2	100.00
CASE	178	11	10	90.91
IF	239	2	2	100.00
IF	252	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	133	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (state_q)
-2-:	181	if (esc_level)
-3-:	193	if (esc_level)
-4-:	205	if (esc_level)
-5-:	214	if (esc_level)
-6-:	229	if (sigint_detected)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Idle	1	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	Covered	T1,T2,T3
Check	-	1	-	-	-	Covered	T1,T2,T3
Check	-	0	-	-	-	Covered	T1,T2,T3
PingResp	-	-	1	-	-	Covered	T4,T8,T9
PingResp	-	-	0	-	-	Covered	T1,T2,T3
EscResp	-	-	-	1	-	Covered	T1,T2,T3
EscResp	-	-	-	0	-	Covered	T1,T2,T3
SigInt	-	-	-	-	1	Covered	T1,T2,T3
SigInt	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	239	if ((sigint_detected && (state_q != SigInt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9733	5117	0	0
EscCntEsc_A	9733	20	0	0
EscCntWrap_A	9733	0	0	0
EscEnCheck_A	9733	347	0	0
EscEnKnownO_A	9733	5217	0	0
EscRespCheck_A	9733	367	0	20
PingRespCheck_A	9733	51	0	20
RespPKnownO_A	9733	5217	0	0
SigIntCheck0_A	9733	40	0	0
SigIntCheck1_A	9733	40	0	0
SigIntCheck2_A	9733	40	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	5117	0	0
T1	477	239	0	0
T2	535	254	0	0
T3	526	275	0	0
T4	504	285	0	0
T5	524	268	0	0
T7	462	272	0	0
T8	447	253	0	0
T10	499	246	0	0
T14	507	252	0	0
T16	468	257	0	0

EscCntEsc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	20	0	0
T1	477	1	0	0
T2	535	1	0	0
T3	526	1	0	0
T4	504	1	0	0
T5	524	1	0	0
T7	462	1	0	0
T8	447	1	0	0
T10	499	1	0	0
T14	507	1	0	0
T16	468	1	0	0

EscCntWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	0	0	0

EscEnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	347	0	0
T1	477	7	0	0
T2	535	23	0	0
T3	526	15	0	0
T4	504	27	0	0
T5	524	6	0	0
T7	462	22	0	0
T8	447	20	0	0
T10	499	14	0	0
T14	507	13	0	0
T16	468	9	0	0

EscEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	5217	0	0
T1	477	244	0	0
T2	535	259	0	0
T3	526	280	0	0
T4	504	290	0	0
T5	524	273	0	0
T7	462	277	0	0
T8	447	258	0	0
T10	499	251	0	0
T14	507	257	0	0
T16	468	262	0	0

EscRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	367	0	20
T1	477	8	0	1
T2	535	24	0	1
T3	526	16	0	1
T4	504	28	0	1
T5	524	7	0	1
T7	462	23	0	1
T8	447	21	0	1
T10	499	15	0	1
T14	507	14	0	1
T16	468	10	0	1

PingRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	51	0	20
T1	477	3	0	1
T2	535	2	0	1
T3	526	2	0	1
T4	504	3	0	1
T5	524	3	0	1
T7	462	3	0	1
T8	447	3	0	1
T10	499	2	0	1
T14	507	3	0	1
T16	468	2	0	1

RespPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	5217	0	0
T1	477	244	0	0
T2	535	259	0	0
T3	526	280	0	0
T4	504	290	0	0
T5	524	273	0	0
T7	462	277	0	0
T8	447	258	0	0
T10	499	251	0	0
T14	507	257	0	0
T16	468	262	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	40	0	0
T1	477	2	0	0
T2	535	2	0	0
T3	526	2	0	0
T4	504	2	0	0
T5	524	2	0	0
T7	462	2	0	0
T8	447	2	0	0
T10	499	2	0	0
T14	507	2	0	0
T16	468	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	40	0	0
T1	477	2	0	0
T2	535	2	0	0
T3	526	2	0	0
T4	504	2	0	0
T5	524	2	0	0
T7	462	2	0	0
T8	447	2	0	0
T10	499	2	0	0
T14	507	2	0	0
T16	468	2	0	0

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9733	40	0	0
T1	477	2	0	0
T2	535	2	0	0
T3	526	2	0	0
T4	504	2	0	0
T5	524	2	0	0
T7	462	2	0	0
T8	447	2	0	0
T10	499	2	0	0
T14	507	2	0	0
T16	468	2	0	0