PWM Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	533.722us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	18.498us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	196.452us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	9.000s	875.760us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	94.591us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	34.081us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	196.452us	20	20	100.00
		pwm_csr_aliasing	5.000s	94.591us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	pulse	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	blink	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	resolution	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	polarity	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	phase	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.650m	12.070ms	50	50	100.00
V2	perf	pwm_perf	50.000s	49.995ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.483m	55.757ms	48	50	96.00
V2	alert_test	pwm_alert_test	4.000s	28.441us	50	50	100.00
V2	intr_test	pwm_intr_test	4.000s	36.544us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	9.000s	458.982us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	9.000s	458.982us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	18.498us	5	5	100.00
		pwm_csr_rw	4.000s	196.452us	20	20	100.00
		pwm_csr_aliasing	5.000s	94.591us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	320.830us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	18.498us	5	5	100.00
		pwm_csr_rw	4.000s	196.452us	20	20	100.00
		pwm_csr_aliasing	5.000s	94.591us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	320.830us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	7.000s	936.313us	20	20	100.00
		pwm_sec_cm	3.000s	217.702us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	7.000s	936.313us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.49	99.08	99.88	94.86	94.92	--	100.00	99.34

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

14.pwm_stress_all.1855757894
Line 451, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/14.pwm_stress_all/latest/run.log

  UVM_ERROR @ 30487144408 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 30487144408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.pwm_stress_all.893064048
Line 414, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/37.pwm_stress_all/latest/run.log

  UVM_ERROR @ 10964911377 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 10964911377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---