PWM Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	10.000s	2.205ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	100.550us	5	5	100.00
V1	csr_rw	pwm_csr_rw	14.000s	214.777us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	1.196ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	93.074us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	17.359us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	14.000s	214.777us	20	20	100.00
		pwm_csr_aliasing	4.000s	93.074us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	pulse	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	blink	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	heartbeat	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	resolution	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	multi_channel	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	polarity	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	phase	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	lowpower	pwm_rand_output	5.817m	10.504ms	50	50	100.00
V2	perf	pwm_perf	50.000s	10.943ms	49	50	98.00
V2	stress_all	pwm_stress_all	5.067m	130.626ms	49	50	98.00
V2	alert_test	pwm_alert_test	4.000s	19.047us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	23.577us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	257.836us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	257.836us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	100.550us	5	5	100.00
		pwm_csr_rw	14.000s	214.777us	20	20	100.00
		pwm_csr_aliasing	4.000s	93.074us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	61.497us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	100.550us	5	5	100.00
		pwm_csr_rw	14.000s	214.777us	20	20	100.00
		pwm_csr_aliasing	4.000s	93.074us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	61.497us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	184.876us	20	20	100.00
		pwm_sec_cm	3.000s	207.485us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	184.876us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.62	99.59	99.26	99.92	95.34	94.92	--	100.00	99.34

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwm_perf has 1 failures.

    • 38.pwm_perf.12921861202537268487711828954004781309652989123688728625860178233793403120992
      Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_perf/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:

  • Test pwm_stress_all has 1 failures.

    • 41.pwm_stress_all.75758598200625240768576960454117065936448046984656997861542481120525205127780
      Line 3037, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/41.pwm_stress_all/latest/run.log

        UVM_ERROR @ 42891599846 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
         PWM :: Channel = [1] did not MATCH
        UVM_INFO @ 42891599846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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