PWRMGR Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.700s	31.865us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	35.273us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.660s	21.739us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.200s	419.159us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	69.083us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.580s	169.837us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.660s	21.739us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	69.083us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.620s	286.990us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.620s	286.990us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.810s	31.184us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	44.488us	49	50	98.00
V2	reset	pwrmgr_reset	1.380s	85.071us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	109.355us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.380s	85.071us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.790s	302.906us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.660s	293.185us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	49.749us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.990s	2.727ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.650s	17.519us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.490s	217.606us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.490s	217.606us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	35.273us	5	5	100.00
		pwrmgr_csr_rw	0.660s	21.739us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	69.083us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	43.586us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	35.273us	5	5	100.00
		pwrmgr_csr_rw	0.660s	21.739us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	69.083us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	43.586us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	192.253us	20	20	100.00
		pwrmgr_sec_cm	1.480s	935.577us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.480s	935.577us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.480s	935.577us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	192.253us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.240s	817.545us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.350s	893.087us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	73.514us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	43.495us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.480s	935.577us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.480s	935.577us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.480s	935.577us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.660s	50.713us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	43.607us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.700s	260.851us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.660s	21.739us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.660s	21.739us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	38.720s	9.448ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1066	1070	99.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.70	98.21	96.58	90.98	96.00	96.27	100.00	98.85

Failure Buckets

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 9.pwrmgr_lowpower_invalid.825436114
      Line 217, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  42178434 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  42178434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 27.pwrmgr_stress_all_with_rand_reset.3269112486
      Line 7356, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 47222898151 ps: (pwrmgr.sv:160) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 47222898151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 38.pwrmgr_wakeup_reset.163520353
      Line 367, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 47.pwrmgr_stress_all_with_rand_reset.2390677221
      Line 676, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 4307269975 ps: (pwrmgr.sv:155) [ASSERT FAILED] PwrmgrSecCmEscToSlowResetReq_A
        UVM_INFO @ 4307269975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.17_18.03.58
• 2023.05.16_19.27.31
• 2023.05.15_18.45.06
• 2023.05.14_18.13.20
• 2023.05.13_18.57.20
• 2023.05.12_18.48.02
• 2023.05.12_11.28.12