PWRMGR Simulation Results

Wednesday August 30 2023 19:02:21 UTC

GitHub Revision: `b0db0e290`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2889561934

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.316us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.720s	43.809us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	22.458us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.500s	314.923us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.930s	74.557us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.640s	54.215us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	22.458us	20	20	100.00
		pwrmgr_csr_aliasing	0.930s	74.557us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.650s	259.679us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.650s	259.679us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.870s	101.231us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	44.271us	50	50	100.00
V2	reset	pwrmgr_reset	1.340s	88.921us	50	50	100.00
		pwrmgr_reset_invalid	1.000s	72.522us	0	50	0.00
V2	main_power_glitch_reset	pwrmgr_reset	1.340s	88.921us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.480s	252.244us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.530s	267.467us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.970s	69.223us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.330s	1.459ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	76.017us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.820s	328.713us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.820s	328.713us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.720s	43.809us	5	5	100.00
		pwrmgr_csr_rw	0.730s	22.458us	20	20	100.00
		pwrmgr_csr_aliasing	0.930s	74.557us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	78.463us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.720s	43.809us	5	5	100.00
		pwrmgr_csr_rw	0.730s	22.458us	20	20	100.00
		pwrmgr_csr_aliasing	0.930s	74.557us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	78.463us	20	20	100.00
V2		TOTAL			489	540	90.56
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.390s	3.781ms	20	20	100.00
		pwrmgr_sec_cm	1.670s	704.787us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.670s	704.787us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.670s	704.787us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.390s	3.781ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.260s	842.406us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.360s	846.217us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	70.190us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.650s	31.322us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.670s	704.787us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.670s	704.787us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.670s	704.787us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.660s	48.724us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	52.530us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.680s	249.735us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	22.458us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	22.458us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	39.910s	9.186ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1018	1070	95.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.80	98.22	96.58	99.44	74.00	96.32	100.00	99.02

Failure Buckets

Offending '(fast_state == FastPwrStateRomCheckGood)' has 50 failures:

Test pwrmgr_reset_invalid has 50 failures.

0.pwrmgr_reset_invalid.149851324
Line 298, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  76068242 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  76068242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_reset_invalid.1182044978
Line 253, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  85742818 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  85742818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_FATAL (cip_base_vseq.sv:99) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 3.pwrmgr_stress_all_with_rand_reset.2876751823
    Line 4548, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14753062328 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
  UVM_INFO @ 14753062328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_wakeup_reset has 1 failures.
  - 42.pwrmgr_wakeup_reset.1950293828
    Line 330, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```