Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T41

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23412198	6205	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23412198	252762	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23412198	10004007	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23412198	252753	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23412198	6205	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23412198	252762	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23412198	10004007	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23412198	252753	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	6205	0	0
T1	110371	33	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	1	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	17	0	0
T19	0	44	0	0
T22	0	21	0	0
T24	0	20	0	0
T36	0	6	0	0
T37	0	21	0	0
T40	0	45	0	0
T41	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	252762	0	0
T1	110371	525	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	12	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	785	0	0
T19	0	2273	0	0
T22	0	841	0	0
T24	0	292	0	0
T36	0	391	0	0
T37	0	559	0	0
T40	0	1056	0	0
T41	0	169	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	10004007	0	0
T1	110371	57844	0	0
T2	5167	2004	0	0
T3	3007	673	0	0
T4	1355	1067	0	0
T5	2937	0	0	0
T6	7860	4864	0	0
T7	9564	4990	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	27350	0	0
T24	0	8343	0	0
T54	0	5296	0	0
T55	0	8657	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	252753	0	0
T1	110371	525	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	12	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	785	0	0
T19	0	2273	0	0
T22	0	841	0	0
T24	0	292	0	0
T36	0	391	0	0
T37	0	559	0	0
T40	0	1056	0	0
T41	0	169	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	6205	0	0
T1	110371	33	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	1	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	17	0	0
T19	0	44	0	0
T22	0	21	0	0
T24	0	20	0	0
T36	0	6	0	0
T37	0	21	0	0
T40	0	45	0	0
T41	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	252762	0	0
T1	110371	525	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	12	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	785	0	0
T19	0	2273	0	0
T22	0	841	0	0
T24	0	292	0	0
T36	0	391	0	0
T37	0	559	0	0
T40	0	1056	0	0
T41	0	169	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	10004007	0	0
T1	110371	57844	0	0
T2	5167	2004	0	0
T3	3007	673	0	0
T4	1355	1067	0	0
T5	2937	0	0	0
T6	7860	4864	0	0
T7	9564	4990	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	27350	0	0
T24	0	8343	0	0
T54	0	5296	0	0
T55	0	8657	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	252753	0	0
T1	110371	525	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	12	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	785	0	0
T19	0	2273	0	0
T22	0	841	0	0
T24	0	292	0	0
T36	0	391	0	0
T37	0	559	0	0
T40	0	1056	0	0
T41	0	169	0	0