Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23986550	14729	0	0
intr_enable_rd_A	23986550	32683	0	0
reset_en_rd_A	23986550	1118	0	0
reset_en_regwen_rd_A	23986550	1092	0	0
wake_info_capture_dis_rd_A	23986550	988	0	0
wakeup_en_rd_A	23986550	1668	0	0
wakeup_en_regwen_rd_A	23986550	935	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	14729	0	0
T1	110371	1	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	0	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	0	0	0
T19	0	31	0	0
T20	0	12	0	0
T46	0	39	0	0
T47	0	4	0	0
T48	0	10	0	0
T57	0	62	0	0
T78	0	6	0	0
T119	0	30	0	0
T120	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	32683	0	0
T3	3007	47	0	0
T4	1355	4	0	0
T5	2937	0	0	0
T6	7860	53	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	0	0	0
T22	0	177	0	0
T23	0	24	0	0
T24	0	185	0	0
T35	0	12	0	0
T38	0	37	0	0
T54	10157	0	0	0
T71	0	103	0	0
T118	4827	0	0	0
T121	0	21	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	1118	0	0
T49	0	64	0	0
T50	0	11	0	0
T51	0	8	0	0
T59	0	116	0	0
T63	0	3	0	0
T78	0	4	0	0
T81	0	13	0	0
T82	0	11	0	0
T111	0	48	0	0
T119	678502	1	0	0
T122	1379	0	0	0
T123	6110	0	0	0
T124	48626	0	0	0
T125	20489	0	0	0
T126	876	0	0	0
T127	4319	0	0	0
T128	1241	0	0	0
T129	4106	0	0	0
T130	32660	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	1092	0	0
T49	0	53	0	0
T50	0	14	0	0
T51	0	22	0	0
T59	0	90	0	0
T63	0	13	0	0
T78	0	6	0	0
T81	0	7	0	0
T82	0	29	0	0
T111	0	42	0	0
T119	678502	4	0	0
T122	1379	0	0	0
T123	6110	0	0	0
T124	48626	0	0	0
T125	20489	0	0	0
T126	876	0	0	0
T127	4319	0	0	0
T128	1241	0	0	0
T129	4106	0	0	0
T130	32660	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	988	0	0
T49	0	43	0	0
T50	0	17	0	0
T51	0	13	0	0
T59	0	74	0	0
T63	0	9	0	0
T78	0	4	0	0
T81	0	10	0	0
T82	0	43	0	0
T111	0	52	0	0
T119	678502	4	0	0
T122	1379	0	0	0
T123	6110	0	0	0
T124	48626	0	0	0
T125	20489	0	0	0
T126	876	0	0	0
T127	4319	0	0	0
T128	1241	0	0	0
T129	4106	0	0	0
T130	32660	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	1668	0	0
T49	0	177	0	0
T50	0	3	0	0
T51	0	8	0	0
T59	0	313	0	0
T63	0	6	0	0
T78	0	1	0	0
T81	0	52	0	0
T82	0	31	0	0
T111	0	41	0	0
T119	678502	13	0	0
T122	1379	0	0	0
T123	6110	0	0	0
T124	48626	0	0	0
T125	20489	0	0	0
T126	876	0	0	0
T127	4319	0	0	0
T128	1241	0	0	0
T129	4106	0	0	0
T130	32660	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986550	935	0	0
T49	0	45	0	0
T50	0	5	0	0
T51	0	11	0	0
T59	0	83	0	0
T63	0	3	0	0
T78	0	9	0	0
T81	0	7	0	0
T82	0	32	0	0
T111	0	30	0	0
T119	678502	15	0	0
T122	1379	0	0	0
T123	6110	0	0	0
T124	48626	0	0	0
T125	20489	0	0	0
T126	876	0	0	0
T127	4319	0	0	0
T128	1241	0	0	0
T129	4106	0	0	0
T130	32660	0	0	0