Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	23412198	52394	0	0
IoStatusRise_A	23412198	58301	0	0
MainStatusFall_A	23412198	52394	0	0
MainStatusRise_A	23412198	58302	0	0
UsbStatusFall_A	23412198	40045	0	0
UsbStatusRise_A	23412198	44892	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	52394	0	0
T1	110371	462	0	0
T2	5167	4	0	0
T3	3007	17	0	0
T4	1355	2	0	0
T5	2937	5	0	0
T6	7860	17	0	0
T7	9564	8	0	0
T8	4763	18	0	0
T9	785	1	0	0
T10	60625	136	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	58301	0	0
T1	110371	519	0	0
T2	5167	5	0	0
T3	3007	18	0	0
T4	1355	3	0	0
T5	2937	6	0	0
T6	7860	18	0	0
T7	9564	9	0	0
T8	4763	20	0	0
T9	785	3	0	0
T10	60625	148	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	52394	0	0
T1	110371	462	0	0
T2	5167	4	0	0
T3	3007	17	0	0
T4	1355	2	0	0
T5	2937	5	0	0
T6	7860	17	0	0
T7	9564	8	0	0
T8	4763	18	0	0
T9	785	1	0	0
T10	60625	136	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	58302	0	0
T1	110371	519	0	0
T2	5167	5	0	0
T3	3007	18	0	0
T4	1355	3	0	0
T5	2937	6	0	0
T6	7860	18	0	0
T7	9564	9	0	0
T8	4763	20	0	0
T9	785	3	0	0
T10	60625	148	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	40045	0	0
T1	110371	385	0	0
T2	5167	3	0	0
T3	3007	17	0	0
T4	1355	2	0	0
T5	2937	5	0	0
T6	7860	16	0	0
T7	9564	6	0	0
T8	4763	18	0	0
T9	785	1	0	0
T10	60625	93	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	44892	0	0
T1	110371	433	0	0
T2	5167	3	0	0
T3	3007	18	0	0
T4	1355	3	0	0
T5	2937	6	0	0
T6	7860	16	0	0
T7	9564	7	0	0
T8	4763	20	0	0
T9	785	3	0	0
T10	60625	102	0	0