Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	23412198	57924	0	0
RomAllowCheckGoodState_A	23412198	57974	0	0
RomBlockActiveState_A	23412198	29876	0	0
RomBlockCheckGoodState_A	23412198	414456	0	0
RomIntgChkDisFalse_A	23412198	22732385	0	0
RomIntgChkDisTrue_A	23412198	171904	0	0
RstreqChkEsctimeout_A	23412198	4020	0	0
RstreqChkFsmterm_A	23412198	140	0	0
RstreqChkGlbesc_A	23412198	4022	0	0
RstreqChkMainpd_A	23412198	950031	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	57924	0	0
T1	110371	518	0	0
T2	5167	5	0	0
T3	3007	18	0	0
T4	1355	3	0	0
T5	2937	6	0	0
T6	7860	18	0	0
T7	9564	9	0	0
T8	4763	13	0	0
T9	785	3	0	0
T10	60625	148	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	57974	0	0
T1	110371	518	0	0
T2	5167	5	0	0
T3	3007	18	0	0
T4	1355	3	0	0
T5	2937	6	0	0
T6	7860	18	0	0
T7	9564	9	0	0
T8	4763	14	0	0
T9	785	3	0	0
T10	60625	148	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	29876	0	0
T19	415622	0	0	0
T21	1538	134	0	0
T23	1781	204	0	0
T35	2972	0	0	0
T36	19853	0	0	0
T37	20667	4	0	0
T38	3086	0	0	0
T39	1607	287	0	0
T40	41642	0	0	0
T41	1685	0	0	0
T71	0	5	0	0
T74	0	16	0	0
T125	0	39	0	0
T131	0	304	0	0
T132	0	912	0	0
T133	0	1152	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	414456	0	0
T1	110371	1102	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	0	0	0
T5	2937	0	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	0	0	0
T9	785	0	0	0
T10	60625	779	0	0
T19	0	1397	0	0
T21	0	9	0	0
T22	0	2249	0	0
T23	0	26	0	0
T24	0	624	0	0
T36	0	414	0	0
T37	0	1321	0	0
T39	0	83	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	22732385	0	0
T1	110371	106170	0	0
T2	5167	5107	0	0
T3	3007	2911	0	0
T4	1355	1258	0	0
T5	2937	2881	0	0
T6	7860	7780	0	0
T7	9564	9464	0	0
T8	4763	3838	0	0
T9	785	647	0	0
T10	60625	59738	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	171904	0	0
T19	415622	0	0	0
T21	1538	278	0	0
T22	37632	2311	0	0
T23	1781	312	0	0
T35	2972	0	0	0
T36	19853	0	0	0
T37	20667	0	0	0
T38	3086	0	0	0
T39	1607	68	0	0
T41	1685	0	0	0
T71	0	258	0	0
T74	0	290	0	0
T131	0	259	0	0
T132	0	2508	0	0
T133	0	438	0	0
T134	0	1181	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	4020	0	0
T1	110371	21	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	0	0	0
T5	2937	1	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	7	0	0
T9	785	1	0	0
T10	60625	4	0	0
T21	0	4	0	0
T23	0	2	0	0
T35	0	3	0	0
T38	0	2	0	0
T39	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	140	0	0
T16	9047	20	0	0
T17	8118	20	0	0
T18	0	40	0	0
T25	0	40	0	0
T26	0	20	0	0
T27	2661	0	0	0
T28	1718	0	0	0
T29	6648	0	0	0
T30	3476	0	0	0
T31	21854	0	0	0
T32	17166	0	0	0
T33	60749	0	0	0
T34	18539	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	4022	0	0
T1	110371	21	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	0	0	0
T5	2937	1	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	7	0	0
T9	785	1	0	0
T10	60625	4	0	0
T21	0	4	0	0
T23	0	2	0	0
T35	0	3	0	0
T38	0	2	0	0
T39	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23412198	950031	0	0
T1	110371	813	0	0
T2	5167	0	0	0
T3	3007	0	0	0
T4	1355	0	0	0
T5	2937	206	0	0
T6	7860	0	0	0
T7	9564	0	0	0
T8	4763	112	0	0
T9	785	0	0	0
T10	60625	2288	0	0
T21	0	97	0	0
T22	0	3325	0	0
T24	0	827	0	0
T35	0	272	0	0
T36	0	1301	0	0
T37	0	2530	0	0