ROM_CTRL Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	34.340s	15.803ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.330s	6.213ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.480s	2.218ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.050s	3.080ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.440s	2.508ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.230s	26.345ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.480s	2.218ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.440s	2.508ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.160s	8.540ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.930s	4.082ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.970s	4.134ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.240m	14.503ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.620s	8.990ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.220s	42.951ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.340s	3.534ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.340s	3.534ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.330s	6.213ms	5	5	100.00
		rom_ctrl_csr_rw	14.480s	2.218ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.440s	2.508ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.300s	8.576ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.330s	6.213ms	5	5	100.00
		rom_ctrl_csr_rw	14.480s	2.218ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.440s	2.508ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.300s	8.576ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.305m	44.847ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.718m	2.401ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.233m	18.957ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.718m	2.401ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.718m	2.401ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.718m	2.401ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	34.340s	15.803ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	34.340s	15.803ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	34.340s	15.803ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.233m	18.957ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
		rom_ctrl_kmac_err_chk	30.620s	8.990ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.675m	47.450ms	46	50	92.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.305m	44.847ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.718m	2.401ms	5	5	100.00
V2S		TOTAL			90	95	94.74
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.793h	84.548ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			479	500	95.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.63	97.16	92.68	97.88	86.67	98.36	98.04	98.61

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 12 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.1467256230
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:150c3725-158c-4d7c-a3a8-313f6bddf66c
```
  - 2.rom_ctrl_stress_all_with_rand_reset.21247881
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a2faa052-fd55-497b-838d-7ec47056b864
```
  - ... and 10 more failures.

UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 3 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

7.rom_ctrl_corrupt_sig_fatal_chk.1274305761
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 774472487 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 774472487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.rom_ctrl_corrupt_sig_fatal_chk.2087359428
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 106075127 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 106075127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test rom_ctrl_smoke has 2 failures.

18.rom_ctrl_smoke.2153523330
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/18.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10006757800 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x533df361
  UVM_INFO @ 10006757800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.rom_ctrl_smoke.2249302324
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/48.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10008023178 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe24cafd6
  UVM_INFO @ 10008023178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

35.rom_ctrl_stress_all_with_rand_reset.2049151295
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10013932598 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x7d175edc
  UVM_INFO @ 10013932598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

32.rom_ctrl_corrupt_sig_fatal_chk.3334515528
Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 30084583451 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 30084583451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_kmac_err_chk has 1 failures.

40.rom_ctrl_kmac_err_chk.1373098208
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/40.rom_ctrl_kmac_err_chk/latest/run.log

  UVM_ERROR @ 3316804819 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3316804819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 12.rom_ctrl_passthru_mem_tl_intg_err.2879181323
    Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10010169428 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9b988000
  UVM_INFO @ 10010169428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```