Line Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
CONT_ASSIGN | 323 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 438 | 1 | 1 | 100.00 |
CONT_ASSIGN | 441 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 443 | 1 | 1 | 100.00 |
CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
CONT_ASSIGN | 449 | 1 | 1 | 100.00 |
CONT_ASSIGN | 453 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
117 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
222 |
1 |
1 |
268 |
1 |
1 |
323 |
1 |
1 |
425 |
8 |
8 |
426 |
8 |
8 |
428 |
8 |
8 |
429 |
8 |
8 |
431 |
8 |
8 |
432 |
8 |
8 |
436 |
1 |
1 |
438 |
1 |
1 |
441 |
1 |
1 |
442 |
1 |
1 |
443 |
1 |
1 |
444 |
1 |
1 |
449 |
1 |
1 |
453 |
1 |
1 |
Cond Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Conditions | 58 | 57 | 98.28 |
Logical | 58 | 57 | 98.28 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 222
EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 268
EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
---------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T19 |
1 | 1 | Covered | T1,T3,T4 |
LINE 429
EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (0[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (1[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (2[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (3[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (4[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (5[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (6[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (7[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 436
EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
-----------1----------- ---------2--------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T2,T37,T38 |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Unreachable | |
LINE 438
EXPRESSION (checker_alert | mux_alert)
------1------ ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T19 |
1 | 0 | Covered | T2,T5,T7 |
LINE 449
EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T39,T40,T41 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T39,T40,T41 |
LINE 453
EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
---------1--------- ------2------ ----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T5,T7,T19 |
0 | 1 | 0 | Covered | T2,T5,T7 |
1 | 0 | 0 | Covered | T2,T37,T38 |
Toggle Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Totals |
61 |
56 |
91.80 |
Total Bits |
2882 |
2805 |
97.33 |
Total Bits 0->1 |
1441 |
1402 |
97.29 |
Total Bits 1->0 |
1441 |
1403 |
97.36 |
| | | |
Ports |
61 |
56 |
91.80 |
Port Bits |
2882 |
2805 |
97.33 |
Port Bits 0->1 |
1441 |
1402 |
97.29 |
Port Bits 1->0 |
1441 |
1403 |
97.36 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
rst_ni |
Yes |
Yes |
T28,T33,T36 |
Yes |
T20,T28,T29 |
INPUT |
rom_cfg_i.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
rom_cfg_i.cfg_en |
No |
No |
|
No |
|
INPUT |
rom_tl_i.d_ready |
Yes |
Yes |
T28,T29,T30 |
Yes |
T20,T28,T29 |
INPUT |
rom_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
INPUT |
rom_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
INPUT |
rom_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T20,T32,T42 |
Yes |
T20,T32,T42 |
INPUT |
rom_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_data[31:0] |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
INPUT |
rom_tl_i.a_mask[3:0] |
Yes |
Yes |
T20,T32,T33 |
Yes |
T20,T32,T33 |
INPUT |
rom_tl_i.a_address[31:0] |
Yes |
Yes |
T20,T32,T33 |
Yes |
T20,T32,T33 |
INPUT |
rom_tl_i.a_source[7:0] |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
INPUT |
rom_tl_i.a_size[1:0] |
Yes |
Yes |
T20,T32,T33 |
Yes |
T20,T32,T33 |
INPUT |
rom_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_opcode[2:0] |
Yes |
Yes |
T20,T32,T33 |
Yes |
T20,T32,T33 |
INPUT |
rom_tl_i.a_valid |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
INPUT |
rom_tl_o.a_ready |
Yes |
Yes |
T28,T32,T33 |
Yes |
T20,T28,T29 |
OUTPUT |
rom_tl_o.d_error |
Yes |
Yes |
T20,T32,T33 |
Yes |
T20,T32,T33 |
OUTPUT |
rom_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T28,T36,T43 |
Yes |
T28,T36,T43 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
T20,*T28,T32 |
Yes |
T20,T28,T32 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_data[31:0] |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
OUTPUT |
rom_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_source[7:0] |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
OUTPUT |
rom_tl_o.d_size[1:0] |
Yes |
Yes |
T20,T32,T33 |
Yes |
T20,T32,T33 |
OUTPUT |
rom_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_opcode[0] |
Yes |
Yes |
*T20,*T32,*T33 |
Yes |
T20,T32,T33 |
OUTPUT |
rom_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_valid |
Yes |
Yes |
T20,T28,T32 |
Yes |
T20,T28,T32 |
OUTPUT |
regs_tl_i.d_ready |
Yes |
Yes |
T28,T29,T30 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T20,T29,T32 |
Yes |
T20,T29,T32 |
INPUT |
regs_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_data[31:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_mask[3:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_address[31:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_source[7:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_size[1:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_opcode[2:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_i.a_valid |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
regs_tl_o.a_ready |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
regs_tl_o.d_error |
Yes |
Yes |
T33,T44,T45 |
Yes |
T20,T32,T33 |
OUTPUT |
regs_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T20,*T28,*T29 |
Yes |
T20,T28,T29 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_data[31:0] |
Yes |
Yes |
T28,T29,T30 |
Yes |
T20,T28,T29 |
OUTPUT |
regs_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_source[7:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
regs_tl_o.d_size[1:0] |
Yes |
Yes |
T20,T28,T30 |
Yes |
T20,T28,T30 |
OUTPUT |
regs_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_opcode[0] |
Yes |
Yes |
*T20,*T28,*T31 |
Yes |
T20,T28,T29 |
OUTPUT |
regs_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_valid |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T28,T29,T30 |
Yes |
T28,T29,T30 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T28,T29,T30 |
Yes |
T28,T29,T30 |
OUTPUT |
pwrmgr_data_o.good[3:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
pwrmgr_data_o.done[3:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T28,T36,T43 |
OUTPUT |
keymgr_data_o.valid |
Yes |
Yes |
T28,T36,T43 |
Yes |
T20,T28,T29 |
OUTPUT |
keymgr_data_o.data[255:0] |
Yes |
Yes |
T28,T36,T43 |
Yes |
T20,T28,T29 |
OUTPUT |
kmac_data_i.error |
No |
Yes |
T16,T11,T17 |
No |
|
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T28,T36,T43 |
Yes |
T28,T36,T43 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T28,T36,T43 |
Yes |
T28,T36,T43 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
INPUT |
kmac_data_o.last |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
kmac_data_o.strb[7:0] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.data[38:0] |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
kmac_data_o.data[63:39] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T20,T28,T29 |
Yes |
T20,T28,T29 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
222 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 222 (tl_rom_h2d_upstream.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rom_ctrl
Assertion Details
AlertTxOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
BusRomIndicesMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288156707 |
287981193 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240439 |
240154 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297507 |
297243 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
FpvSecCmFifoRptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
0 |
0 |
0 |
FpvSecCmFifoWptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
60 |
0 |
0 |
T2 |
165481 |
20 |
0 |
0 |
T3 |
157624 |
0 |
0 |
0 |
T4 |
30664 |
0 |
0 |
0 |
T5 |
240477 |
0 |
0 |
0 |
T6 |
459140 |
0 |
0 |
0 |
T7 |
297538 |
0 |
0 |
0 |
T8 |
595046 |
0 |
0 |
0 |
T9 |
102662 |
0 |
0 |
0 |
T10 |
9282 |
0 |
0 |
0 |
T16 |
196236 |
0 |
0 |
0 |
T37 |
0 |
10 |
0 |
0 |
T38 |
0 |
10 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
KeymgrDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
109608962 |
0 |
0 |
T1 |
121309 |
5295 |
0 |
0 |
T2 |
165481 |
24 |
0 |
0 |
T3 |
157624 |
126106 |
0 |
0 |
T4 |
30664 |
3549 |
0 |
0 |
T5 |
240477 |
6532 |
0 |
0 |
T6 |
459140 |
451571 |
0 |
0 |
T7 |
297538 |
18854 |
0 |
0 |
T8 |
595046 |
469590 |
0 |
0 |
T9 |
102662 |
915 |
0 |
0 |
T10 |
9282 |
1026 |
0 |
0 |
KeymgrDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
KeymgrDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
KeymgrValidChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
0 |
0 |
337 |
KmacDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
178246810 |
0 |
0 |
T1 |
121309 |
120697 |
0 |
0 |
T2 |
165481 |
159286 |
0 |
0 |
T3 |
157624 |
314832 |
0 |
0 |
T4 |
30664 |
26531 |
0 |
0 |
T5 |
240477 |
239284 |
0 |
0 |
T6 |
459140 |
75358 |
0 |
0 |
T7 |
297538 |
295171 |
0 |
0 |
T8 |
595046 |
125404 |
0 |
0 |
T9 |
102662 |
101624 |
0 |
0 |
T10 |
9282 |
8184 |
0 |
0 |
KmacDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
KmacDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
PwrmgrDataChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
0 |
0 |
337 |
PwrmgrDataOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
RegsTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
RegsTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
12172026 |
0 |
0 |
T1 |
121309 |
128 |
0 |
0 |
T2 |
165481 |
20 |
0 |
0 |
T3 |
157624 |
381224 |
0 |
0 |
T4 |
30664 |
64 |
0 |
0 |
T5 |
240477 |
34 |
0 |
0 |
T6 |
459140 |
383904 |
0 |
0 |
T7 |
297538 |
126 |
0 |
0 |
T8 |
595046 |
277130 |
0 |
0 |
T9 |
102662 |
0 |
0 |
0 |
T10 |
9282 |
0 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T26 |
0 |
32 |
0 |
0 |
RegsTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
RegsTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
RomTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
RomTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
20735797 |
0 |
0 |
T1 |
121309 |
280 |
0 |
0 |
T2 |
165481 |
0 |
0 |
0 |
T3 |
157624 |
98348 |
0 |
0 |
T4 |
30664 |
507 |
0 |
0 |
T5 |
240477 |
12 |
0 |
0 |
T6 |
459140 |
482736 |
0 |
0 |
T7 |
297538 |
9 |
0 |
0 |
T8 |
595046 |
176695 |
0 |
0 |
T9 |
102662 |
122 |
0 |
0 |
T10 |
9282 |
339 |
0 |
0 |
T27 |
0 |
326 |
0 |
0 |
RomTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
RomTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
287989096 |
0 |
0 |
T1 |
121309 |
121261 |
0 |
0 |
T2 |
165481 |
161172 |
0 |
0 |
T3 |
157624 |
157610 |
0 |
0 |
T4 |
30664 |
30151 |
0 |
0 |
T5 |
240477 |
240160 |
0 |
0 |
T6 |
459140 |
459126 |
0 |
0 |
T7 |
297538 |
297250 |
0 |
0 |
T8 |
595046 |
595033 |
0 |
0 |
T9 |
102662 |
102591 |
0 |
0 |
T10 |
9282 |
9231 |
0 |
0 |
StabilityChkKmac_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
178244193 |
0 |
0 |
T1 |
121309 |
120696 |
0 |
0 |
T2 |
165481 |
159225 |
0 |
0 |
T3 |
157624 |
314826 |
0 |
0 |
T4 |
30664 |
26524 |
0 |
0 |
T5 |
240477 |
239280 |
0 |
0 |
T6 |
459140 |
75347 |
0 |
0 |
T7 |
297538 |
295167 |
0 |
0 |
T8 |
595046 |
125403 |
0 |
0 |
T9 |
102662 |
101623 |
0 |
0 |
T10 |
9282 |
8183 |
0 |
0 |
StabilityChkkeymgr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
109607627 |
0 |
0 |
T1 |
121309 |
5289 |
0 |
0 |
T2 |
165481 |
10 |
0 |
0 |
T3 |
157624 |
126106 |
0 |
0 |
T4 |
30664 |
3546 |
0 |
0 |
T5 |
240477 |
6513 |
0 |
0 |
T6 |
459140 |
451570 |
0 |
0 |
T7 |
297538 |
18840 |
0 |
0 |
T8 |
595046 |
469590 |
0 |
0 |
T9 |
102662 |
914 |
0 |
0 |
T10 |
9282 |
1025 |
0 |
0 |
TlAccessChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
178380134 |
0 |
0 |
T1 |
121309 |
120732 |
0 |
0 |
T2 |
165481 |
161148 |
0 |
0 |
T3 |
157624 |
315041 |
0 |
0 |
T4 |
30664 |
26602 |
0 |
0 |
T5 |
240477 |
239507 |
0 |
0 |
T6 |
459140 |
75551 |
0 |
0 |
T7 |
297538 |
295365 |
0 |
0 |
T8 |
595046 |
125443 |
0 |
0 |
T9 |
102662 |
101676 |
0 |
0 |
T10 |
9282 |
8205 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
60 |
0 |
0 |
T2 |
165481 |
20 |
0 |
0 |
T3 |
157624 |
0 |
0 |
0 |
T4 |
30664 |
0 |
0 |
0 |
T5 |
240477 |
0 |
0 |
0 |
T6 |
459140 |
0 |
0 |
0 |
T7 |
297538 |
0 |
0 |
0 |
T8 |
595046 |
0 |
0 |
0 |
T9 |
102662 |
0 |
0 |
0 |
T10 |
9282 |
0 |
0 |
0 |
T16 |
196236 |
0 |
0 |
0 |
T37 |
0 |
10 |
0 |
0 |
T38 |
0 |
10 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
513 |
0 |
0 |
T2 |
165481 |
20 |
0 |
0 |
T3 |
157624 |
0 |
0 |
0 |
T4 |
30664 |
0 |
0 |
0 |
T5 |
240477 |
16 |
0 |
0 |
T6 |
459140 |
0 |
0 |
0 |
T7 |
297538 |
15 |
0 |
0 |
T8 |
595046 |
0 |
0 |
0 |
T9 |
102662 |
0 |
0 |
0 |
T10 |
9282 |
0 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T16 |
196236 |
0 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T48 |
0 |
5 |
0 |
0 |
T49 |
0 |
15 |
0 |
0 |
T50 |
0 |
5 |
0 |
0 |
T51 |
0 |
5 |
0 |
0 |
T52 |
0 |
5 |
0 |
0 |
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288170688 |
0 |
0 |
0 |