SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rom_ctrl_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.98 | 100.00 | 98.28 | 97.33 | 100.00 | 79.31 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 328420501 | 3757477 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 328420501 | 3757477 | 0 | 0 |
T20 | 160217 | 411 | 0 | 0 |
T28 | 187293 | 0 | 0 | 0 |
T29 | 69529 | 0 | 0 | 0 |
T30 | 150945 | 0 | 0 | 0 |
T31 | 8375 | 0 | 0 | 0 |
T32 | 86306 | 611 | 0 | 0 |
T33 | 66968 | 3 | 0 | 0 |
T34 | 53564 | 0 | 0 | 0 |
T35 | 191891 | 0 | 0 | 0 |
T36 | 388134 | 0 | 0 | 0 |
T42 | 0 | 257 | 0 | 0 |
T44 | 0 | 5 | 0 | 0 |
T45 | 0 | 1 | 0 | 0 |
T53 | 0 | 851 | 0 | 0 |
T54 | 0 | 296 | 0 | 0 |
T55 | 0 | 7 | 0 | 0 |
T56 | 0 | 959 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |