ROM_CTRL Simulation Results

Wednesday October 04 2023 19:02:35 UTC

GitHub Revision: `1522c8119`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1107990535

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	44.680s	8.398ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	20.670s	2.180ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.570s	5.189ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.850s	1.281ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.900s	9.176ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.150s	2.212ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.570s	5.189ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.900s	9.176ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.500s	7.947ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.240s	10.873ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.790s	4.335ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.812m	13.007ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.210s	8.716ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.230s	2.146ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.520s	2.192ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.520s	2.192ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	20.670s	2.180ms	5	5	100.00
		rom_ctrl_csr_rw	16.570s	5.189ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.900s	9.176ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.780s	4.225ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	20.670s	2.180ms	5	5	100.00
		rom_ctrl_csr_rw	16.570s	5.189ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.900s	9.176ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.780s	4.225ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.711m	44.803ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.997m	1.443ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.451m	9.160ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.997m	1.443ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.997m	1.443ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.997m	1.443ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	44.680s	8.398ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	44.680s	8.398ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	44.680s	8.398ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.451m	9.160ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.210s	8.716ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.756m	57.940ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.711m	44.803ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.997m	1.443ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.284h	405.740ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			485	500	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.49	97.11	92.68	97.88	100.00	98.37	98.04	98.38

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 12 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.1312599659
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c06dd34d-e980-48f2-a2c0-1b2aa2455dd3
```
  - 12.rom_ctrl_stress_all_with_rand_reset.3883418403
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:016840b8-202e-4aac-9114-9ec494ed3c66
```
  - ... and 10 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.

3.rom_ctrl_passthru_mem_tl_intg_err.3463317158
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10007000821 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1d628000
  UVM_INFO @ 10007000821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all_with_rand_reset has 2 failures.

20.rom_ctrl_stress_all_with_rand_reset.344620636
Line 211, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10870958146 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x71c22bee
  UVM_INFO @ 10870958146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.rom_ctrl_stress_all_with_rand_reset.1105740840
Line 212, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 11842813596 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1bf33793
  UVM_INFO @ 11842813596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---