Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.43	96.89	84.90	97.17	93.33	96.41	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	94.37	100.00	95.37	90.00	93.33	96.61	90.91
gen_rom_scramble_enabled.u_rom	98.21	92.86		100.00		100.00	100.00
regs_tlul_assert_device	95.24	100.00				85.71	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.65	99.41	98.82	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	87.21	90.72	62.40	92.59		90.36	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
122	1	1
123	1	1
124	1	1
125	1	1
128	1	1
222	1	1
268	1	1
323	1	1
425	8	8
426	8	8
428	8	8
429	8	8
431	8	8
432	8	8
436	1	1
438	1	1
441	1	1
442	1	1
443	1	1
444	1	1
449	1	1
453	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       222
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       268
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T3,T4,T5

 LINE       429
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T27,T28,T29
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       438
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T2,T4,T7

 LINE       449
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T14

 LINE       453
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T7,T9
0	1	0	Covered	T2,T4,T7
1	0	0	Covered	T27,T28,T29

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T18,T19,T20	Yes	T17,T18,T19	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T17,T18,T22	Yes	T17,T18,T22	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T17,T18,T22	Yes	T17,T18,T19	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_i.a_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rom_tl_o.a_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
rom_tl_o.d_error	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T17,T18,T22	Yes	T17,T18,T22	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T17,T18,T19	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_i.a_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
regs_tl_o.a_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_error	Yes	Yes	T18,T19,T23	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T17,T18,T19	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T17,T18,T19	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T17,T18,T19	Yes	T30,T31,T32	OUTPUT
keymgr_data_o.valid	Yes	Yes	T30,T31,T32	Yes	T17,T18,T19	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
kmac_data_i.error	No	Yes	T2,T15,T16	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
kmac_data_i.done	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
kmac_data_i.ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
kmac_data_o.last	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	222	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	222	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	206613945	206394740	0	0
BusRomIndicesMatch_A	206606995	206391140	0	0
FpvSecCmFifoRptrCheck_A	206613945	0	0	0
FpvSecCmFifoWptrCheck_A	206613945	0	0	0
FpvSecCmRegWeOnehotCheck_A	206613945	100	0	0
KeymgrDataODataKnown_A	206613945	503435	0	0
KeymgrDataODataKnown_AKnownEnable	206613945	206394740	0	0
KeymgrDataOValidKnown_A	206613945	206394740	0	0
KeymgrValidChk_A	206613945	0	0	305
KmacDataODataKnown_A	206613945	205746280	0	0
KmacDataODataKnown_AKnownEnable	206613945	206394740	0	0
KmacDataOValidKnown_A	206613945	206394740	0	0
PwrmgrDataChk_A	206613945	0	0	305
PwrmgrDataOKnown_A	206613945	206394740	0	0
RegsTlOAReadyKnown_A	206613945	206394740	0	0
RegsTlODDataKnown_A	206613945	18770	0	0
RegsTlODDataKnown_AKnownEnable	206613945	206394740	0	0
RegsTlODValidKnown_A	206613945	206394740	0	0
RomTlOAReadyKnown_A	206613945	206394740	0	0
RomTlODDataKnown_A	206613945	42000	0	0
RomTlODDataKnown_AKnownEnable	206613945	206394740	0	0
RomTlODValidKnown_A	206613945	206394740	0	0
StabilityChkKmac_A	206613945	205743425	0	0
StabilityChkkeymgr_A	206613945	502320	0	0
TlAccessChk_A	206613945	205891305	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	206613945	100	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	206613945	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	206613945	850	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	206613945	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206606995	206391140	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293368	293054	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293368	293054	0	0
T8	263142	262996	0	0
T9	293368	293054	0	0
T10	131208	131128	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	100	0	0
T27	144679	20	0	0
T28	144679	20	0	0
T29	0	20	0	0
T33	0	20	0	0
T34	0	20	0	0
T35	293381	0	0	0
T36	132368	0	0	0
T37	132368	0	0	0
T38	263142	0	0	0
T39	293381	0	0	0
T40	131208	0	0	0
T41	261813	0	0	0
T42	263142	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	503435	0	0
T1	131208	115	0	0
T2	261813	115	0	0
T3	395461	1907	0	0
T4	293381	5218	0	0
T5	395461	1907	0	0
T6	263142	1426	0	0
T7	293381	5218	0	0
T8	263142	1426	0	0
T9	293381	5218	0	0
T10	131208	115	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	0	0	305

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	205746280	0	0
T1	131208	130931	0	0
T2	261813	261362	0	0
T3	395461	393086	0	0
T4	293381	292342	0	0
T5	395461	393086	0	0
T6	263142	261409	0	0
T7	293381	292342	0	0
T8	263142	261409	0	0
T9	293381	292342	0	0
T10	131208	130931	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	0	0	305

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	18770	0	0
T1	131208	73	0	0
T2	261813	1	0	0
T3	395461	84	0	0
T4	293381	118	0	0
T5	395461	84	0	0
T6	263142	94	0	0
T7	293381	118	0	0
T8	263142	94	0	0
T9	293381	118	0	0
T10	131208	73	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	42000	0	0
T3	395461	256	0	0
T4	293381	17	0	0
T5	395461	256	0	0
T6	263142	297	0	0
T7	293381	17	0	0
T8	263142	297	0	0
T9	293381	17	0	0
T10	131208	0	0	0
T11	293381	17	0	0
T12	0	270	0	0
T13	0	256	0	0
T14	131208	0	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	206394740	0	0
T1	131208	131128	0	0
T2	261813	261662	0	0
T3	395461	395189	0	0
T4	293381	293061	0	0
T5	395461	395189	0	0
T6	263142	262996	0	0
T7	293381	293061	0	0
T8	263142	262996	0	0
T9	293381	293061	0	0
T10	131208	131128	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	205743425	0	0
T1	131208	130930	0	0
T2	261813	261360	0	0
T3	395461	393082	0	0
T4	293381	292337	0	0
T5	395461	393082	0	0
T6	263142	261407	0	0
T7	293381	292337	0	0
T8	263142	261407	0	0
T9	293381	292337	0	0
T10	131208	130930	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	502320	0	0
T1	131208	114	0	0
T2	261813	114	0	0
T3	395461	1904	0	0
T4	293381	5205	0	0
T5	395461	1904	0	0
T6	263142	1424	0	0
T7	293381	5205	0	0
T8	263142	1424	0	0
T9	293381	5205	0	0
T10	131208	114	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	205891305	0	0
T1	131208	131013	0	0
T2	261813	261547	0	0
T3	395461	393282	0	0
T4	293381	292539	0	0
T5	395461	393282	0	0
T6	263142	261570	0	0
T7	293381	292539	0	0
T8	263142	261570	0	0
T9	293381	292539	0	0
T10	131208	131013	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	100	0	0
T27	144679	20	0	0
T28	144679	20	0	0
T29	0	20	0	0
T33	0	20	0	0
T34	0	20	0	0
T35	293381	0	0	0
T36	132368	0	0	0
T37	132368	0	0	0
T38	263142	0	0	0
T39	293381	0	0	0
T40	131208	0	0	0
T41	261813	0	0	0
T42	263142	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	850	0	0
T4	293381	15	0	0
T5	395461	0	0	0
T6	263142	0	0	0
T7	293381	15	0	0
T8	263142	0	0	0
T9	293381	15	0	0
T10	131208	0	0	0
T11	293381	15	0	0
T12	132368	0	0	0
T14	131208	0	0	0
T43	0	15	0	0
T44	0	15	0	0
T45	0	15	0	0
T46	0	15	0	0
T47	0	15	0	0
T48	0	15	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206613945	0	0	0