Unified Coverage Report :: Module :: rom_ctrl_rom_reg_top

Module : rom_ctrl_rom_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_rom_top	100.00	100.00				100.00

---

Module Instance : tb.dut.u_rom_top

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	98.28	97.33		100.00	79.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_rom_reg_top

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	36	3	3	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	65	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
36	1	1
37	1	1
39	1	1
59	1	1
60	1	1
65		unreachable

---

Branch Coverage for Module : rom_ctrl_rom_reg_top

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	36	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	36	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19