ROM_CTRL Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 29.610s 6.265ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 16.000s 3.139ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 12.580s 3.124ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 13.110s 3.124ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 12.360s 3.124ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 12.680s 3.135ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 12.580s 3.124ms 20 20 100.00
rom_ctrl_csr_aliasing 12.360s 3.124ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 12.220s 3.124ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 12.370s 3.124ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 13.960s 3.152ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 44.510s 9.416ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 27.090s 6.234ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 12.990s 3.124ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 17.120s 3.124ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 17.120s 3.124ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 16.000s 3.139ms 5 5 100.00
rom_ctrl_csr_rw 12.580s 3.124ms 20 20 100.00
rom_ctrl_csr_aliasing 12.360s 3.124ms 5 5 100.00
rom_ctrl_same_csr_outstanding 14.570s 3.142ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 16.000s 3.139ms 5 5 100.00
rom_ctrl_csr_rw 12.580s 3.124ms 20 20 100.00
rom_ctrl_csr_aliasing 12.360s 3.124ms 5 5 100.00
rom_ctrl_same_csr_outstanding 14.570s 3.142ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 4.915m 65.915ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.972m 3.445ms 5 5 100.00
rom_ctrl_tl_intg_err 1.386m 3.476ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.972m 3.445ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.972m 3.445ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.972m 3.445ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 29.610s 6.265ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 29.610s 6.265ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 29.610s 6.265ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.386m 3.476ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
rom_ctrl_kmac_err_chk 27.090s 6.234ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 5.883m 69.854ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 4.915m 65.915ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.972m 3.445ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 450 500 90.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31

Failure Buckets

Past Results