7147be371
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rom_ctrl_smoke | 30.290s | 6.265ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 15.890s | 3.139ms | 5 | 5 | 100.00 |
V1 | csr_rw | rom_ctrl_csr_rw | 12.690s | 3.124ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 12.830s | 3.124ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rom_ctrl_csr_aliasing | 12.480s | 3.124ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 12.920s | 3.135ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 12.690s | 3.124ms | 20 | 20 | 100.00 |
rom_ctrl_csr_aliasing | 12.480s | 3.124ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | rom_ctrl_mem_walk | 12.290s | 3.124ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | rom_ctrl_mem_partial_access | 12.310s | 3.124ms | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 13.850s | 3.152ms | 50 | 50 | 100.00 |
V2 | stress_all | rom_ctrl_stress_all | 45.200s | 9.416ms | 50 | 50 | 100.00 |
V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 26.790s | 6.234ms | 50 | 50 | 100.00 |
V2 | alert_test | rom_ctrl_alert_test | 13.370s | 3.124ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 16.670s | 3.124ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 16.670s | 3.124ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 15.890s | 3.139ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 12.690s | 3.124ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 12.480s | 3.124ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 14.860s | 3.142ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 15.890s | 3.139ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 12.690s | 3.124ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 12.480s | 3.124ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 14.860s | 3.142ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 240 | 240 | 100.00 | |||
V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 4.800m | 65.915ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | rom_ctrl_sec_cm | 1.989m | 3.445ms | 5 | 5 | 100.00 |
rom_ctrl_tl_intg_err | 1.379m | 3.476ms | 20 | 20 | 100.00 | ||
V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.989m | 3.445ms | 5 | 5 | 100.00 |
V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.989m | 3.445ms | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.989m | 3.445ms | 5 | 5 | 100.00 |
V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 30.290s | 6.265ms | 50 | 50 | 100.00 |
V2S | sec_cm_mem_digest | rom_ctrl_smoke | 30.290s | 6.265ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 30.290s | 6.265ms | 50 | 50 | 100.00 |
V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.379m | 3.476ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
rom_ctrl_kmac_err_chk | 26.790s | 6.234ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 5.800m | 69.854ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 4.800m | 65.915ms | 20 | 20 | 100.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.989m | 3.445ms | 5 | 5 | 100.00 |
V2S | TOTAL | 95 | 95 | 100.00 | |||
V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 450 | 500 | 90.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 6 | 6 | 6 | 100.00 |
V2S | 4 | 4 | 4 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
93.27 | 96.89 | 84.90 | 97.17 | 93.33 | 96.41 | 97.89 | 86.31 |
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 50 failures:
0.rom_ctrl_stress_all_with_rand_reset.61041729135342098705095486912572629103811951463678269402381370304232656399256
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:6e8b0822-061e-4f34-9a76-597b2516a2af
1.rom_ctrl_stress_all_with_rand_reset.4890785106410780214898383345506789477908782667247768787761200417024023333864
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:81fde5f7-7c82-48c8-8ca5-ef2b39c6608b
... and 48 more failures.