ROM_CTRL Simulation Results

Sunday October 15 2023 19:02:25 UTC

GitHub Revision: `b2a255f8a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1600673825

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.680s	13.966ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.940s	2.174ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.090s	4.135ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.120s	1.725ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.760s	2.069ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.300s	2.853ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.090s	4.135ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.760s	2.069ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.790s	4.166ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.480s	2.214ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.840s	2.289ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.601m	16.249ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.200s	4.179ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.020s	4.250ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.350s	1.903ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.350s	1.903ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.940s	2.174ms	5	5	100.00
		rom_ctrl_csr_rw	16.090s	4.135ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.760s	2.069ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.010s	1.923ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.940s	2.174ms	5	5	100.00
		rom_ctrl_csr_rw	16.090s	4.135ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.760s	2.069ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.010s	1.923ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.301m	169.130ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.009m	9.275ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.377m	1.847ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.009m	9.275ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.009m	9.275ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.009m	9.275ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.680s	13.966ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.680s	13.966ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.680s	13.966ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.377m	1.847ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.200s	4.179ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.971m	73.604ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.301m	169.130ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.009m	9.275ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.649h	91.177ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			483	500	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	97.11	93.27	97.88	100.00	99.02	97.89	98.14

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.1350484252
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b8e4d3d2-00f9-404f-99c4-8d7096617f3e
```
  - 5.rom_ctrl_stress_all_with_rand_reset.416842653
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4fe42c62-3486-4077-bec0-5ecf967fa3b0
```
  - ... and 12 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

1.rom_ctrl_stress_all_with_rand_reset.4269942153
Line 209, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10010605762 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb566236d
  UVM_INFO @ 10010605762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.rom_ctrl_stress_all_with_rand_reset.2587064362
Line 209, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10009491320 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3c5adfbc
  UVM_INFO @ 10009491320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.