ROM_CTRL Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: `9601d3bbdd`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.160s	4.106ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.860s	1.486ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.700s	20.398ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.630s	14.476ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.290s	9.006ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.460s	7.042ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.700s	20.398ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.290s	9.006ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.870s	15.639ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.910s	8.697ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.100s	2.042ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.431m	27.146ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.130s	8.343ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.270s	9.915ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.980s	2.891ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.980s	2.891ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.860s	1.486ms	5	5	100.00
		rom_ctrl_csr_rw	16.700s	20.398ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.290s	9.006ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.390s	1.987ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.860s	1.486ms	5	5	100.00
		rom_ctrl_csr_rw	16.700s	20.398ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.290s	9.006ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.390s	1.987ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.527m	42.293ms	18	20	90.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.815m	256.060us	5	5	100.00
		rom_ctrl_tl_intg_err	1.427m	2.310ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.815m	256.060us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.815m	256.060us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.815m	256.060us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.160s	4.106ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.160s	4.106ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.160s	4.106ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.427m	2.310ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
		rom_ctrl_kmac_err_chk	33.130s	8.343ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.367m	67.690ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.527m	42.293ms	18	20	90.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.815m	256.060us	5	5	100.00
V2S		TOTAL			92	95	96.84
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.945h	46.419ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			483	500	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	97.11	93.27	97.88	100.00	99.02	97.89	99.07

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.51223549883225643679273269609903506279333965703069229942567941746368754107958
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:803f15c3-87a5-4861-a6f3-dfb492f3a606
```
  - 9.rom_ctrl_stress_all_with_rand_reset.51164409023791365881867379849134808725163890404697844476912524645458690792061
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:545754f0-c64e-49a5-b2cb-cb0adff70b9c
```
  - ... and 11 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.
  - 2.rom_ctrl_passthru_mem_tl_intg_err.9906006202061612790900004365445581635877569268382976794187211353851331281614
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10009539786 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe6670008
  UVM_INFO @ 10009539786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.rom_ctrl_passthru_mem_tl_intg_err.73366770923100239273228330377807299591168637612799902454683802371581901684965
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10007072493 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x192b8008
  UVM_INFO @ 10007072493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.rom_ctrl_stress_all_with_rand_reset.10571123444854490255643019616063872121469589367179986377592119460232856786283
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10021146873 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xdc8f58ca
  UVM_INFO @ 10021146873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 4.rom_ctrl_corrupt_sig_fatal_chk.17558978647114760757917790317386220765888576211864439805036686685786693981047
    Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 429509862 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 429509862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9601d3bbdd`