ROM_CTRL Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 42.640s 8.621ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 15.810s 1.745ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 16.160s 6.785ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 12.090s 1.314ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 16.040s 2.148ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 17.850s 8.412ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 16.160s 6.785ms 20 20 100.00
rom_ctrl_csr_aliasing 16.040s 2.148ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 12.870s 3.118ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 12.980s 1.550ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 17.660s 14.286ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 1.432m 70.185ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 35.710s 36.429ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 17.260s 4.327ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 19.220s 2.023ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 19.220s 2.023ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 15.810s 1.745ms 5 5 100.00
rom_ctrl_csr_rw 16.160s 6.785ms 20 20 100.00
rom_ctrl_csr_aliasing 16.040s 2.148ms 5 5 100.00
rom_ctrl_same_csr_outstanding 17.000s 2.362ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 15.810s 1.745ms 5 5 100.00
rom_ctrl_csr_rw 16.160s 6.785ms 20 20 100.00
rom_ctrl_csr_aliasing 16.040s 2.148ms 5 5 100.00
rom_ctrl_same_csr_outstanding 17.000s 2.362ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 5.631m 35.397ms 19 20 95.00
V2S tl_intg_err rom_ctrl_sec_cm 1.986m 7.011ms 5 5 100.00
rom_ctrl_tl_intg_err 1.431m 4.202ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.986m 7.011ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.986m 7.011ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.986m 7.011ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 42.640s 8.621ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 42.640s 8.621ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 42.640s 8.621ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.431m 4.202ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
rom_ctrl_kmac_err_chk 35.710s 36.429ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 8.889m 217.322ms 49 50 98.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 5.631m 35.397ms 19 20 95.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.986m 7.011ms 5 5 100.00
V2S TOTAL 93 95 97.89
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.446h 18.960ms 37 50 74.00
V3 TOTAL 37 50 74.00
TOTAL 485 500 97.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 2 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.58 97.11 92.53 97.88 100.00 98.37 97.89 99.30

Failure Buckets

Past Results