Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
57.99 39.18 35.44 91.88 0.00 44.08 98.63 96.74


Total tests in report: 144
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
43.88 43.88 38.95 38.95 33.86 33.86 39.96 39.96 0.00 0.00 42.76 42.76 95.90 95.90 55.71 55.71 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.426615783
51.77 7.90 38.95 0.00 34.72 0.86 90.29 50.33 0.00 0.00 43.09 0.33 97.09 1.20 58.28 2.56 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3684055925
54.12 2.34 38.95 0.00 34.72 0.00 90.37 0.08 0.00 0.00 43.09 0.00 97.09 0.00 74.59 16.32 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3096310360
55.88 1.76 39.18 0.23 35.44 0.72 92.38 2.01 0.00 0.00 44.08 0.99 97.09 0.00 82.98 8.39 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.384508263
56.83 0.95 39.18 0.00 35.44 0.00 96.99 4.61 0.00 0.00 44.08 0.00 97.95 0.85 84.15 1.17 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3285652874
57.66 0.83 39.18 0.00 35.44 0.00 96.99 0.00 0.00 0.00 44.08 0.00 97.95 0.00 89.98 5.83 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2933492711
58.06 0.40 39.18 0.00 35.44 0.00 96.99 0.00 0.00 0.00 44.08 0.00 97.95 0.00 92.77 2.80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2594330329
58.32 0.27 39.18 0.00 35.44 0.00 96.99 0.00 0.00 0.00 44.08 0.00 97.95 0.00 94.64 1.86 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.421975538
58.46 0.13 39.18 0.00 35.44 0.00 96.99 0.00 0.00 0.00 44.08 0.00 97.95 0.00 95.57 0.93 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2856769181
58.57 0.11 39.18 0.00 35.44 0.00 97.26 0.27 0.00 0.00 44.08 0.00 98.46 0.51 95.57 0.00 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1162755677
58.62 0.05 39.18 0.00 35.44 0.00 97.37 0.11 0.00 0.00 44.08 0.00 98.46 0.00 95.80 0.23 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.507119563
58.67 0.05 39.18 0.00 35.44 0.00 97.48 0.11 0.00 0.00 44.08 0.00 98.46 0.00 96.04 0.23 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2273098761
58.71 0.04 39.18 0.00 35.44 0.00 97.53 0.05 0.00 0.00 44.08 0.00 98.46 0.00 96.27 0.23 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3189227
58.75 0.04 39.18 0.00 35.44 0.00 97.59 0.05 0.00 0.00 44.08 0.00 98.46 0.00 96.50 0.23 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2109062010
58.79 0.04 39.18 0.00 35.44 0.00 97.64 0.05 0.00 0.00 44.08 0.00 98.46 0.00 96.74 0.23 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1177885159
58.82 0.03 39.18 0.00 35.44 0.00 97.67 0.03 0.00 0.00 44.08 0.00 98.63 0.17 96.74 0.00 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2976992534

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.937857293
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3245525004
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.299903478
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.115772646
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.544202728
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3482109956
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2109888349
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1002241104
/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3161096050
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2354454887
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3278885885
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2271824899
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3757236981
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.518753515
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1690272472
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4260975435
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1676770588
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2739244721
/workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2088761154
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.150288433
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3382152546
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3434914633
/workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.946005755
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.418146331
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3633155496
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2696387519
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2926706009
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.794826350
/workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3977297886
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3802314911
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2368416473
/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3050687235
/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2013600308
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3857648566
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.94640272
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.12419821
/workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3171055134
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.275292827
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.441843417
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2663103939
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1996030866
/workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1865693461
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.260729888
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1482150395
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2292863705
/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1883913187
/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2347426612
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.329459393
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3017996879
/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3957663821
/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2223363052
/workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.535682021
/workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.630260900
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1841546983
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2972583257
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3236917949
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.902263959
/workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4017246449
/workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2571017293
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3148877234
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3650974170
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3071352874
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2334101887
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.837337062
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1938449499
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.230599641
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2869273023
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3357730267
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2867088106
/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1418235806
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2725926824
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1638975798
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.32943287
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1902639113
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3799836567
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3735998658
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1532756698
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3670892387
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1816745011
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.720381675
/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3034178551
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1667816895
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3106398684
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2438869826
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2927104684
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2553551973
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3813403112
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1179922750
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.168780480
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3051060160
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2992018396
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1803009713
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.74438815
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2440681972
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1417856741
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1549644928
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.900659533
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.660556117
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4238572408
/workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1683405689
/workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2601401981
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.398767668
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2648425846
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.699390515
/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.804838415
/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2727523162
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.646117440
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1427288072
/workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3020579444
/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.558422504
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1221659762
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3385816522
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.342980938
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1624952773
/workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.238635998
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2060737131
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4022209937
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3870559790
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1191614996
/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3866488665
/workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.877422616
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3746780936
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.104169461
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.141180465
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3082599916
/workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.377255289
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4242386315
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1489167118



Total test records in report: 144
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1532756698 Apr 04 12:28:52 PM PDT 24 Apr 04 12:29:07 PM PDT 24 7412784863 ps
T2 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.426615783 Apr 04 12:29:36 PM PDT 24 Apr 04 12:29:47 PM PDT 24 561757757 ps
T3 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2976992534 Apr 04 12:29:08 PM PDT 24 Apr 04 12:29:20 PM PDT 24 5850937527 ps
T14 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2926706009 Apr 04 12:28:55 PM PDT 24 Apr 04 12:28:59 PM PDT 24 830134781 ps
T7 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1676770588 Apr 04 12:29:38 PM PDT 24 Apr 04 12:29:55 PM PDT 24 2052048163 ps
T4 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2869273023 Apr 04 12:30:56 PM PDT 24 Apr 04 12:31:38 PM PDT 24 4322414426 ps
T5 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3633155496 Apr 04 12:28:57 PM PDT 24 Apr 04 12:29:44 PM PDT 24 8819807930 ps
T11 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2060737131 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:54 PM PDT 24 293408243 ps
T17 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4242386315 Apr 04 12:28:53 PM PDT 24 Apr 04 12:29:02 PM PDT 24 5443471209 ps
T21 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4238572408 Apr 04 12:28:15 PM PDT 24 Apr 04 12:28:28 PM PDT 24 1382373635 ps
T6 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.299903478 Apr 04 12:27:26 PM PDT 24 Apr 04 12:27:39 PM PDT 24 4147013182 ps
T12 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3096310360 Apr 04 12:29:56 PM PDT 24 Apr 04 12:30:10 PM PDT 24 1963337930 ps
T8 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3684055925 Apr 04 12:30:35 PM PDT 24 Apr 04 12:31:21 PM PDT 24 18814445975 ps
T13 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2972583257 Apr 04 12:30:44 PM PDT 24 Apr 04 12:31:25 PM PDT 24 7568715067 ps
T27 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1417856741 Apr 04 12:28:30 PM PDT 24 Apr 04 12:28:43 PM PDT 24 5579615964 ps
T28 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2347426612 Apr 04 12:30:27 PM PDT 24 Apr 04 12:30:37 PM PDT 24 1047807620 ps
T18 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.104169461 Apr 04 12:27:50 PM PDT 24 Apr 04 12:28:29 PM PDT 24 13477720723 ps
T29 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3434914633 Apr 04 12:29:39 PM PDT 24 Apr 04 12:29:47 PM PDT 24 3060632651 ps
T30 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2334101887 Apr 04 12:31:18 PM PDT 24 Apr 04 12:31:27 PM PDT 24 4378262133 ps
T19 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1177885159 Apr 04 12:29:07 PM PDT 24 Apr 04 12:29:21 PM PDT 24 5278121806 ps
T20 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.398767668 Apr 04 12:28:50 PM PDT 24 Apr 04 12:30:08 PM PDT 24 4884021627 ps
T22 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3735998658 Apr 04 12:29:22 PM PDT 24 Apr 04 12:29:39 PM PDT 24 3144010673 ps
T42 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1179922750 Apr 04 12:29:14 PM PDT 24 Apr 04 12:29:30 PM PDT 24 2062475082 ps
T48 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3482109956 Apr 04 12:27:34 PM PDT 24 Apr 04 12:27:47 PM PDT 24 1450684167 ps
T23 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.384508263 Apr 04 12:30:22 PM PDT 24 Apr 04 12:31:40 PM PDT 24 8730398364 ps
T49 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2553551973 Apr 04 12:29:40 PM PDT 24 Apr 04 12:29:51 PM PDT 24 837502802 ps
T50 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.238635998 Apr 04 12:28:54 PM PDT 24 Apr 04 12:29:05 PM PDT 24 2519614207 ps
T51 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3670892387 Apr 04 12:27:50 PM PDT 24 Apr 04 12:28:05 PM PDT 24 2069379523 ps
T43 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3082599916 Apr 04 12:28:56 PM PDT 24 Apr 04 12:29:12 PM PDT 24 2021222669 ps
T24 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2594330329 Apr 04 12:29:35 PM PDT 24 Apr 04 12:29:51 PM PDT 24 7346422754 ps
T44 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1996030866 Apr 04 12:30:26 PM PDT 24 Apr 04 12:30:37 PM PDT 24 9456280444 ps
T9 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3285652874 Apr 04 12:30:46 PM PDT 24 Apr 04 12:32:11 PM PDT 24 19522154175 ps
T10 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3020579444 Apr 04 12:29:16 PM PDT 24 Apr 04 12:30:21 PM PDT 24 17100421843 ps
T25 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3857648566 Apr 04 12:29:08 PM PDT 24 Apr 04 12:29:28 PM PDT 24 8497503013 ps
T40 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.699390515 Apr 04 12:30:11 PM PDT 24 Apr 04 12:30:18 PM PDT 24 1690885910 ps
T16 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1162755677 Apr 04 12:27:26 PM PDT 24 Apr 04 12:28:07 PM PDT 24 3237336043 ps
T36 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3650974170 Apr 04 12:30:55 PM PDT 24 Apr 04 12:32:11 PM PDT 24 4797350682 ps
T41 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3757236981 Apr 04 12:28:16 PM PDT 24 Apr 04 12:28:33 PM PDT 24 4197020283 ps
T37 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2856769181 Apr 04 12:29:07 PM PDT 24 Apr 04 12:29:43 PM PDT 24 586028155 ps
T26 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3746780936 Apr 04 12:27:48 PM PDT 24 Apr 04 12:28:02 PM PDT 24 1274844888 ps
T38 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3870559790 Apr 04 12:27:48 PM PDT 24 Apr 04 12:27:56 PM PDT 24 498375783 ps
T57 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3171055134 Apr 04 12:30:27 PM PDT 24 Apr 04 12:30:42 PM PDT 24 7750610426 ps
T39 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2933492711 Apr 04 12:29:03 PM PDT 24 Apr 04 12:29:19 PM PDT 24 2077706945 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2109062010 Apr 04 12:28:57 PM PDT 24 Apr 04 12:29:39 PM PDT 24 1168778155 ps
T15 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3050687235 Apr 04 12:29:23 PM PDT 24 Apr 04 12:29:42 PM PDT 24 1494281486 ps
T31 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1683405689 Apr 04 12:29:07 PM PDT 24 Apr 04 12:29:57 PM PDT 24 5735239457 ps
T79 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3382152546 Apr 04 12:28:48 PM PDT 24 Apr 04 12:29:02 PM PDT 24 1520955236 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1638975798 Apr 04 12:30:58 PM PDT 24 Apr 04 12:32:18 PM PDT 24 10584523297 ps
T60 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2927104684 Apr 04 12:28:54 PM PDT 24 Apr 04 12:29:01 PM PDT 24 335355073 ps
T52 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1549644928 Apr 04 12:28:23 PM PDT 24 Apr 04 12:28:40 PM PDT 24 14266576298 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3051060160 Apr 04 12:28:53 PM PDT 24 Apr 04 12:28:57 PM PDT 24 346750041 ps
T74 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2663103939 Apr 04 12:30:29 PM PDT 24 Apr 04 12:30:33 PM PDT 24 551980231 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.342980938 Apr 04 12:27:49 PM PDT 24 Apr 04 12:27:53 PM PDT 24 232156207 ps
T82 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2292863705 Apr 04 12:30:32 PM PDT 24 Apr 04 12:30:36 PM PDT 24 333649177 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.518753515 Apr 04 12:29:45 PM PDT 24 Apr 04 12:30:02 PM PDT 24 5272986071 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3236917949 Apr 04 12:31:08 PM PDT 24 Apr 04 12:31:13 PM PDT 24 395513625 ps
T53 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1427288072 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:50 PM PDT 24 1377745229 ps
T71 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.275292827 Apr 04 12:30:21 PM PDT 24 Apr 04 12:30:34 PM PDT 24 12353782484 ps
T59 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2601401981 Apr 04 12:28:51 PM PDT 24 Apr 04 12:29:05 PM PDT 24 6584208491 ps
T63 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2273098761 Apr 04 12:29:49 PM PDT 24 Apr 04 12:30:34 PM PDT 24 1942758849 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3148877234 Apr 04 12:30:37 PM PDT 24 Apr 04 12:30:50 PM PDT 24 987444147 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2725926824 Apr 04 12:30:24 PM PDT 24 Apr 04 12:30:33 PM PDT 24 933072014 ps
T84 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.877422616 Apr 04 12:27:49 PM PDT 24 Apr 04 12:28:01 PM PDT 24 5735789529 ps
T75 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1482150395 Apr 04 12:30:26 PM PDT 24 Apr 04 12:30:42 PM PDT 24 7432494126 ps
T32 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1624952773 Apr 04 12:29:36 PM PDT 24 Apr 04 12:30:11 PM PDT 24 12773182842 ps
T33 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.946005755 Apr 04 12:28:53 PM PDT 24 Apr 04 12:30:16 PM PDT 24 20111710569 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2696387519 Apr 04 12:28:54 PM PDT 24 Apr 04 12:29:09 PM PDT 24 6954985432 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.507119563 Apr 04 12:30:26 PM PDT 24 Apr 04 12:31:34 PM PDT 24 1726430039 ps
T86 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2727523162 Apr 04 12:30:12 PM PDT 24 Apr 04 12:30:17 PM PDT 24 174950639 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2867088106 Apr 04 12:31:19 PM PDT 24 Apr 04 12:31:24 PM PDT 24 93852780 ps
T78 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.260729888 Apr 04 12:30:22 PM PDT 24 Apr 04 12:30:32 PM PDT 24 1210416089 ps
T76 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.421975538 Apr 04 12:29:47 PM PDT 24 Apr 04 12:29:55 PM PDT 24 419785522 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2223363052 Apr 04 12:30:56 PM PDT 24 Apr 04 12:31:10 PM PDT 24 1686093768 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2739244721 Apr 04 12:28:16 PM PDT 24 Apr 04 12:28:24 PM PDT 24 2610892220 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.12419821 Apr 04 12:30:37 PM PDT 24 Apr 04 12:30:52 PM PDT 24 1832133710 ps
T91 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3957663821 Apr 04 12:30:30 PM PDT 24 Apr 04 12:30:49 PM PDT 24 1623995232 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.544202728 Apr 04 12:27:34 PM PDT 24 Apr 04 12:27:38 PM PDT 24 333434369 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.646117440 Apr 04 12:28:15 PM PDT 24 Apr 04 12:28:26 PM PDT 24 1028381044 ps
T67 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.150288433 Apr 04 12:27:35 PM PDT 24 Apr 04 12:28:53 PM PDT 24 13086919421 ps
T94 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3071352874 Apr 04 12:30:33 PM PDT 24 Apr 04 12:30:38 PM PDT 24 450815958 ps
T95 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.230599641 Apr 04 12:30:50 PM PDT 24 Apr 04 12:31:10 PM PDT 24 2111326379 ps
T70 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3017996879 Apr 04 12:30:28 PM PDT 24 Apr 04 12:31:06 PM PDT 24 345731459 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2368416473 Apr 04 12:30:19 PM PDT 24 Apr 04 12:30:30 PM PDT 24 5058399269 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1803009713 Apr 04 12:29:22 PM PDT 24 Apr 04 12:29:32 PM PDT 24 1831596078 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3278885885 Apr 04 12:27:29 PM PDT 24 Apr 04 12:28:06 PM PDT 24 319090434 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.660556117 Apr 04 12:28:17 PM PDT 24 Apr 04 12:28:31 PM PDT 24 5995081798 ps
T77 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1841546983 Apr 04 12:30:46 PM PDT 24 Apr 04 12:30:58 PM PDT 24 2065519109 ps
T99 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1221659762 Apr 04 12:29:54 PM PDT 24 Apr 04 12:31:12 PM PDT 24 1812459562 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2571017293 Apr 04 12:30:33 PM PDT 24 Apr 04 12:30:37 PM PDT 24 91159251 ps
T101 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3977297886 Apr 04 12:28:54 PM PDT 24 Apr 04 12:29:10 PM PDT 24 3315959692 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.937857293 Apr 04 12:27:37 PM PDT 24 Apr 04 12:27:52 PM PDT 24 3787217597 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.441843417 Apr 04 12:30:16 PM PDT 24 Apr 04 12:31:27 PM PDT 24 1262037902 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1667816895 Apr 04 12:28:45 PM PDT 24 Apr 04 12:29:04 PM PDT 24 1763607491 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1690272472 Apr 04 12:28:51 PM PDT 24 Apr 04 12:29:01 PM PDT 24 910682263 ps
T34 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.804838415 Apr 04 12:28:19 PM PDT 24 Apr 04 12:28:48 PM PDT 24 3154803261 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3357730267 Apr 04 12:30:27 PM PDT 24 Apr 04 12:30:39 PM PDT 24 9290965244 ps
T107 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1191614996 Apr 04 12:29:05 PM PDT 24 Apr 04 12:29:16 PM PDT 24 4244383739 ps
T35 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3189227 Apr 04 12:30:25 PM PDT 24 Apr 04 12:31:21 PM PDT 24 13026213008 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.74438815 Apr 04 12:28:53 PM PDT 24 Apr 04 12:29:02 PM PDT 24 532005569 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3034178551 Apr 04 12:28:57 PM PDT 24 Apr 04 12:29:11 PM PDT 24 1713769764 ps
T110 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4022209937 Apr 04 12:28:50 PM PDT 24 Apr 04 12:29:35 PM PDT 24 1626524111 ps
T111 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2013600308 Apr 04 12:30:10 PM PDT 24 Apr 04 12:30:19 PM PDT 24 3081807855 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3799836567 Apr 04 12:29:40 PM PDT 24 Apr 04 12:29:55 PM PDT 24 1586704133 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.141180465 Apr 04 12:28:55 PM PDT 24 Apr 04 12:29:03 PM PDT 24 499597651 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3802314911 Apr 04 12:29:05 PM PDT 24 Apr 04 12:30:19 PM PDT 24 8776118125 ps
T54 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2438869826 Apr 04 12:29:08 PM PDT 24 Apr 04 12:29:22 PM PDT 24 1927298560 ps
T114 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1816745011 Apr 04 12:29:04 PM PDT 24 Apr 04 12:29:21 PM PDT 24 8834601078 ps
T115 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2648425846 Apr 04 12:28:44 PM PDT 24 Apr 04 12:28:55 PM PDT 24 3742534434 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2354454887 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:54 PM PDT 24 8932623796 ps
T61 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1883913187 Apr 04 12:30:22 PM PDT 24 Apr 04 12:32:04 PM PDT 24 102330709745 ps
T117 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.900659533 Apr 04 12:28:32 PM PDT 24 Apr 04 12:28:47 PM PDT 24 7251392876 ps
T45 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.377255289 Apr 04 12:29:07 PM PDT 24 Apr 04 12:30:30 PM PDT 24 10574380685 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2088761154 Apr 04 12:27:50 PM PDT 24 Apr 04 12:28:00 PM PDT 24 1104266246 ps
T119 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1489167118 Apr 04 12:28:56 PM PDT 24 Apr 04 12:29:15 PM PDT 24 3434637034 ps
T55 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4017246449 Apr 04 12:31:13 PM PDT 24 Apr 04 12:31:40 PM PDT 24 1098886688 ps
T120 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3385816522 Apr 04 12:27:49 PM PDT 24 Apr 04 12:28:00 PM PDT 24 9821076607 ps
T121 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1938449499 Apr 04 12:30:30 PM PDT 24 Apr 04 12:30:35 PM PDT 24 178945363 ps
T122 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.418146331 Apr 04 12:28:52 PM PDT 24 Apr 04 12:29:05 PM PDT 24 982097566 ps
T123 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1418235806 Apr 04 12:30:46 PM PDT 24 Apr 04 12:30:55 PM PDT 24 4545849785 ps
T124 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.794826350 Apr 04 12:28:52 PM PDT 24 Apr 04 12:29:58 PM PDT 24 16808149599 ps
T125 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.32943287 Apr 04 12:29:06 PM PDT 24 Apr 04 12:29:10 PM PDT 24 90131584 ps
T126 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2109888349 Apr 04 12:29:23 PM PDT 24 Apr 04 12:29:32 PM PDT 24 900458448 ps
T127 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.558422504 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:58 PM PDT 24 5624536434 ps
T46 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3866488665 Apr 04 12:28:51 PM PDT 24 Apr 04 12:29:18 PM PDT 24 2473740430 ps
T128 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4260975435 Apr 04 12:28:15 PM PDT 24 Apr 04 12:28:23 PM PDT 24 2378811622 ps
T129 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1902639113 Apr 04 12:27:49 PM PDT 24 Apr 04 12:28:06 PM PDT 24 41716485942 ps
T130 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2992018396 Apr 04 12:28:53 PM PDT 24 Apr 04 12:29:21 PM PDT 24 3414105345 ps
T131 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.902263959 Apr 04 12:30:34 PM PDT 24 Apr 04 12:30:47 PM PDT 24 5712050601 ps
T132 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.115772646 Apr 04 12:27:36 PM PDT 24 Apr 04 12:27:49 PM PDT 24 1520513215 ps
T133 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.168780480 Apr 04 12:28:57 PM PDT 24 Apr 04 12:29:01 PM PDT 24 93930656 ps
T134 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3161096050 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:50 PM PDT 24 2014335490 ps
T47 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.535682021 Apr 04 12:30:32 PM PDT 24 Apr 04 12:31:38 PM PDT 24 12199718430 ps
T135 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3245525004 Apr 04 12:27:34 PM PDT 24 Apr 04 12:27:39 PM PDT 24 321759691 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3106398684 Apr 04 12:27:50 PM PDT 24 Apr 04 12:28:30 PM PDT 24 1084659103 ps
T136 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1002241104 Apr 04 12:27:34 PM PDT 24 Apr 04 12:28:40 PM PDT 24 25731822471 ps
T137 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1865693461 Apr 04 12:30:29 PM PDT 24 Apr 04 12:30:40 PM PDT 24 4427448566 ps
T138 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.94640272 Apr 04 12:30:26 PM PDT 24 Apr 04 12:30:41 PM PDT 24 7948873933 ps
T56 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2271824899 Apr 04 12:27:50 PM PDT 24 Apr 04 12:27:58 PM PDT 24 654009033 ps
T139 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3813403112 Apr 04 12:29:03 PM PDT 24 Apr 04 12:29:08 PM PDT 24 187517356 ps
T140 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.720381675 Apr 04 12:27:50 PM PDT 24 Apr 04 12:28:16 PM PDT 24 4917856949 ps
T141 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.837337062 Apr 04 12:30:26 PM PDT 24 Apr 04 12:31:29 PM PDT 24 8233989444 ps
T142 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.329459393 Apr 04 12:30:26 PM PDT 24 Apr 04 12:30:40 PM PDT 24 936543955 ps
T143 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2440681972 Apr 04 12:28:34 PM PDT 24 Apr 04 12:28:40 PM PDT 24 345191204 ps
T144 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.630260900 Apr 04 12:31:40 PM PDT 24 Apr 04 12:31:48 PM PDT 24 699946475 ps

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.426615783
Short name T2
Test name
Test status
Simulation time 561757757 ps
CPU time 10.48 seconds
Started Apr 04 12:29:36 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 218676 kb
Host smart-6d14ee51-698a-4ead-a488-0ff28f0a1ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426615783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.426615783
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3684055925
Short name T8
Test name
Test status
Simulation time 18814445975 ps
CPU time 46.48 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:31:21 PM PDT 24
Peak memory 210440 kb
Host smart-c7695ba6-4f64-450d-aefe-ec2f19a097fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684055925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3684055925
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3096310360
Short name T12
Test name
Test status
Simulation time 1963337930 ps
CPU time 13 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:30:10 PM PDT 24
Peak memory 218644 kb
Host smart-8313d803-d132-445d-ba15-bf81c78a7090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096310360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3096310360
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.384508263
Short name T23
Test name
Test status
Simulation time 8730398364 ps
CPU time 77.56 seconds
Started Apr 04 12:30:22 PM PDT 24
Finished Apr 04 12:31:40 PM PDT 24
Peak memory 211564 kb
Host smart-9ac41477-83aa-4f8e-914e-824abfcd0d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384508263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.384508263
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3285652874
Short name T9
Test name
Test status
Simulation time 19522154175 ps
CPU time 84.73 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 210592 kb
Host smart-d6f2da06-fb7a-4080-9349-bbbce39724b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285652874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3285652874
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2933492711
Short name T39
Test name
Test status
Simulation time 2077706945 ps
CPU time 15.09 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:19 PM PDT 24
Peak memory 217576 kb
Host smart-ba36efbe-fc31-45ba-9a53-9a95d4c7e7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933492711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2933492711
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2594330329
Short name T24
Test name
Test status
Simulation time 7346422754 ps
CPU time 15.68 seconds
Started Apr 04 12:29:35 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 218740 kb
Host smart-4b0eb898-1652-4b97-980c-2bb52a2dd6b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594330329 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2594330329
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.421975538
Short name T76
Test name
Test status
Simulation time 419785522 ps
CPU time 7.94 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 218624 kb
Host smart-97ffc37a-8e9d-41d6-8662-6af85eac5ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421975538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.421975538
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2856769181
Short name T37
Test name
Test status
Simulation time 586028155 ps
CPU time 35.63 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 211484 kb
Host smart-407c84be-6d09-4b46-bd26-746740a45154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856769181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2856769181
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1162755677
Short name T16
Test name
Test status
Simulation time 3237336043 ps
CPU time 40.21 seconds
Started Apr 04 12:27:26 PM PDT 24
Finished Apr 04 12:28:07 PM PDT 24
Peak memory 210368 kb
Host smart-6f0a9115-4d87-4ea4-acc6-1954ac30b9b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162755677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1162755677
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.507119563
Short name T64
Test name
Test status
Simulation time 1726430039 ps
CPU time 68.41 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:31:34 PM PDT 24
Peak memory 218668 kb
Host smart-0553d468-0327-421b-91be-dc4577ad4d91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507119563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.507119563
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2273098761
Short name T63
Test name
Test status
Simulation time 1942758849 ps
CPU time 44.48 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:30:34 PM PDT 24
Peak memory 212268 kb
Host smart-1b8e0abe-f5ba-4e92-aa68-ef297bba7f24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273098761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2273098761
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3189227
Short name T35
Test name
Test status
Simulation time 13026213008 ps
CPU time 54.97 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:31:21 PM PDT 24
Peak memory 210540 kb
Host smart-dbd7233c-e5f3-428a-b18f-897f3e4e3e02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pass
thru_mem_tl_intg_err.3189227
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2109062010
Short name T62
Test name
Test status
Simulation time 1168778155 ps
CPU time 42.05 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:39 PM PDT 24
Peak memory 210908 kb
Host smart-54eaac4f-9e80-4d5c-a00c-719baf3208fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109062010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2109062010
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1177885159
Short name T19
Test name
Test status
Simulation time 5278121806 ps
CPU time 13.95 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:29:21 PM PDT 24
Peak memory 218688 kb
Host smart-f4deea9a-ce17-42bc-b97d-f692e27d5139
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177885159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1177885159
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2976992534
Short name T3
Test name
Test status
Simulation time 5850937527 ps
CPU time 12.41 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:20 PM PDT 24
Peak memory 210380 kb
Host smart-835aef6b-24d7-44a2-87dd-341bc697a8b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976992534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2976992534
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.937857293
Short name T102
Test name
Test status
Simulation time 3787217597 ps
CPU time 14.93 seconds
Started Apr 04 12:27:37 PM PDT 24
Finished Apr 04 12:27:52 PM PDT 24
Peak memory 210448 kb
Host smart-b5e493ae-b7a6-4a9f-a746-a142d4041046
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937857293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.937857293
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3245525004
Short name T135
Test name
Test status
Simulation time 321759691 ps
CPU time 4.38 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:27:39 PM PDT 24
Peak memory 210340 kb
Host smart-887372a5-d325-4150-96f1-fb6819c158ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245525004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3245525004
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.299903478
Short name T6
Test name
Test status
Simulation time 4147013182 ps
CPU time 13.3 seconds
Started Apr 04 12:27:26 PM PDT 24
Finished Apr 04 12:27:39 PM PDT 24
Peak memory 210820 kb
Host smart-8b7c9bb3-0141-45d9-b746-07cecc8793a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299903478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.299903478
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.115772646
Short name T132
Test name
Test status
Simulation time 1520513215 ps
CPU time 13.36 seconds
Started Apr 04 12:27:36 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 218416 kb
Host smart-6b2351b1-bc1c-490d-a056-0b48c682fbc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115772646 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.115772646
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.544202728
Short name T92
Test name
Test status
Simulation time 333434369 ps
CPU time 4.13 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:27:38 PM PDT 24
Peak memory 210304 kb
Host smart-4cb978c0-c216-46f1-8d7b-603c64ce31cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544202728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.544202728
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3482109956
Short name T48
Test name
Test status
Simulation time 1450684167 ps
CPU time 12.11 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:27:47 PM PDT 24
Peak memory 210208 kb
Host smart-6aef5cab-f441-4e8e-81f5-954a06936e52
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482109956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3482109956
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2109888349
Short name T126
Test name
Test status
Simulation time 900458448 ps
CPU time 9.48 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:32 PM PDT 24
Peak memory 210440 kb
Host smart-13a0c9e7-e236-4181-9468-bf3c62eb1b7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109888349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2109888349
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1002241104
Short name T136
Test name
Test status
Simulation time 25731822471 ps
CPU time 65.24 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:28:40 PM PDT 24
Peak memory 210876 kb
Host smart-fcd48496-4429-477d-bce9-51f96e39e78e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002241104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1002241104
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3161096050
Short name T134
Test name
Test status
Simulation time 2014335490 ps
CPU time 15.04 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:50 PM PDT 24
Peak memory 210356 kb
Host smart-243d3c49-5225-470a-95d2-9718f96cbb95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161096050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3161096050
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2354454887
Short name T116
Test name
Test status
Simulation time 8932623796 ps
CPU time 19.81 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:54 PM PDT 24
Peak memory 218648 kb
Host smart-cdae5c89-52d1-4829-a5d8-2c47b3e436fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354454887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2354454887
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3278885885
Short name T69
Test name
Test status
Simulation time 319090434 ps
CPU time 36.77 seconds
Started Apr 04 12:27:29 PM PDT 24
Finished Apr 04 12:28:06 PM PDT 24
Peak memory 212368 kb
Host smart-e6e74453-0789-45a5-b748-1b8e800f233d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278885885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3278885885
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2271824899
Short name T56
Test name
Test status
Simulation time 654009033 ps
CPU time 8.11 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:27:58 PM PDT 24
Peak memory 210208 kb
Host smart-f4788e0a-85d9-41e8-887b-4dbe5da430ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271824899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2271824899
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3757236981
Short name T41
Test name
Test status
Simulation time 4197020283 ps
CPU time 17.26 seconds
Started Apr 04 12:28:16 PM PDT 24
Finished Apr 04 12:28:33 PM PDT 24
Peak memory 210544 kb
Host smart-78db8c71-e5e3-45c6-ba8d-3af66a65036b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757236981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3757236981
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.518753515
Short name T83
Test name
Test status
Simulation time 5272986071 ps
CPU time 16.33 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:30:02 PM PDT 24
Peak memory 210444 kb
Host smart-4616a120-ef5e-478a-8a56-94e7865fbfc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518753515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.518753515
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1690272472
Short name T105
Test name
Test status
Simulation time 910682263 ps
CPU time 9.67 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:29:01 PM PDT 24
Peak memory 212876 kb
Host smart-2e4c9a09-11f2-4df7-8433-96b6474dff9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690272472 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1690272472
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4260975435
Short name T128
Test name
Test status
Simulation time 2378811622 ps
CPU time 7.85 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:23 PM PDT 24
Peak memory 210548 kb
Host smart-34957ff8-339e-4b9c-b09d-3d452ed29a4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260975435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4260975435
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1676770588
Short name T7
Test name
Test status
Simulation time 2052048163 ps
CPU time 15.98 seconds
Started Apr 04 12:29:38 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 210264 kb
Host smart-5e663fd6-d58c-4383-bfd4-180a446ab575
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676770588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1676770588
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2739244721
Short name T89
Test name
Test status
Simulation time 2610892220 ps
CPU time 8.48 seconds
Started Apr 04 12:28:16 PM PDT 24
Finished Apr 04 12:28:24 PM PDT 24
Peak memory 210480 kb
Host smart-a0fcea08-a0c4-4f03-9d0d-e003fe29e9b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739244721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2739244721
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2088761154
Short name T118
Test name
Test status
Simulation time 1104266246 ps
CPU time 10.42 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:28:00 PM PDT 24
Peak memory 210204 kb
Host smart-c0ac2bdf-80d3-4094-beb6-513da081235e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088761154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2088761154
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.150288433
Short name T67
Test name
Test status
Simulation time 13086919421 ps
CPU time 77.58 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 211724 kb
Host smart-8b2f376a-9d4c-468e-a888-455ca4b94bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150288433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.150288433
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3382152546
Short name T79
Test name
Test status
Simulation time 1520955236 ps
CPU time 13.01 seconds
Started Apr 04 12:28:48 PM PDT 24
Finished Apr 04 12:29:02 PM PDT 24
Peak memory 209876 kb
Host smart-632b5ae0-3555-4701-9a69-afa9adfe66bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382152546 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3382152546
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3434914633
Short name T29
Test name
Test status
Simulation time 3060632651 ps
CPU time 7.36 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 210440 kb
Host smart-68995ee9-ea53-47f8-9544-d0183342795c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434914633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3434914633
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.946005755
Short name T33
Test name
Test status
Simulation time 20111710569 ps
CPU time 83 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:30:16 PM PDT 24
Peak memory 217260 kb
Host smart-cc9227fe-0a56-4e3d-853a-2d6d2fa9f4d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946005755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.946005755
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.418146331
Short name T122
Test name
Test status
Simulation time 982097566 ps
CPU time 12.4 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 217576 kb
Host smart-06f7aca9-4337-4ad9-b8f4-103b1b6044b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418146331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.418146331
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3633155496
Short name T5
Test name
Test status
Simulation time 8819807930 ps
CPU time 47.43 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 217360 kb
Host smart-6613fedb-fd53-47d7-bb02-3290ea59deb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633155496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3633155496
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2696387519
Short name T85
Test name
Test status
Simulation time 6954985432 ps
CPU time 14.39 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 217256 kb
Host smart-98b8c5d9-93a9-4553-b5d4-9242675d1171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696387519 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2696387519
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2926706009
Short name T14
Test name
Test status
Simulation time 830134781 ps
CPU time 4.05 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:28:59 PM PDT 24
Peak memory 210092 kb
Host smart-64797df9-57b6-4865-ab9f-a718de128ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926706009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2926706009
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.794826350
Short name T124
Test name
Test status
Simulation time 16808149599 ps
CPU time 65.98 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 209508 kb
Host smart-de8584b7-5ca0-4fe9-9561-0b6044bbc552
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794826350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.794826350
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3977297886
Short name T101
Test name
Test status
Simulation time 3315959692 ps
CPU time 15.49 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:10 PM PDT 24
Peak memory 209036 kb
Host smart-875a592e-739c-426c-9caf-bf1ce04551df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977297886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3977297886
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3802314911
Short name T68
Test name
Test status
Simulation time 8776118125 ps
CPU time 74.06 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:30:19 PM PDT 24
Peak memory 211236 kb
Host smart-823c696e-4c69-4502-8a9a-95087d7b4162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802314911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3802314911
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2368416473
Short name T96
Test name
Test status
Simulation time 5058399269 ps
CPU time 11.56 seconds
Started Apr 04 12:30:19 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 210544 kb
Host smart-2d4dd939-49aa-4e8c-9d21-3fa5d7ad0134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368416473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2368416473
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3050687235
Short name T15
Test name
Test status
Simulation time 1494281486 ps
CPU time 19.04 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:42 PM PDT 24
Peak memory 209260 kb
Host smart-e5928a02-da95-453c-9f78-7c79f8756ba0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050687235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3050687235
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2013600308
Short name T111
Test name
Test status
Simulation time 3081807855 ps
CPU time 8.86 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:19 PM PDT 24
Peak memory 210572 kb
Host smart-bf92ce43-ab88-4b22-a9a5-d680f4f59cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013600308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2013600308
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3857648566
Short name T25
Test name
Test status
Simulation time 8497503013 ps
CPU time 19.94 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:28 PM PDT 24
Peak memory 218684 kb
Host smart-40de5512-8dd6-4f71-a320-f1b8c018e5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857648566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3857648566
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.94640272
Short name T138
Test name
Test status
Simulation time 7948873933 ps
CPU time 15.11 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:41 PM PDT 24
Peak memory 212680 kb
Host smart-e3e70a8d-edda-45c7-bc3e-8a3f8d7bc119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94640272 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.94640272
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.12419821
Short name T90
Test name
Test status
Simulation time 1832133710 ps
CPU time 14.36 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:52 PM PDT 24
Peak memory 210364 kb
Host smart-afe87302-8694-42a0-9317-9edfcaf62b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.12419821
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3171055134
Short name T57
Test name
Test status
Simulation time 7750610426 ps
CPU time 15.24 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 210524 kb
Host smart-d212a879-06a1-426d-9c0e-cd94db523d3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171055134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3171055134
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.275292827
Short name T71
Test name
Test status
Simulation time 12353782484 ps
CPU time 13.3 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:34 PM PDT 24
Peak memory 218728 kb
Host smart-5fb054c7-79f4-4e19-a7ad-97bb753daa5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275292827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.275292827
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.441843417
Short name T103
Test name
Test status
Simulation time 1262037902 ps
CPU time 70.93 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:31:27 PM PDT 24
Peak memory 210388 kb
Host smart-5f36e98f-2514-47cf-95f1-c13d552739fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441843417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.441843417
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2663103939
Short name T74
Test name
Test status
Simulation time 551980231 ps
CPU time 4.23 seconds
Started Apr 04 12:30:29 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 211716 kb
Host smart-c5c2caf6-d8b9-4025-9414-d5d8cf462e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663103939 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2663103939
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1996030866
Short name T44
Test name
Test status
Simulation time 9456280444 ps
CPU time 9.98 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 210480 kb
Host smart-2c3132da-b91c-41e6-a261-9daa06e521c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996030866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1996030866
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1865693461
Short name T137
Test name
Test status
Simulation time 4427448566 ps
CPU time 10.91 seconds
Started Apr 04 12:30:29 PM PDT 24
Finished Apr 04 12:30:40 PM PDT 24
Peak memory 210556 kb
Host smart-e3ebb17d-0daf-4272-bbfa-5e88dd295c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865693461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1865693461
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.260729888
Short name T78
Test name
Test status
Simulation time 1210416089 ps
CPU time 10.23 seconds
Started Apr 04 12:30:22 PM PDT 24
Finished Apr 04 12:30:32 PM PDT 24
Peak memory 214832 kb
Host smart-d0ecc06d-1eae-4c82-88a5-a15b1f0601e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260729888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.260729888
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1482150395
Short name T75
Test name
Test status
Simulation time 7432494126 ps
CPU time 15.03 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 218692 kb
Host smart-1191a1a5-f1c6-4b23-8f3d-abe7149c7b8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482150395 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1482150395
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2292863705
Short name T82
Test name
Test status
Simulation time 333649177 ps
CPU time 4.1 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 210408 kb
Host smart-c4aacacc-4c68-426e-b2b6-ce17769e0d5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292863705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2292863705
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1883913187
Short name T61
Test name
Test status
Simulation time 102330709745 ps
CPU time 102.46 seconds
Started Apr 04 12:30:22 PM PDT 24
Finished Apr 04 12:32:04 PM PDT 24
Peak memory 210600 kb
Host smart-eeafcf63-8b04-46fd-a285-f3fa7c6a72ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883913187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1883913187
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2347426612
Short name T28
Test name
Test status
Simulation time 1047807620 ps
CPU time 10.27 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 210468 kb
Host smart-94dd41d3-8f50-48df-9fb6-cfc156ac1582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347426612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2347426612
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.329459393
Short name T142
Test name
Test status
Simulation time 936543955 ps
CPU time 13.81 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:40 PM PDT 24
Peak memory 218732 kb
Host smart-f4ebf5df-d3c8-451f-8e52-747cb4b46640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329459393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.329459393
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3017996879
Short name T70
Test name
Test status
Simulation time 345731459 ps
CPU time 36.98 seconds
Started Apr 04 12:30:28 PM PDT 24
Finished Apr 04 12:31:06 PM PDT 24
Peak memory 211484 kb
Host smart-ca2e50d8-08a5-4daf-b628-c90141abffba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017996879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3017996879
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3957663821
Short name T91
Test name
Test status
Simulation time 1623995232 ps
CPU time 13.58 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 213916 kb
Host smart-61f61b4e-e3ad-4d93-84fd-2f8d461800b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957663821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3957663821
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2223363052
Short name T88
Test name
Test status
Simulation time 1686093768 ps
CPU time 13.64 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:31:10 PM PDT 24
Peak memory 210508 kb
Host smart-de72209a-3f71-439e-babe-9b587998f4f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223363052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2223363052
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.535682021
Short name T47
Test name
Test status
Simulation time 12199718430 ps
CPU time 65.27 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 210580 kb
Host smart-616c7f2a-84b9-4357-b006-8615fd873124
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535682021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.535682021
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.630260900
Short name T144
Test name
Test status
Simulation time 699946475 ps
CPU time 7.39 seconds
Started Apr 04 12:31:40 PM PDT 24
Finished Apr 04 12:31:48 PM PDT 24
Peak memory 210436 kb
Host smart-21f75bea-2711-400d-90a1-6d6e363034c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630260900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.630260900
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1841546983
Short name T77
Test name
Test status
Simulation time 2065519109 ps
CPU time 11.63 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:58 PM PDT 24
Peak memory 218640 kb
Host smart-c4c4df57-7eca-4877-99bb-90816f94eca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841546983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1841546983
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2972583257
Short name T13
Test name
Test status
Simulation time 7568715067 ps
CPU time 40.77 seconds
Started Apr 04 12:30:44 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 211320 kb
Host smart-429762d4-bd84-4519-bc36-47a2d38c5d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972583257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2972583257
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3236917949
Short name T80
Test name
Test status
Simulation time 395513625 ps
CPU time 4.93 seconds
Started Apr 04 12:31:08 PM PDT 24
Finished Apr 04 12:31:13 PM PDT 24
Peak memory 213660 kb
Host smart-9cad64c0-ea08-4587-a5c6-c6adbf10e10f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236917949 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3236917949
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.902263959
Short name T131
Test name
Test status
Simulation time 5712050601 ps
CPU time 13.11 seconds
Started Apr 04 12:30:34 PM PDT 24
Finished Apr 04 12:30:47 PM PDT 24
Peak memory 210540 kb
Host smart-f6e6c249-4a01-4a33-8468-723c7082f724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902263959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.902263959
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4017246449
Short name T55
Test name
Test status
Simulation time 1098886688 ps
CPU time 27.56 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:31:40 PM PDT 24
Peak memory 210492 kb
Host smart-0d0007ab-e659-47f4-9891-219c4c373673
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017246449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4017246449
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2571017293
Short name T100
Test name
Test status
Simulation time 91159251 ps
CPU time 4.24 seconds
Started Apr 04 12:30:33 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 210368 kb
Host smart-84064a86-52de-4fb3-87eb-adee5db99816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571017293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2571017293
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3148877234
Short name T73
Test name
Test status
Simulation time 987444147 ps
CPU time 12.38 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:50 PM PDT 24
Peak memory 218500 kb
Host smart-8e95e685-aeee-4fd1-8e04-96574eb156a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148877234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3148877234
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3650974170
Short name T36
Test name
Test status
Simulation time 4797350682 ps
CPU time 75.41 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 211564 kb
Host smart-7e06ebd3-285f-462f-b3ce-06387091c6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650974170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3650974170
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3071352874
Short name T94
Test name
Test status
Simulation time 450815958 ps
CPU time 5.11 seconds
Started Apr 04 12:30:33 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 218612 kb
Host smart-bd40d8e2-be14-478f-9028-4f48a097cc5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071352874 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3071352874
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2334101887
Short name T30
Test name
Test status
Simulation time 4378262133 ps
CPU time 8.51 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:31:27 PM PDT 24
Peak memory 210568 kb
Host smart-431948b6-400b-4c57-8cbc-59cec5e8ec23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334101887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2334101887
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.837337062
Short name T141
Test name
Test status
Simulation time 8233989444 ps
CPU time 63.18 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:31:29 PM PDT 24
Peak memory 210588 kb
Host smart-44ef11b7-9525-48f0-bd7e-8b1e74518b5d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837337062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.837337062
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1938449499
Short name T121
Test name
Test status
Simulation time 178945363 ps
CPU time 4.11 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:30:35 PM PDT 24
Peak memory 210492 kb
Host smart-c51cf335-0b19-4636-a65e-3d2d40e3d49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938449499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1938449499
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.230599641
Short name T95
Test name
Test status
Simulation time 2111326379 ps
CPU time 19.32 seconds
Started Apr 04 12:30:50 PM PDT 24
Finished Apr 04 12:31:10 PM PDT 24
Peak memory 214864 kb
Host smart-c1f86c1d-f770-4124-9655-26417561c676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230599641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.230599641
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2869273023
Short name T4
Test name
Test status
Simulation time 4322414426 ps
CPU time 41.77 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 211592 kb
Host smart-a82c8e28-2876-4c88-a215-166a1b7dd193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869273023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2869273023
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3357730267
Short name T106
Test name
Test status
Simulation time 9290965244 ps
CPU time 12.71 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:39 PM PDT 24
Peak memory 212100 kb
Host smart-b624ae53-5f09-4671-b047-4efaba6d70e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357730267 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3357730267
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2867088106
Short name T87
Test name
Test status
Simulation time 93852780 ps
CPU time 4.33 seconds
Started Apr 04 12:31:19 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 210428 kb
Host smart-830b95da-fdd3-4e3e-b235-d686c7174709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867088106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2867088106
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1418235806
Short name T123
Test name
Test status
Simulation time 4545849785 ps
CPU time 9.1 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:55 PM PDT 24
Peak memory 210460 kb
Host smart-4970df29-7a79-41f9-a15c-b95a49ac73a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418235806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1418235806
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2725926824
Short name T72
Test name
Test status
Simulation time 933072014 ps
CPU time 8.08 seconds
Started Apr 04 12:30:24 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 218776 kb
Host smart-10c4d1a2-dec0-42f8-8ded-6492ac6ffad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725926824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2725926824
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1638975798
Short name T66
Test name
Test status
Simulation time 10584523297 ps
CPU time 79.22 seconds
Started Apr 04 12:30:58 PM PDT 24
Finished Apr 04 12:32:18 PM PDT 24
Peak memory 212680 kb
Host smart-288fc413-1ba4-47c5-9e74-5ca447f24a37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638975798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1638975798
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.32943287
Short name T125
Test name
Test status
Simulation time 90131584 ps
CPU time 4.17 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:10 PM PDT 24
Peak memory 210372 kb
Host smart-07c55fc7-5292-4286-935a-7afd2a76115b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32943287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasi
ng.32943287
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1902639113
Short name T129
Test name
Test status
Simulation time 41716485942 ps
CPU time 17.43 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:28:06 PM PDT 24
Peak memory 210188 kb
Host smart-c1096b1e-7e48-4c2a-9525-8835fb3b986c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902639113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1902639113
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3799836567
Short name T112
Test name
Test status
Simulation time 1586704133 ps
CPU time 14.87 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 210456 kb
Host smart-f2115ec3-2dc2-4b54-b5d5-52975de0ae0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799836567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3799836567
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3735998658
Short name T22
Test name
Test status
Simulation time 3144010673 ps
CPU time 16.72 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:39 PM PDT 24
Peak memory 218808 kb
Host smart-268af61f-fafd-4a7b-9808-156614226f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735998658 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3735998658
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1532756698
Short name T1
Test name
Test status
Simulation time 7412784863 ps
CPU time 14.69 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:29:07 PM PDT 24
Peak memory 209660 kb
Host smart-02471569-290d-4f27-8de9-9dcd5ec3ab7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532756698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1532756698
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3670892387
Short name T51
Test name
Test status
Simulation time 2069379523 ps
CPU time 14.93 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:28:05 PM PDT 24
Peak memory 210192 kb
Host smart-37d176a4-e1e9-4e3c-be63-ba0a5f5c738c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670892387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3670892387
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1816745011
Short name T114
Test name
Test status
Simulation time 8834601078 ps
CPU time 16.53 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:21 PM PDT 24
Peak memory 210436 kb
Host smart-5939876d-0d00-4fe6-841c-ca646420e05d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816745011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1816745011
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.720381675
Short name T140
Test name
Test status
Simulation time 4917856949 ps
CPU time 26.32 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:28:16 PM PDT 24
Peak memory 210288 kb
Host smart-0f51116f-f466-443c-ab76-3f2c3bad708b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720381675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.720381675
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3034178551
Short name T109
Test name
Test status
Simulation time 1713769764 ps
CPU time 14.7 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:11 PM PDT 24
Peak memory 210244 kb
Host smart-720a6486-abd2-4657-9e57-f83e5b1ea548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034178551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3034178551
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1667816895
Short name T104
Test name
Test status
Simulation time 1763607491 ps
CPU time 18.02 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 218004 kb
Host smart-fe2eb7ce-a523-4183-9edf-1b77728e989c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667816895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1667816895
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3106398684
Short name T65
Test name
Test status
Simulation time 1084659103 ps
CPU time 40.52 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:28:30 PM PDT 24
Peak memory 210940 kb
Host smart-54a65a51-5491-4d46-8d6f-da5457a5c048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106398684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3106398684
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2438869826
Short name T54
Test name
Test status
Simulation time 1927298560 ps
CPU time 14.76 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 210324 kb
Host smart-0e5041c2-5fce-4b23-a516-2b128f70d862
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438869826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2438869826
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2927104684
Short name T60
Test name
Test status
Simulation time 335355073 ps
CPU time 6.42 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:01 PM PDT 24
Peak memory 209636 kb
Host smart-a7dfc5ef-4e8d-4a36-a1ae-1d7bbd902a92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927104684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2927104684
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2553551973
Short name T49
Test name
Test status
Simulation time 837502802 ps
CPU time 10.59 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 210452 kb
Host smart-a9614d77-f2ac-4d96-b5f5-f1228ecdddf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553551973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2553551973
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3813403112
Short name T139
Test name
Test status
Simulation time 187517356 ps
CPU time 4.6 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:08 PM PDT 24
Peak memory 218332 kb
Host smart-5aae5abd-8c2c-4972-8fd6-8823ba5c84a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813403112 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3813403112
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1179922750
Short name T42
Test name
Test status
Simulation time 2062475082 ps
CPU time 15.48 seconds
Started Apr 04 12:29:14 PM PDT 24
Finished Apr 04 12:29:30 PM PDT 24
Peak memory 210484 kb
Host smart-02217b2d-1416-49d5-a815-3d8b6f30857e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179922750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1179922750
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.168780480
Short name T133
Test name
Test status
Simulation time 93930656 ps
CPU time 3.94 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:01 PM PDT 24
Peak memory 209596 kb
Host smart-63f125bb-1fc9-4187-8bc5-70fcf7af0184
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168780480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.168780480
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3051060160
Short name T81
Test name
Test status
Simulation time 346750041 ps
CPU time 4.02 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 210008 kb
Host smart-64058910-a559-4b98-8bbd-c21ca49f68e9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051060160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3051060160
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2992018396
Short name T130
Test name
Test status
Simulation time 3414105345 ps
CPU time 27.82 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:29:21 PM PDT 24
Peak memory 210216 kb
Host smart-11629509-2b38-4a88-a06a-e2aa17412bd2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992018396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2992018396
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1803009713
Short name T97
Test name
Test status
Simulation time 1831596078 ps
CPU time 10 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:32 PM PDT 24
Peak memory 210348 kb
Host smart-8ea01a8d-9c74-4cba-af97-498f9f4d8f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803009713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1803009713
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.74438815
Short name T108
Test name
Test status
Simulation time 532005569 ps
CPU time 9.14 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:29:02 PM PDT 24
Peak memory 218300 kb
Host smart-4c8e1d6f-55a8-461f-9db7-9d7facc8b79b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74438815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.74438815
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2440681972
Short name T143
Test name
Test status
Simulation time 345191204 ps
CPU time 6.52 seconds
Started Apr 04 12:28:34 PM PDT 24
Finished Apr 04 12:28:40 PM PDT 24
Peak memory 210312 kb
Host smart-7a813c4d-b82c-43eb-9583-b200e6e542ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440681972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2440681972
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1417856741
Short name T27
Test name
Test status
Simulation time 5579615964 ps
CPU time 13.31 seconds
Started Apr 04 12:28:30 PM PDT 24
Finished Apr 04 12:28:43 PM PDT 24
Peak memory 210448 kb
Host smart-9031218a-fda7-4e66-9eb2-431bf781901b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417856741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1417856741
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1549644928
Short name T52
Test name
Test status
Simulation time 14266576298 ps
CPU time 16.46 seconds
Started Apr 04 12:28:23 PM PDT 24
Finished Apr 04 12:28:40 PM PDT 24
Peak memory 210468 kb
Host smart-0d992cd0-7ccd-4ff7-9f51-989ac9164217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549644928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1549644928
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.900659533
Short name T117
Test name
Test status
Simulation time 7251392876 ps
CPU time 14.76 seconds
Started Apr 04 12:28:32 PM PDT 24
Finished Apr 04 12:28:47 PM PDT 24
Peak memory 210448 kb
Host smart-5e465c1a-e834-4809-bf67-33c9c31a5d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900659533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.900659533
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.660556117
Short name T98
Test name
Test status
Simulation time 5995081798 ps
CPU time 14.3 seconds
Started Apr 04 12:28:17 PM PDT 24
Finished Apr 04 12:28:31 PM PDT 24
Peak memory 210316 kb
Host smart-352a566e-a1a6-47d9-be84-ae223a967d8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660556117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.660556117
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4238572408
Short name T21
Test name
Test status
Simulation time 1382373635 ps
CPU time 12.84 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:28 PM PDT 24
Peak memory 210308 kb
Host smart-9004abd6-4a8d-4f71-babe-5b9d93f51f32
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238572408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4238572408
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1683405689
Short name T31
Test name
Test status
Simulation time 5735239457 ps
CPU time 49.52 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:29:57 PM PDT 24
Peak memory 210456 kb
Host smart-9c999589-af9f-4670-8c3e-6bbc2baac6dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683405689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1683405689
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2601401981
Short name T59
Test name
Test status
Simulation time 6584208491 ps
CPU time 13.85 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 210456 kb
Host smart-1399e1bb-6997-4550-ba7d-0843f760b1cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601401981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2601401981
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.398767668
Short name T20
Test name
Test status
Simulation time 4884021627 ps
CPU time 76.6 seconds
Started Apr 04 12:28:50 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 210604 kb
Host smart-5b5c4a58-6a22-4bb2-beb5-ff86782b48ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398767668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.398767668
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2648425846
Short name T115
Test name
Test status
Simulation time 3742534434 ps
CPU time 9.86 seconds
Started Apr 04 12:28:44 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 211292 kb
Host smart-34925374-05e6-4644-a6af-e9b2fcc5ec3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648425846 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2648425846
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.699390515
Short name T40
Test name
Test status
Simulation time 1690885910 ps
CPU time 7.26 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:18 PM PDT 24
Peak memory 210376 kb
Host smart-93e27e2b-cd81-488d-9242-c5da41101a73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699390515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.699390515
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.804838415
Short name T34
Test name
Test status
Simulation time 3154803261 ps
CPU time 29.14 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:48 PM PDT 24
Peak memory 210496 kb
Host smart-eb93fa1f-131a-4775-81f1-9cd511707d7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804838415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.804838415
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2727523162
Short name T86
Test name
Test status
Simulation time 174950639 ps
CPU time 4.26 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:17 PM PDT 24
Peak memory 210488 kb
Host smart-02a4abf6-4866-408c-923e-a53a8ba90c6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727523162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2727523162
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.646117440
Short name T93
Test name
Test status
Simulation time 1028381044 ps
CPU time 10.98 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:26 PM PDT 24
Peak memory 213368 kb
Host smart-8bb82a63-20e6-4589-9dfc-22748d7b8919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646117440 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.646117440
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1427288072
Short name T53
Test name
Test status
Simulation time 1377745229 ps
CPU time 4.12 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 210352 kb
Host smart-bf467690-3b9e-4021-b283-1da5190431cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427288072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1427288072
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3020579444
Short name T10
Test name
Test status
Simulation time 17100421843 ps
CPU time 65.25 seconds
Started Apr 04 12:29:16 PM PDT 24
Finished Apr 04 12:30:21 PM PDT 24
Peak memory 210452 kb
Host smart-a82e3da6-d871-4802-8268-29b9af5d30dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020579444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3020579444
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.558422504
Short name T127
Test name
Test status
Simulation time 5624536434 ps
CPU time 12.69 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 210472 kb
Host smart-6a19076e-10e8-4394-842f-ed53bb220d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558422504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.558422504
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1221659762
Short name T99
Test name
Test status
Simulation time 1812459562 ps
CPU time 77.77 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:31:12 PM PDT 24
Peak memory 211276 kb
Host smart-dc1f9553-91c6-4741-80b3-0f49ab090010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221659762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1221659762
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3385816522
Short name T120
Test name
Test status
Simulation time 9821076607 ps
CPU time 10.99 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:28:00 PM PDT 24
Peak memory 218468 kb
Host smart-4ae8213d-0385-4dd9-b8da-e3f649aebce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385816522 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3385816522
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.342980938
Short name T58
Test name
Test status
Simulation time 232156207 ps
CPU time 4.08 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:27:53 PM PDT 24
Peak memory 210048 kb
Host smart-434e6e59-e77e-4468-8eb2-8072abc045ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342980938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.342980938
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1624952773
Short name T32
Test name
Test status
Simulation time 12773182842 ps
CPU time 35.15 seconds
Started Apr 04 12:29:36 PM PDT 24
Finished Apr 04 12:30:11 PM PDT 24
Peak memory 210404 kb
Host smart-a3793882-7f7b-4ced-a27c-0361d092d800
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624952773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1624952773
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.238635998
Short name T50
Test name
Test status
Simulation time 2519614207 ps
CPU time 11.36 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 210304 kb
Host smart-ae2a5b1c-be70-4b36-baad-bf7b1503fdba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238635998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.238635998
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2060737131
Short name T11
Test name
Test status
Simulation time 293408243 ps
CPU time 7.81 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:54 PM PDT 24
Peak memory 218652 kb
Host smart-f0fb3d6a-8d25-458b-9e3d-b8cdd79fce03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060737131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2060737131
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4022209937
Short name T110
Test name
Test status
Simulation time 1626524111 ps
CPU time 44.36 seconds
Started Apr 04 12:28:50 PM PDT 24
Finished Apr 04 12:29:35 PM PDT 24
Peak memory 210100 kb
Host smart-ce62b086-da5a-458b-b3ad-3641f1e73aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022209937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4022209937
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3870559790
Short name T38
Test name
Test status
Simulation time 498375783 ps
CPU time 7.48 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:27:56 PM PDT 24
Peak memory 210124 kb
Host smart-4271bbc9-0d43-4243-bb1d-fade8c8d932a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870559790 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3870559790
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1191614996
Short name T107
Test name
Test status
Simulation time 4244383739 ps
CPU time 10.5 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:29:16 PM PDT 24
Peak memory 210468 kb
Host smart-1d0967b6-806d-4cfb-bb77-e38797b1b888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191614996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1191614996
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3866488665
Short name T46
Test name
Test status
Simulation time 2473740430 ps
CPU time 27.21 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:29:18 PM PDT 24
Peak memory 209716 kb
Host smart-f4a70599-5a68-4074-85aa-07df498fd93e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866488665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3866488665
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.877422616
Short name T84
Test name
Test status
Simulation time 5735789529 ps
CPU time 12.38 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:28:01 PM PDT 24
Peak memory 210204 kb
Host smart-97883a88-515b-4be6-8aad-9fcdbea181f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877422616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.877422616
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3746780936
Short name T26
Test name
Test status
Simulation time 1274844888 ps
CPU time 13.55 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:28:02 PM PDT 24
Peak memory 218032 kb
Host smart-244bedb6-c267-4fae-916e-3ff929c46081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746780936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3746780936
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.104169461
Short name T18
Test name
Test status
Simulation time 13477720723 ps
CPU time 38.7 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:28:29 PM PDT 24
Peak memory 218436 kb
Host smart-3078a901-f381-4923-9668-74f55a0048ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104169461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.104169461
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.141180465
Short name T113
Test name
Test status
Simulation time 499597651 ps
CPU time 7.65 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:29:03 PM PDT 24
Peak memory 217376 kb
Host smart-6df96f90-efc3-4908-95f4-0e4a1724b18d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141180465 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.141180465
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3082599916
Short name T43
Test name
Test status
Simulation time 2021222669 ps
CPU time 15.49 seconds
Started Apr 04 12:28:56 PM PDT 24
Finished Apr 04 12:29:12 PM PDT 24
Peak memory 210224 kb
Host smart-89fe3945-3f45-4080-b753-9a01d53330a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082599916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3082599916
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.377255289
Short name T45
Test name
Test status
Simulation time 10574380685 ps
CPU time 83.02 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 211564 kb
Host smart-491c9da5-6c04-4afa-8aff-5af727a0c5b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377255289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.377255289
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4242386315
Short name T17
Test name
Test status
Simulation time 5443471209 ps
CPU time 9.21 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:29:02 PM PDT 24
Peak memory 210204 kb
Host smart-e2eab522-81cb-48ab-a4fa-86e0db5ae5d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242386315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4242386315
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1489167118
Short name T119
Test name
Test status
Simulation time 3434637034 ps
CPU time 18.11 seconds
Started Apr 04 12:28:56 PM PDT 24
Finished Apr 04 12:29:15 PM PDT 24
Peak memory 218540 kb
Host smart-aa56bf14-c5cf-491d-899f-abdbf14e3dec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489167118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1489167118
Directory /workspace/9.rom_ctrl_tl_errors/latest
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