1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 0 | 50 | 0.00 | ||
| V2 | stress_all | rom_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||
| V2 | alert_test | rom_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 240 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 95 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 500 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 6 | 6 | 0 | 0.00 |
| V2S | 4 | 4 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 500 failures:
0.rom_ctrl_smoke.93679030601604628402995999928944103861633199344745552537398296405104987579367
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_smoke/latest/run.log
1.rom_ctrl_smoke.113168786385708567312056271446474314865211482846837043030758826691658322932223
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log
... and 48 more failures.
0.rom_ctrl_stress_all.23171280580265293827704814549501221568185331528688346849481657832295944282662
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
1.rom_ctrl_stress_all.76469656775053638168507762887857164430705059342156834784249233973798489320832
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
... and 48 more failures.
0.rom_ctrl_max_throughput_chk.45624909364545597635997488688124125349126946412155934783721550283748821386700
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
1.rom_ctrl_max_throughput_chk.57304748701128636054613063438079563375662875372345570062002865895871750439681
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_corrupt_sig_fatal_chk.11401539899081740455548491029658584302404249837359555061506037753203335646224
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
1.rom_ctrl_corrupt_sig_fatal_chk.74968521790656968117934086790705127686723644083205783863840629079482381205084
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_kmac_err_chk.90498262343677540733792178125046904372764970782667613502322815042522310652014
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
1.rom_ctrl_kmac_err_chk.45028710129138963819307750452727681073777031201365597378625560456589224297625
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log