ROM_CTRL/32KB Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.529m	32.106ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.190s	1.973ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.310s	2.146ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.080s	4.381ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.720s	1.807ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.140s	8.920ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.310s	2.146ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.720s	1.807ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.040s	18.613ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.130s	24.594ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.140s	18.499ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	5.114m	109.494ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.132m	15.684ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.610s	37.866ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.620s	9.670ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.620s	9.670ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.190s	1.973ms	5	5	100.00
		rom_ctrl_csr_rw	16.310s	2.146ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.720s	1.807ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.580s	2.183ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.190s	1.973ms	5	5	100.00
		rom_ctrl_csr_rw	16.310s	2.146ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.720s	1.807ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.580s	2.183ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.643m	25.739ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.917m	1.608ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.318m	29.078ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.917m	1.608ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.917m	1.608ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.917m	1.608ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.529m	32.106ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.529m	32.106ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.529m	32.106ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.318m	29.078ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.132m	15.684ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.859m	426.521ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.643m	25.739ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.917m	1.608ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.032h	195.499ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			459	500	91.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.34353439988271250432129190192463584704651904100025097983502343488437666833357
      Line 641, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 195498848757 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 195498848757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_ctrl_stress_all_with_rand_reset.96362695157625952587756296347004174160983008693524971264514498833096044865101
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 424951187 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 424951187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 6 failures.

    • 9.rom_ctrl_stress_all_with_rand_reset.55126579045395323305348449568254722119686011809339687071522319406825333547984
      Line 268, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10110783404 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x55d6a177
        UVM_INFO @ 10110783404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.rom_ctrl_stress_all_with_rand_reset.113981897361566259418012207609258929459428660776667637455690652448157778613959
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10864734466 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x20f6488d
        UVM_INFO @ 10864734466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.39924963441364699312469530512030074148265337604664290463679283016467753102727
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a85c293c-da6a-4024-ad9e-d2998fb44049
      

    • 20.rom_ctrl_stress_all_with_rand_reset.32702081371239735427496710372516117067705622961102915962402540918821419448124
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:9460c0d2-550f-4035-bc45-22d0eb9fcef2
      

    • ... and 3 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test rom_ctrl_stress_all has 2 failures.

    • 39.rom_ctrl_stress_all.98124519575475623859591612423520338054888228240075911844156712478316199560680
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/39.rom_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 40029045118 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x89a68c09
        UVM_INFO @ 40029045118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.rom_ctrl_stress_all.46189510242097983776233882532993624372649838841631898779493087351816486507833
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/47.rom_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 40037916548 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x26d26a32
        UVM_INFO @ 40037916548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job rom_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:

  • Test rom_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:f482faf6-c6da-4bf8-aaab-0378a093291e
      

Past Results

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