2723ca659d
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 16.460s | 14.267ms | 5 | 5 | 100.00 |
V1 | csr_rw | rom_ctrl_csr_rw | 15.490s | 2.021ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 17.430s | 41.716ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rom_ctrl_csr_aliasing | 14.930s | 3.787ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.720s | 3.144ms | 19 | 20 | 95.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 15.490s | 2.021ms | 20 | 20 | 100.00 |
rom_ctrl_csr_aliasing | 14.930s | 3.787ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | rom_ctrl_mem_walk | 16.530s | 8.835ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | rom_ctrl_mem_partial_access | 15.980s | 2.052ms | 5 | 5 | 100.00 |
V1 | TOTAL | 64 | 115 | 55.65 | |||
V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 0 | 50 | 0.00 | ||
V2 | stress_all | rom_ctrl_stress_all | 0 | 50 | 0.00 | ||
V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||
V2 | alert_test | rom_ctrl_alert_test | 0 | 50 | 0.00 | ||
V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 19.940s | 8.498ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 19.940s | 8.498ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 16.460s | 14.267ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 15.490s | 2.021ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 14.930s | 3.787ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 15.490s | 3.316ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 16.460s | 14.267ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 15.490s | 2.021ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 14.930s | 3.787ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 15.490s | 3.316ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 40 | 240 | 16.67 | |||
V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.708m | 102.331ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
rom_ctrl_tl_intg_err | 1.320m | 10.585ms | 20 | 20 | 100.00 | ||
V2S | prim_fsm_check | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
V2S | sec_cm_mem_digest | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.320m | 10.585ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||||
V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.708m | 102.331ms | 20 | 20 | 100.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
V2S | TOTAL | 40 | 95 | 42.11 | |||
V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 144 | 500 | 28.80 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 6 | 75.00 |
V2 | 6 | 6 | 2 | 33.33 |
V2S | 4 | 4 | 2 | 50.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
57.99 | 39.18 | 35.44 | 91.88 | 0.00 | 44.08 | 98.63 | 96.74 |
Job killed most likely because its dependent job failed.
has 355 failures:
0.rom_ctrl_smoke.66677864266609764768860289895746050380135862142591209913329035548260746943751
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_smoke/latest/run.log
1.rom_ctrl_smoke.51750156848503664585074617880550376317109942800607051239949989483998327732825
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log
... and 48 more failures.
0.rom_ctrl_stress_all.58572418314983913505379970350114734498802234005030139252902563567409016088875
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
1.rom_ctrl_stress_all.65325028204209650052486355061238560425288143784770376049565092655014662810275
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
... and 48 more failures.
0.rom_ctrl_max_throughput_chk.8872803007335116897969949147954796988881893976582732640187723248711073301985
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
1.rom_ctrl_max_throughput_chk.52225118005757844737424281976676307026904879428102840752961632931941817195159
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_corrupt_sig_fatal_chk.5550072248278473949350411681025858581536483034743155619551911917818349631693
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
1.rom_ctrl_corrupt_sig_fatal_chk.114769574583434425836636050303448985051435335626001118720176457925643664993735
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_kmac_err_chk.7893889244918508354693874348850250168983392833276817591504347488555549121751
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
1.rom_ctrl_kmac_err_chk.113931984717682115202718927222829566568136906258615991133699093468694306217764
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
... and 48 more failures.
tar (child): /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/default/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now
has 1 failures:
Exit reason: Error: User command failed Job returned non-zero exit code
has 1 failures:
12.rom_ctrl_csr_mem_rw_with_rand_reset.81739961149161277615398470212345915390457580633334372247580440158319277516962
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093833890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3093833890
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Apr 4 12:30 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255