ROM_CTRL/64KB Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 0 50 0.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 16.460s 14.267ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 15.490s 2.021ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 17.430s 41.716ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 14.930s 3.787ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 16.720s 3.144ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 15.490s 2.021ms 20 20 100.00
rom_ctrl_csr_aliasing 14.930s 3.787ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 16.530s 8.835ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 15.980s 2.052ms 5 5 100.00
V1 TOTAL 64 115 55.65
V2 max_throughput_chk rom_ctrl_max_throughput_chk 0 50 0.00
V2 stress_all rom_ctrl_stress_all 0 50 0.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 0 50 0.00
V2 alert_test rom_ctrl_alert_test 0 50 0.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 19.940s 8.498ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 19.940s 8.498ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 16.460s 14.267ms 5 5 100.00
rom_ctrl_csr_rw 15.490s 2.021ms 20 20 100.00
rom_ctrl_csr_aliasing 14.930s 3.787ms 5 5 100.00
rom_ctrl_same_csr_outstanding 15.490s 3.316ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 16.460s 14.267ms 5 5 100.00
rom_ctrl_csr_rw 15.490s 2.021ms 20 20 100.00
rom_ctrl_csr_aliasing 14.930s 3.787ms 5 5 100.00
rom_ctrl_same_csr_outstanding 15.490s 3.316ms 20 20 100.00
V2 TOTAL 40 240 16.67
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.708m 102.331ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 0 5 0.00
rom_ctrl_tl_intg_err 1.320m 10.585ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 0 5 0.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 0 5 0.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 0 5 0.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 0 50 0.00
V2S sec_cm_mem_digest rom_ctrl_smoke 0 50 0.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 0 50 0.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.320m 10.585ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
rom_ctrl_kmac_err_chk 0 50 0.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 50 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.708m 102.331ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 0 5 0.00
V2S TOTAL 40 95 42.11
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 144 500 28.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 6 75.00
V2 6 6 2 33.33
V2S 4 4 2 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
57.99 39.18 35.44 91.88 0.00 44.08 98.63 96.74

Failure Buckets

Past Results