ROM_CTRL/32KB Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.880s	4.162ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.130s	10.034ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.430s	9.498ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.590s	10.190ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.210s	1.985ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.200s	2.195ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.430s	9.498ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.210s	1.985ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.380s	1.792ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.490s	13.497ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.030s	8.235ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.453m	7.959ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.980s	7.467ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.840s	2.193ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.160s	29.181ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.160s	29.181ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.130s	10.034ms	5	5	100.00
		rom_ctrl_csr_rw	15.430s	9.498ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.210s	1.985ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.530s	15.901ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.130s	10.034ms	5	5	100.00
		rom_ctrl_csr_rw	15.430s	9.498ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.210s	1.985ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.530s	15.901ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.609m	50.375ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.992m	4.629ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.306m	8.768ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.992m	4.629ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.992m	4.629ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.992m	4.629ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.880s	4.162ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.880s	4.162ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.880s	4.162ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.306m	8.768ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.980s	7.467ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.481m	238.963ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.609m	50.375ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.992m	4.629ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.482h	34.229ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	96.97	93.44	97.88	100.00	98.69	97.88	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 30 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.87980843002107525075002265225079745598057842678541634399601892209225148952542
      Line 322, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30111467462 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30111467462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.rom_ctrl_stress_all_with_rand_reset.24703127900460582336729606329544682859765977871484389743855782708144261488198
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2569004321 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2569004321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 8 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.85662661840045398381704963143419074980169256967114762701072376137805423569042
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7e9535c3-3198-4f76-8240-34d739990747
      

    • 9.rom_ctrl_stress_all_with_rand_reset.72056101124756201973162627417074481358375125345903176014259069258703901324273
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:f8620dd8-7939-472b-958f-07fa4391d6ea
      

    • ... and 6 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.rom_ctrl_stress_all_with_rand_reset.96056383320523843979410206183375348194568747457286219179134600034825853719284
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10007406962 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xef295ab7
        UVM_INFO @ 10007406962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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