SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.49 | 96.89 | 92.13 | 97.67 | 100.00 | 98.62 | 98.05 | 99.06 |
T296 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2073010420 | Aug 23 06:12:18 AM UTC 24 | Aug 23 06:12:25 AM UTC 24 | 548719445 ps | ||
T297 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3268686338 | Aug 23 06:12:18 AM UTC 24 | Aug 23 06:12:29 AM UTC 24 | 799084351 ps | ||
T298 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2080519993 | Aug 23 06:10:47 AM UTC 24 | Aug 23 06:12:29 AM UTC 24 | 6592446161 ps | ||
T299 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2677422878 | Aug 23 06:12:20 AM UTC 24 | Aug 23 06:12:31 AM UTC 24 | 301612466 ps | ||
T120 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1650572252 | Aug 23 06:08:09 AM UTC 24 | Aug 23 06:12:31 AM UTC 24 | 30818187290 ps | ||
T300 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2056991892 | Aug 23 06:12:26 AM UTC 24 | Aug 23 06:12:32 AM UTC 24 | 257050547 ps | ||
T301 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.388971199 | Aug 23 06:12:30 AM UTC 24 | Aug 23 06:12:36 AM UTC 24 | 100021737 ps | ||
T302 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1685724921 | Aug 23 06:10:38 AM UTC 24 | Aug 23 06:12:43 AM UTC 24 | 8362117338 ps | ||
T303 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.821091747 | Aug 23 06:12:32 AM UTC 24 | Aug 23 06:12:43 AM UTC 24 | 1916381374 ps | ||
T304 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1384427299 | Aug 23 06:12:30 AM UTC 24 | Aug 23 06:12:45 AM UTC 24 | 1106723133 ps | ||
T305 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.896966318 | Aug 23 06:12:37 AM UTC 24 | Aug 23 06:12:45 AM UTC 24 | 546230286 ps | ||
T306 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2643451421 | Aug 23 06:12:45 AM UTC 24 | Aug 23 06:12:51 AM UTC 24 | 373668451 ps | ||
T307 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2889228052 | Aug 23 06:12:44 AM UTC 24 | Aug 23 06:12:53 AM UTC 24 | 149463085 ps | ||
T308 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1796217764 | Aug 23 06:11:15 AM UTC 24 | Aug 23 06:12:53 AM UTC 24 | 13176314503 ps | ||
T309 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2652746702 | Aug 23 06:11:34 AM UTC 24 | Aug 23 06:12:55 AM UTC 24 | 8625124632 ps | ||
T310 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2156044787 | Aug 23 06:12:54 AM UTC 24 | Aug 23 06:13:00 AM UTC 24 | 250833371 ps | ||
T311 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2243232534 | Aug 23 06:11:27 AM UTC 24 | Aug 23 06:13:01 AM UTC 24 | 2929055731 ps | ||
T312 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3534905834 | Aug 23 06:12:46 AM UTC 24 | Aug 23 06:13:01 AM UTC 24 | 5481706227 ps | ||
T313 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2850869466 | Aug 23 06:12:55 AM UTC 24 | Aug 23 06:13:02 AM UTC 24 | 197757668 ps | ||
T314 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2237768388 | Aug 23 06:12:54 AM UTC 24 | Aug 23 06:13:05 AM UTC 24 | 171028351 ps | ||
T315 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1386006343 | Aug 23 06:11:25 AM UTC 24 | Aug 23 06:13:08 AM UTC 24 | 3469595637 ps | ||
T316 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3580225553 | Aug 23 06:13:03 AM UTC 24 | Aug 23 06:13:08 AM UTC 24 | 127859358 ps | ||
T317 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1175268150 | Aug 23 06:12:22 AM UTC 24 | Aug 23 06:13:12 AM UTC 24 | 1322113909 ps | ||
T318 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.87561854 | Aug 23 06:13:02 AM UTC 24 | Aug 23 06:13:13 AM UTC 24 | 1466670116 ps | ||
T319 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2514093075 | Aug 23 06:11:42 AM UTC 24 | Aug 23 06:13:14 AM UTC 24 | 7124363530 ps | ||
T320 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4191473469 | Aug 23 06:13:09 AM UTC 24 | Aug 23 06:13:15 AM UTC 24 | 408480946 ps | ||
T321 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4243029004 | Aug 23 06:11:53 AM UTC 24 | Aug 23 06:13:16 AM UTC 24 | 1879710017 ps | ||
T322 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1783572102 | Aug 23 06:13:06 AM UTC 24 | Aug 23 06:13:16 AM UTC 24 | 592882728 ps | ||
T323 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2096031436 | Aug 23 06:10:40 AM UTC 24 | Aug 23 06:13:16 AM UTC 24 | 2906542568 ps | ||
T324 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1847454204 | Aug 23 06:13:16 AM UTC 24 | Aug 23 06:13:20 AM UTC 24 | 88080337 ps | ||
T325 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.868953186 | Aug 23 06:08:33 AM UTC 24 | Aug 23 06:13:22 AM UTC 24 | 9660084747 ps | ||
T326 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3205890510 | Aug 23 06:13:17 AM UTC 24 | Aug 23 06:13:23 AM UTC 24 | 102480351 ps | ||
T327 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1473304341 | Aug 23 06:13:13 AM UTC 24 | Aug 23 06:13:23 AM UTC 24 | 1838775868 ps | ||
T328 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.234442457 | Aug 23 06:11:54 AM UTC 24 | Aug 23 06:13:23 AM UTC 24 | 2819700281 ps | ||
T329 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.775525666 | Aug 23 06:09:53 AM UTC 24 | Aug 23 06:13:25 AM UTC 24 | 4039888253 ps | ||
T330 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3290151761 | Aug 23 06:12:12 AM UTC 24 | Aug 23 06:13:27 AM UTC 24 | 29920644972 ps | ||
T331 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3223748025 | Aug 23 06:13:17 AM UTC 24 | Aug 23 06:13:28 AM UTC 24 | 259587307 ps | ||
T332 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2967422767 | Aug 23 06:13:23 AM UTC 24 | Aug 23 06:13:28 AM UTC 24 | 89097471 ps | ||
T333 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3369093548 | Aug 23 06:13:16 AM UTC 24 | Aug 23 06:13:30 AM UTC 24 | 1087831812 ps | ||
T334 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1187856476 | Aug 23 06:11:45 AM UTC 24 | Aug 23 06:13:31 AM UTC 24 | 2288996447 ps | ||
T335 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.169612099 | Aug 23 06:11:18 AM UTC 24 | Aug 23 06:13:32 AM UTC 24 | 8093144689 ps | ||
T336 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2295857842 | Aug 23 06:11:01 AM UTC 24 | Aug 23 06:13:33 AM UTC 24 | 3477363081 ps | ||
T337 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.426436896 | Aug 23 06:10:53 AM UTC 24 | Aug 23 06:13:33 AM UTC 24 | 90322154837 ps | ||
T338 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2721074405 | Aug 23 06:11:31 AM UTC 24 | Aug 23 06:13:38 AM UTC 24 | 9294039357 ps | ||
T339 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3858066762 | Aug 23 06:12:02 AM UTC 24 | Aug 23 06:13:46 AM UTC 24 | 7707290289 ps | ||
T340 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2797012633 | Aug 23 06:13:17 AM UTC 24 | Aug 23 06:14:08 AM UTC 24 | 1192965363 ps | ||
T341 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1930883218 | Aug 23 06:13:02 AM UTC 24 | Aug 23 06:14:11 AM UTC 24 | 2094162839 ps | ||
T342 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2181873348 | Aug 23 06:12:20 AM UTC 24 | Aug 23 06:14:22 AM UTC 24 | 7077771084 ps | ||
T343 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3187019779 | Aug 23 06:12:11 AM UTC 24 | Aug 23 06:14:23 AM UTC 24 | 32408111329 ps | ||
T344 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2170389249 | Aug 23 06:13:09 AM UTC 24 | Aug 23 06:14:27 AM UTC 24 | 17989239626 ps | ||
T345 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4204300943 | Aug 23 06:13:21 AM UTC 24 | Aug 23 06:14:34 AM UTC 24 | 1576667222 ps | ||
T346 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1304860407 | Aug 23 06:11:59 AM UTC 24 | Aug 23 06:14:38 AM UTC 24 | 3470406847 ps | ||
T347 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.763192292 | Aug 23 06:10:15 AM UTC 24 | Aug 23 06:14:40 AM UTC 24 | 9012025339 ps | ||
T348 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3220318823 | Aug 23 06:11:08 AM UTC 24 | Aug 23 06:14:47 AM UTC 24 | 17567410392 ps | ||
T349 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1303811065 | Aug 23 06:12:46 AM UTC 24 | Aug 23 06:15:02 AM UTC 24 | 3101483739 ps | ||
T350 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3249277340 | Aug 23 06:12:31 AM UTC 24 | Aug 23 06:15:08 AM UTC 24 | 13726861709 ps | ||
T351 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1070068505 | Aug 23 06:12:52 AM UTC 24 | Aug 23 06:15:08 AM UTC 24 | 8003778442 ps | ||
T352 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4220275745 | Aug 23 06:13:13 AM UTC 24 | Aug 23 06:15:20 AM UTC 24 | 9141815741 ps | ||
T353 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3637442493 | Aug 23 06:12:32 AM UTC 24 | Aug 23 06:15:49 AM UTC 24 | 3468997063 ps | ||
T354 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1010131001 | Aug 23 06:13:01 AM UTC 24 | Aug 23 06:15:52 AM UTC 24 | 50309116262 ps | ||
T69 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3811217192 | Aug 23 05:58:15 AM UTC 24 | Aug 23 05:58:33 AM UTC 24 | 3623646526 ps | ||
T355 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.102404934 | Aug 23 05:58:27 AM UTC 24 | Aug 23 05:58:35 AM UTC 24 | 333727392 ps | ||
T356 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.901124824 | Aug 23 05:58:36 AM UTC 24 | Aug 23 05:58:41 AM UTC 24 | 369476142 ps | ||
T357 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1690920501 | Aug 23 05:58:42 AM UTC 24 | Aug 23 05:58:47 AM UTC 24 | 366592590 ps | ||
T70 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1939800155 | Aug 23 05:58:47 AM UTC 24 | Aug 23 05:58:54 AM UTC 24 | 94562958 ps | ||
T71 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3596080244 | Aug 23 05:58:51 AM UTC 24 | Aug 23 05:58:56 AM UTC 24 | 92088977 ps | ||
T105 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3224096884 | Aug 23 05:58:54 AM UTC 24 | Aug 23 05:59:00 AM UTC 24 | 245860175 ps | ||
T75 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2754269737 | Aug 23 05:58:56 AM UTC 24 | Aug 23 05:59:02 AM UTC 24 | 1131969765 ps | ||
T99 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1133474205 | Aug 23 05:59:00 AM UTC 24 | Aug 23 05:59:06 AM UTC 24 | 132584804 ps | ||
T358 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2254866626 | Aug 23 05:59:02 AM UTC 24 | Aug 23 05:59:08 AM UTC 24 | 100540730 ps | ||
T359 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2460107004 | Aug 23 05:59:09 AM UTC 24 | Aug 23 05:59:18 AM UTC 24 | 155639256 ps | ||
T360 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.938779908 | Aug 23 05:59:27 AM UTC 24 | Aug 23 05:59:31 AM UTC 24 | 86297547 ps | ||
T76 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3491164257 | Aug 23 05:59:06 AM UTC 24 | Aug 23 05:59:33 AM UTC 24 | 2426572352 ps | ||
T361 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2241306385 | Aug 23 05:59:32 AM UTC 24 | Aug 23 05:59:37 AM UTC 24 | 132571850 ps | ||
T77 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2083452475 | Aug 23 05:59:34 AM UTC 24 | Aug 23 05:59:39 AM UTC 24 | 466955913 ps | ||
T66 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.21066749 | Aug 23 05:58:34 AM UTC 24 | Aug 23 05:59:40 AM UTC 24 | 1019222561 ps | ||
T106 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3200551159 | Aug 23 05:59:33 AM UTC 24 | Aug 23 05:59:40 AM UTC 24 | 717338248 ps | ||
T362 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2460150129 | Aug 23 05:59:35 AM UTC 24 | Aug 23 05:59:40 AM UTC 24 | 260318857 ps | ||
T78 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1302036686 | Aug 23 05:59:38 AM UTC 24 | Aug 23 05:59:43 AM UTC 24 | 168164385 ps | ||
T100 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2481318410 | Aug 23 05:59:40 AM UTC 24 | Aug 23 05:59:45 AM UTC 24 | 176383452 ps | ||
T363 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.219186668 | Aug 23 05:59:41 AM UTC 24 | Aug 23 05:59:46 AM UTC 24 | 93121249 ps | ||
T364 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1025887092 | Aug 23 05:59:41 AM UTC 24 | Aug 23 05:59:49 AM UTC 24 | 334498476 ps | ||
T365 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2845104883 | Aug 23 05:59:45 AM UTC 24 | Aug 23 05:59:50 AM UTC 24 | 351091245 ps | ||
T366 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2282373601 | Aug 23 05:59:47 AM UTC 24 | Aug 23 05:59:52 AM UTC 24 | 516976106 ps | ||
T367 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1549718063 | Aug 23 05:59:50 AM UTC 24 | Aug 23 05:59:55 AM UTC 24 | 183296780 ps | ||
T368 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3417921665 | Aug 23 05:59:53 AM UTC 24 | Aug 23 05:59:58 AM UTC 24 | 168049648 ps | ||
T79 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1586955202 | Aug 23 05:59:50 AM UTC 24 | Aug 23 05:59:59 AM UTC 24 | 277494857 ps | ||
T80 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1502923752 | Aug 23 05:59:55 AM UTC 24 | Aug 23 06:00:00 AM UTC 24 | 168608111 ps | ||
T369 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1488745518 | Aug 23 05:59:41 AM UTC 24 | Aug 23 06:00:01 AM UTC 24 | 531503517 ps | ||
T81 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2901656110 | Aug 23 05:59:58 AM UTC 24 | Aug 23 06:00:03 AM UTC 24 | 200255538 ps | ||
T370 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4009185167 | Aug 23 05:59:59 AM UTC 24 | Aug 23 06:00:07 AM UTC 24 | 151425402 ps | ||
T371 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1312052192 | Aug 23 06:00:08 AM UTC 24 | Aug 23 06:00:12 AM UTC 24 | 174963404 ps | ||
T372 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2905943665 | Aug 23 06:00:02 AM UTC 24 | Aug 23 06:00:15 AM UTC 24 | 334781628 ps | ||
T373 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3289704655 | Aug 23 06:00:14 AM UTC 24 | Aug 23 06:00:19 AM UTC 24 | 251202095 ps | ||
T67 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.795648894 | Aug 23 05:59:43 AM UTC 24 | Aug 23 06:00:19 AM UTC 24 | 296025292 ps | ||
T82 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2582607628 | Aug 23 06:00:16 AM UTC 24 | Aug 23 06:00:21 AM UTC 24 | 257213810 ps | ||
T374 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.996416988 | Aug 23 06:00:15 AM UTC 24 | Aug 23 06:00:22 AM UTC 24 | 163451609 ps | ||
T92 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.918896141 | Aug 23 06:00:20 AM UTC 24 | Aug 23 06:00:25 AM UTC 24 | 1659726403 ps | ||
T87 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.803366378 | Aug 23 06:00:20 AM UTC 24 | Aug 23 06:00:25 AM UTC 24 | 563957955 ps | ||
T68 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1770673711 | Aug 23 05:59:20 AM UTC 24 | Aug 23 06:00:26 AM UTC 24 | 1102942030 ps | ||
T375 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.641051868 | Aug 23 06:00:22 AM UTC 24 | Aug 23 06:00:27 AM UTC 24 | 383982589 ps | ||
T101 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2616032400 | Aug 23 06:00:22 AM UTC 24 | Aug 23 06:00:27 AM UTC 24 | 129146894 ps | ||
T88 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.26416040 | Aug 23 06:00:01 AM UTC 24 | Aug 23 06:00:30 AM UTC 24 | 1601787681 ps | ||
T376 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.864806306 | Aug 23 06:00:28 AM UTC 24 | Aug 23 06:00:33 AM UTC 24 | 335595596 ps | ||
T377 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2580059534 | Aug 23 06:00:28 AM UTC 24 | Aug 23 06:00:34 AM UTC 24 | 496658285 ps | ||
T378 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3577220209 | Aug 23 06:00:26 AM UTC 24 | Aug 23 06:00:35 AM UTC 24 | 519596751 ps | ||
T379 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1663540336 | Aug 23 06:00:28 AM UTC 24 | Aug 23 06:00:35 AM UTC 24 | 266919682 ps | ||
T380 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3599765510 | Aug 23 06:00:30 AM UTC 24 | Aug 23 06:00:36 AM UTC 24 | 129153937 ps | ||
T381 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.462620137 | Aug 23 06:00:33 AM UTC 24 | Aug 23 06:00:38 AM UTC 24 | 1656683216 ps | ||
T382 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1753315558 | Aug 23 06:00:34 AM UTC 24 | Aug 23 06:00:40 AM UTC 24 | 129903539 ps | ||
T383 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3217890705 | Aug 23 06:00:35 AM UTC 24 | Aug 23 06:00:41 AM UTC 24 | 170489724 ps | ||
T102 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.926583004 | Aug 23 06:00:35 AM UTC 24 | Aug 23 06:00:41 AM UTC 24 | 129465256 ps | ||
T103 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1766685567 | Aug 23 06:00:25 AM UTC 24 | Aug 23 06:00:43 AM UTC 24 | 1491223329 ps | ||
T384 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1552504825 | Aug 23 06:00:40 AM UTC 24 | Aug 23 06:00:47 AM UTC 24 | 260838019 ps | ||
T385 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2166911728 | Aug 23 06:00:42 AM UTC 24 | Aug 23 06:00:48 AM UTC 24 | 132201578 ps | ||
T104 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3843459769 | Aug 23 06:00:42 AM UTC 24 | Aug 23 06:00:48 AM UTC 24 | 128611513 ps | ||
T386 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2102888216 | Aug 23 06:00:44 AM UTC 24 | Aug 23 06:00:49 AM UTC 24 | 427242262 ps | ||
T89 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1666002706 | Aug 23 06:00:50 AM UTC 24 | Aug 23 06:00:55 AM UTC 24 | 288668000 ps | ||
T95 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2100967234 | Aug 23 06:00:36 AM UTC 24 | Aug 23 06:00:57 AM UTC 24 | 2016551190 ps | ||
T387 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3987903710 | Aug 23 06:00:49 AM UTC 24 | Aug 23 06:00:58 AM UTC 24 | 574690779 ps | ||
T388 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.341104088 | Aug 23 06:00:53 AM UTC 24 | Aug 23 06:00:58 AM UTC 24 | 262915803 ps | ||
T389 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2313180571 | Aug 23 06:00:56 AM UTC 24 | Aug 23 06:01:02 AM UTC 24 | 102099832 ps | ||
T390 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3815593566 | Aug 23 06:00:48 AM UTC 24 | Aug 23 06:01:06 AM UTC 24 | 1452379035 ps | ||
T391 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3982223292 | Aug 23 06:01:02 AM UTC 24 | Aug 23 06:01:07 AM UTC 24 | 168368857 ps | ||
T392 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2087805750 | Aug 23 06:00:59 AM UTC 24 | Aug 23 06:01:08 AM UTC 24 | 659264967 ps | ||
T393 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2764514082 | Aug 23 06:01:07 AM UTC 24 | Aug 23 06:01:13 AM UTC 24 | 418653189 ps | ||
T108 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.749889209 | Aug 23 06:00:08 AM UTC 24 | Aug 23 06:01:14 AM UTC 24 | 809009467 ps | ||
T394 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3878670227 | Aug 23 06:01:07 AM UTC 24 | Aug 23 06:01:14 AM UTC 24 | 966311852 ps | ||
T395 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1866372181 | Aug 23 06:00:57 AM UTC 24 | Aug 23 06:01:15 AM UTC 24 | 363488887 ps | ||
T109 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.820918919 | Aug 23 06:00:41 AM UTC 24 | Aug 23 06:01:17 AM UTC 24 | 848464029 ps | ||
T396 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.421213914 | Aug 23 06:01:09 AM UTC 24 | Aug 23 06:01:19 AM UTC 24 | 167733575 ps | ||
T90 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.662099033 | Aug 23 06:01:14 AM UTC 24 | Aug 23 06:01:20 AM UTC 24 | 133911820 ps | ||
T397 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3513529153 | Aug 23 06:01:16 AM UTC 24 | Aug 23 06:01:20 AM UTC 24 | 85600110 ps | ||
T398 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1875071467 | Aug 23 06:01:16 AM UTC 24 | Aug 23 06:01:21 AM UTC 24 | 132687224 ps | ||
T399 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.857424732 | Aug 23 06:01:21 AM UTC 24 | Aug 23 06:01:26 AM UTC 24 | 775071808 ps | ||
T400 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2933424717 | Aug 23 06:01:22 AM UTC 24 | Aug 23 06:01:27 AM UTC 24 | 168531630 ps | ||
T401 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3429024659 | Aug 23 06:01:20 AM UTC 24 | Aug 23 06:01:28 AM UTC 24 | 126408497 ps | ||
T113 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3788431310 | Aug 23 06:00:49 AM UTC 24 | Aug 23 06:01:28 AM UTC 24 | 1465500376 ps | ||
T402 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1237227167 | Aug 23 06:01:08 AM UTC 24 | Aug 23 06:01:29 AM UTC 24 | 1036057630 ps | ||
T114 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1616801030 | Aug 23 06:00:27 AM UTC 24 | Aug 23 06:01:32 AM UTC 24 | 861230607 ps | ||
T403 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.238520786 | Aug 23 06:01:27 AM UTC 24 | Aug 23 06:01:34 AM UTC 24 | 527628622 ps | ||
T93 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2008740408 | Aug 23 06:01:30 AM UTC 24 | Aug 23 06:01:35 AM UTC 24 | 86596700 ps | ||
T96 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1578977266 | Aug 23 06:01:18 AM UTC 24 | Aug 23 06:01:36 AM UTC 24 | 1494165750 ps | ||
T404 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2777926813 | Aug 23 06:01:32 AM UTC 24 | Aug 23 06:01:38 AM UTC 24 | 519253480 ps | ||
T405 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1660784069 | Aug 23 06:01:29 AM UTC 24 | Aug 23 06:01:38 AM UTC 24 | 152452985 ps | ||
T406 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.202425579 | Aug 23 06:01:34 AM UTC 24 | Aug 23 06:01:39 AM UTC 24 | 201017484 ps | ||
T407 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3261078930 | Aug 23 06:01:36 AM UTC 24 | Aug 23 06:01:44 AM UTC 24 | 738208332 ps | ||
T408 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.161143895 | Aug 23 06:01:39 AM UTC 24 | Aug 23 06:01:44 AM UTC 24 | 171867907 ps | ||
T409 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2299283260 | Aug 23 06:01:40 AM UTC 24 | Aug 23 06:01:45 AM UTC 24 | 88011401 ps | ||
T410 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.824677441 | Aug 23 06:01:27 AM UTC 24 | Aug 23 06:01:48 AM UTC 24 | 553269400 ps | ||
T411 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2474702998 | Aug 23 06:01:44 AM UTC 24 | Aug 23 06:01:50 AM UTC 24 | 376944529 ps | ||
T412 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3880785993 | Aug 23 06:01:45 AM UTC 24 | Aug 23 06:01:54 AM UTC 24 | 132395493 ps | ||
T413 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3365624146 | Aug 23 06:01:50 AM UTC 24 | Aug 23 06:01:56 AM UTC 24 | 499513160 ps | ||
T94 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1102377557 | Aug 23 06:01:35 AM UTC 24 | Aug 23 06:01:56 AM UTC 24 | 2185002667 ps | ||
T118 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3823126325 | Aug 23 06:01:21 AM UTC 24 | Aug 23 06:01:56 AM UTC 24 | 206094998 ps | ||
T414 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1201507907 | Aug 23 06:01:55 AM UTC 24 | Aug 23 06:02:00 AM UTC 24 | 135093035 ps | ||
T415 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3040609352 | Aug 23 06:01:55 AM UTC 24 | Aug 23 06:02:01 AM UTC 24 | 373174270 ps | ||
T97 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1536810329 | Aug 23 06:01:44 AM UTC 24 | Aug 23 06:02:02 AM UTC 24 | 363407584 ps | ||
T416 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1694588773 | Aug 23 06:02:01 AM UTC 24 | Aug 23 06:02:06 AM UTC 24 | 132871784 ps | ||
T117 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2581255167 | Aug 23 06:01:29 AM UTC 24 | Aug 23 06:02:06 AM UTC 24 | 994377055 ps | ||
T417 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3528478347 | Aug 23 06:01:57 AM UTC 24 | Aug 23 06:02:07 AM UTC 24 | 1358472329 ps | ||
T110 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2143147469 | Aug 23 06:00:59 AM UTC 24 | Aug 23 06:02:07 AM UTC 24 | 427585029 ps | ||
T418 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4039282367 | Aug 23 06:02:02 AM UTC 24 | Aug 23 06:02:08 AM UTC 24 | 363328862 ps | ||
T419 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.447786995 | Aug 23 06:02:03 AM UTC 24 | Aug 23 06:02:09 AM UTC 24 | 121457023 ps | ||
T91 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1812535439 | Aug 23 06:02:08 AM UTC 24 | Aug 23 06:02:13 AM UTC 24 | 85413283 ps | ||
T420 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.993301147 | Aug 23 06:02:08 AM UTC 24 | Aug 23 06:02:13 AM UTC 24 | 396457746 ps | ||
T421 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1412294121 | Aug 23 06:01:38 AM UTC 24 | Aug 23 06:02:14 AM UTC 24 | 730579361 ps | ||
T422 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3670875716 | Aug 23 06:02:09 AM UTC 24 | Aug 23 06:02:15 AM UTC 24 | 184867832 ps | ||
T423 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1998074819 | Aug 23 06:02:14 AM UTC 24 | Aug 23 06:02:19 AM UTC 24 | 168028426 ps | ||
T424 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3274026662 | Aug 23 06:02:15 AM UTC 24 | Aug 23 06:02:21 AM UTC 24 | 132198803 ps | ||
T425 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1536729769 | Aug 23 06:02:15 AM UTC 24 | Aug 23 06:02:21 AM UTC 24 | 137731922 ps | ||
T426 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1326512899 | Aug 23 06:02:13 AM UTC 24 | Aug 23 06:02:22 AM UTC 24 | 586578275 ps | ||
T111 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4225527949 | Aug 23 06:01:13 AM UTC 24 | Aug 23 06:02:22 AM UTC 24 | 279315619 ps | ||
T427 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2490567758 | Aug 23 06:01:57 AM UTC 24 | Aug 23 06:02:23 AM UTC 24 | 570034306 ps | ||
T428 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.137240092 | Aug 23 06:02:23 AM UTC 24 | Aug 23 06:02:27 AM UTC 24 | 350980325 ps | ||
T429 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2122607542 | Aug 23 06:02:23 AM UTC 24 | Aug 23 06:02:28 AM UTC 24 | 261208823 ps | ||
T430 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2948850999 | Aug 23 06:02:23 AM UTC 24 | Aug 23 06:02:28 AM UTC 24 | 132203214 ps | ||
T431 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4079417041 | Aug 23 06:02:21 AM UTC 24 | Aug 23 06:02:29 AM UTC 24 | 132330256 ps | ||
T432 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.620700916 | Aug 23 06:02:09 AM UTC 24 | Aug 23 06:02:30 AM UTC 24 | 526773437 ps | ||
T433 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1590465401 | Aug 23 06:02:07 AM UTC 24 | Aug 23 06:02:33 AM UTC 24 | 1095464666 ps | ||
T434 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4074010077 | Aug 23 06:02:29 AM UTC 24 | Aug 23 06:02:34 AM UTC 24 | 86531822 ps | ||
T435 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.527256492 | Aug 23 06:02:30 AM UTC 24 | Aug 23 06:02:35 AM UTC 24 | 517001218 ps | ||
T436 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.326127317 | Aug 23 06:02:28 AM UTC 24 | Aug 23 06:02:35 AM UTC 24 | 131682955 ps | ||
T437 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4231066961 | Aug 23 06:02:31 AM UTC 24 | Aug 23 06:02:37 AM UTC 24 | 262071803 ps | ||
T438 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3408659168 | Aug 23 06:02:24 AM UTC 24 | Aug 23 06:02:42 AM UTC 24 | 356962990 ps | ||
T439 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.530940415 | Aug 23 06:02:34 AM UTC 24 | Aug 23 06:02:42 AM UTC 24 | 519118542 ps | ||
T440 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.792182334 | Aug 23 06:02:36 AM UTC 24 | Aug 23 06:02:42 AM UTC 24 | 460415296 ps | ||
T441 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3441648127 | Aug 23 06:02:36 AM UTC 24 | Aug 23 06:02:42 AM UTC 24 | 501777812 ps | ||
T116 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.587665290 | Aug 23 06:02:07 AM UTC 24 | Aug 23 06:02:43 AM UTC 24 | 216523989 ps | ||
T442 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3040778225 | Aug 23 06:02:38 AM UTC 24 | Aug 23 06:02:44 AM UTC 24 | 143356414 ps | ||
T443 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.225615138 | Aug 23 06:02:19 AM UTC 24 | Aug 23 06:02:45 AM UTC 24 | 2052764777 ps | ||
T444 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2403480970 | Aug 23 06:02:42 AM UTC 24 | Aug 23 06:02:48 AM UTC 24 | 498903519 ps | ||
T445 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.835097835 | Aug 23 06:02:13 AM UTC 24 | Aug 23 06:02:49 AM UTC 24 | 372674894 ps | ||
T446 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1556128544 | Aug 23 06:02:43 AM UTC 24 | Aug 23 06:02:49 AM UTC 24 | 130919156 ps | ||
T447 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1637236539 | Aug 23 06:02:42 AM UTC 24 | Aug 23 06:02:51 AM UTC 24 | 499095523 ps | ||
T448 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3467494775 | Aug 23 06:02:45 AM UTC 24 | Aug 23 06:02:51 AM UTC 24 | 148681885 ps | ||
T112 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.718763964 | Aug 23 06:01:48 AM UTC 24 | Aug 23 06:02:55 AM UTC 24 | 980575745 ps | ||
T449 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3176846225 | Aug 23 06:02:22 AM UTC 24 | Aug 23 06:02:59 AM UTC 24 | 189843519 ps | ||
T450 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2978325043 | Aug 23 06:02:42 AM UTC 24 | Aug 23 06:03:01 AM UTC 24 | 381160207 ps | ||
T115 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1690978416 | Aug 23 06:01:58 AM UTC 24 | Aug 23 06:03:04 AM UTC 24 | 284322009 ps | ||
T451 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1031878232 | Aug 23 06:02:35 AM UTC 24 | Aug 23 06:03:12 AM UTC 24 | 455907974 ps | ||
T452 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.733434736 | Aug 23 06:02:34 AM UTC 24 | Aug 23 06:03:13 AM UTC 24 | 12480479300 ps | ||
T453 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.140568222 | Aug 23 06:02:42 AM UTC 24 | Aug 23 06:03:19 AM UTC 24 | 468901664 ps | ||
T454 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2219520545 | Aug 23 06:02:29 AM UTC 24 | Aug 23 06:03:35 AM UTC 24 | 631296616 ps |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3486436971 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1021832131 ps |
CPU time | 8.34 seconds |
Started | Aug 23 06:05:55 AM UTC 24 |
Finished | Aug 23 06:06:04 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486436971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3486436971 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1643035083 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 5240793084 ps |
CPU time | 45.44 seconds |
Started | Aug 23 06:05:55 AM UTC 24 |
Finished | Aug 23 06:06:42 AM UTC 24 |
Peak memory | 230836 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1643035083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1643035083 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1493994095 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 7525648285 ps |
CPU time | 87.43 seconds |
Started | Aug 23 06:06:03 AM UTC 24 |
Finished | Aug 23 06:07:32 AM UTC 24 |
Peak memory | 223616 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493994095 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.1493994095 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3899267724 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 461455043 ps |
CPU time | 15.19 seconds |
Started | Aug 23 06:05:57 AM UTC 24 |
Finished | Aug 23 06:06:14 AM UTC 24 |
Peak memory | 225452 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389926772 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.3899267724 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.21066749 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1019222561 ps |
CPU time | 64.17 seconds |
Started | Aug 23 05:58:34 AM UTC 24 |
Finished | Aug 23 05:59:40 AM UTC 24 |
Peak memory | 223868 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21066749 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.21066749 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1162025002 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 6829053431 ps |
CPU time | 101.47 seconds |
Started | Aug 23 06:06:26 AM UTC 24 |
Finished | Aug 23 06:08:09 AM UTC 24 |
Peak memory | 253376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162025002 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.1162025002 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1071977672 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 1037944649 ps |
CPU time | 9.86 seconds |
Started | Aug 23 06:05:57 AM UTC 24 |
Finished | Aug 23 06:06:09 AM UTC 24 |
Peak memory | 221356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071977672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1071977672 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2842889937 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 137920573 ps |
CPU time | 48.87 seconds |
Started | Aug 23 06:06:04 AM UTC 24 |
Finished | Aug 23 06:06:54 AM UTC 24 |
Peak memory | 257584 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842889937 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2842889937 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3491164257 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 2426572352 ps |
CPU time | 25.09 seconds |
Started | Aug 23 05:59:06 AM UTC 24 |
Finished | Aug 23 05:59:33 AM UTC 24 |
Peak memory | 221984 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491164257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.3491164257 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.355584403 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 779973128 ps |
CPU time | 12.97 seconds |
Started | Aug 23 06:06:02 AM UTC 24 |
Finished | Aug 23 06:06:16 AM UTC 24 |
Peak memory | 223468 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355584403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.355584403 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2143147469 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 427585029 ps |
CPU time | 66.85 seconds |
Started | Aug 23 06:00:59 AM UTC 24 |
Finished | Aug 23 06:02:07 AM UTC 24 |
Peak memory | 229256 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143147469 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.2143147469 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1043144202 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1970739223 ps |
CPU time | 13.32 seconds |
Started | Aug 23 06:06:03 AM UTC 24 |
Finished | Aug 23 06:06:17 AM UTC 24 |
Peak memory | 221548 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043144202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1043144202 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1937060142 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1036146407 ps |
CPU time | 10.24 seconds |
Started | Aug 23 06:06:55 AM UTC 24 |
Finished | Aug 23 06:07:06 AM UTC 24 |
Peak memory | 221356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937060142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1937060142 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3211316517 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 1185020274 ps |
CPU time | 3.79 seconds |
Started | Aug 23 06:05:56 AM UTC 24 |
Finished | Aug 23 06:06:01 AM UTC 24 |
Peak memory | 221384 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211316517 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3211316517 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.26416040 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 1601787681 ps |
CPU time | 28.29 seconds |
Started | Aug 23 06:00:01 AM UTC 24 |
Finished | Aug 23 06:00:30 AM UTC 24 |
Peak memory | 222040 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26416040 -assert nopostproc +U VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.26416040 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3467905036 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1947741849 ps |
CPU time | 61.68 seconds |
Started | Aug 23 06:06:28 AM UTC 24 |
Finished | Aug 23 06:07:31 AM UTC 24 |
Peak memory | 231052 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3467905036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3467905036 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1770673711 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1102942030 ps |
CPU time | 64.74 seconds |
Started | Aug 23 05:59:20 AM UTC 24 |
Finished | Aug 23 06:00:26 AM UTC 24 |
Peak memory | 223996 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770673711 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.1770673711 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2808581746 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 596900638 ps |
CPU time | 8.69 seconds |
Started | Aug 23 06:05:55 AM UTC 24 |
Finished | Aug 23 06:06:05 AM UTC 24 |
Peak memory | 221356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808581746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2808581746 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2497123991 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 16828500055 ps |
CPU time | 238.81 seconds |
Started | Aug 23 06:05:57 AM UTC 24 |
Finished | Aug 23 06:10:00 AM UTC 24 |
Peak memory | 248304 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2497123991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2497123991 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2878106327 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1251730901 ps |
CPU time | 15.9 seconds |
Started | Aug 23 06:05:55 AM UTC 24 |
Finished | Aug 23 06:06:12 AM UTC 24 |
Peak memory | 225452 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287810632 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.2878106327 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2754269737 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1131969765 ps |
CPU time | 4.42 seconds |
Started | Aug 23 05:58:56 AM UTC 24 |
Finished | Aug 23 05:59:02 AM UTC 24 |
Peak memory | 221756 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754269737 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.2754269737 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3224096884 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 245860175 ps |
CPU time | 4.51 seconds |
Started | Aug 23 05:58:54 AM UTC 24 |
Finished | Aug 23 05:59:00 AM UTC 24 |
Peak memory | 227964 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224096884 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.3224096884 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1939800155 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 94562958 ps |
CPU time | 5.43 seconds |
Started | Aug 23 05:58:47 AM UTC 24 |
Finished | Aug 23 05:58:54 AM UTC 24 |
Peak memory | 221820 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939800155 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.1939800155 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2254866626 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 100540730 ps |
CPU time | 4.28 seconds |
Started | Aug 23 05:59:02 AM UTC 24 |
Finished | Aug 23 05:59:08 AM UTC 24 |
Peak memory | 229308 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2254866626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r om_ctrl_csr_mem_rw_with_rand_reset.2254866626 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3596080244 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 92088977 ps |
CPU time | 3.86 seconds |
Started | Aug 23 05:58:51 AM UTC 24 |
Finished | Aug 23 05:58:56 AM UTC 24 |
Peak memory | 221744 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596080244 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3596080244 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1690920501 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 366592590 ps |
CPU time | 3.62 seconds |
Started | Aug 23 05:58:42 AM UTC 24 |
Finished | Aug 23 05:58:47 AM UTC 24 |
Peak memory | 221548 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690920501 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.1690920501 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.901124824 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 369476142 ps |
CPU time | 4.22 seconds |
Started | Aug 23 05:58:36 AM UTC 24 |
Finished | Aug 23 05:58:41 AM UTC 24 |
Peak memory | 221688 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901124824 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.901124824 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3811217192 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 3623646526 ps |
CPU time | 17.26 seconds |
Started | Aug 23 05:58:15 AM UTC 24 |
Finished | Aug 23 05:58:33 AM UTC 24 |
Peak memory | 222112 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811217192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.3811217192 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1133474205 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 132584804 ps |
CPU time | 4.53 seconds |
Started | Aug 23 05:59:00 AM UTC 24 |
Finished | Aug 23 05:59:06 AM UTC 24 |
Peak memory | 222000 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133474205 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.1133474205 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.102404934 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 333727392 ps |
CPU time | 6.92 seconds |
Started | Aug 23 05:58:27 AM UTC 24 |
Finished | Aug 23 05:58:35 AM UTC 24 |
Peak memory | 229276 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102404934 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.102404934 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1302036686 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 168164385 ps |
CPU time | 3.86 seconds |
Started | Aug 23 05:59:38 AM UTC 24 |
Finished | Aug 23 05:59:43 AM UTC 24 |
Peak memory | 229148 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302036686 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.1302036686 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2460150129 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 260318857 ps |
CPU time | 4.58 seconds |
Started | Aug 23 05:59:35 AM UTC 24 |
Finished | Aug 23 05:59:40 AM UTC 24 |
Peak memory | 227964 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460150129 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.2460150129 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3200551159 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 717338248 ps |
CPU time | 6.53 seconds |
Started | Aug 23 05:59:33 AM UTC 24 |
Finished | Aug 23 05:59:40 AM UTC 24 |
Peak memory | 221748 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200551159 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.3200551159 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.219186668 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 93121249 ps |
CPU time | 4.05 seconds |
Started | Aug 23 05:59:41 AM UTC 24 |
Finished | Aug 23 05:59:46 AM UTC 24 |
Peak memory | 229136 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=219186668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ro m_ctrl_csr_mem_rw_with_rand_reset.219186668 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2083452475 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 466955913 ps |
CPU time | 4.33 seconds |
Started | Aug 23 05:59:34 AM UTC 24 |
Finished | Aug 23 05:59:39 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083452475 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2083452475 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2241306385 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 132571850 ps |
CPU time | 4.46 seconds |
Started | Aug 23 05:59:32 AM UTC 24 |
Finished | Aug 23 05:59:37 AM UTC 24 |
Peak memory | 221620 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241306385 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.2241306385 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.938779908 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 86297547 ps |
CPU time | 3.66 seconds |
Started | Aug 23 05:59:27 AM UTC 24 |
Finished | Aug 23 05:59:31 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938779908 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.938779908 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2481318410 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 176383452 ps |
CPU time | 3.73 seconds |
Started | Aug 23 05:59:40 AM UTC 24 |
Finished | Aug 23 05:59:45 AM UTC 24 |
Peak memory | 221936 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481318410 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.2481318410 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2460107004 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 155639256 ps |
CPU time | 8.63 seconds |
Started | Aug 23 05:59:09 AM UTC 24 |
Finished | Aug 23 05:59:18 AM UTC 24 |
Peak memory | 226076 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460107004 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2460107004 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.202425579 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 201017484 ps |
CPU time | 4.35 seconds |
Started | Aug 23 06:01:34 AM UTC 24 |
Finished | Aug 23 06:01:39 AM UTC 24 |
Peak memory | 229144 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=202425579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.r om_ctrl_csr_mem_rw_with_rand_reset.202425579 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2008740408 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 86596700 ps |
CPU time | 3.68 seconds |
Started | Aug 23 06:01:30 AM UTC 24 |
Finished | Aug 23 06:01:35 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008740408 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2008740408 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.824677441 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 553269400 ps |
CPU time | 19.81 seconds |
Started | Aug 23 06:01:27 AM UTC 24 |
Finished | Aug 23 06:01:48 AM UTC 24 |
Peak memory | 221844 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824677441 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.824677441 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2777926813 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 519253480 ps |
CPU time | 4.37 seconds |
Started | Aug 23 06:01:32 AM UTC 24 |
Finished | Aug 23 06:01:38 AM UTC 24 |
Peak memory | 221812 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777926813 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.2777926813 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1660784069 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 152452985 ps |
CPU time | 8.39 seconds |
Started | Aug 23 06:01:29 AM UTC 24 |
Finished | Aug 23 06:01:38 AM UTC 24 |
Peak memory | 229400 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660784069 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1660784069 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2581255167 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 994377055 ps |
CPU time | 35.79 seconds |
Started | Aug 23 06:01:29 AM UTC 24 |
Finished | Aug 23 06:02:06 AM UTC 24 |
Peak memory | 229248 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581255167 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.2581255167 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2474702998 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 376944529 ps |
CPU time | 4.87 seconds |
Started | Aug 23 06:01:44 AM UTC 24 |
Finished | Aug 23 06:01:50 AM UTC 24 |
Peak memory | 228152 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2474702998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rom_ctrl_csr_mem_rw_with_rand_reset.2474702998 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.161143895 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 171867907 ps |
CPU time | 3.76 seconds |
Started | Aug 23 06:01:39 AM UTC 24 |
Finished | Aug 23 06:01:44 AM UTC 24 |
Peak memory | 221756 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161143895 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.161143895 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1102377557 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 2185002667 ps |
CPU time | 19.81 seconds |
Started | Aug 23 06:01:35 AM UTC 24 |
Finished | Aug 23 06:01:56 AM UTC 24 |
Peak memory | 222036 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102377557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.1102377557 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2299283260 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 88011401 ps |
CPU time | 3.74 seconds |
Started | Aug 23 06:01:40 AM UTC 24 |
Finished | Aug 23 06:01:45 AM UTC 24 |
Peak memory | 221812 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299283260 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.2299283260 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3261078930 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 738208332 ps |
CPU time | 6.62 seconds |
Started | Aug 23 06:01:36 AM UTC 24 |
Finished | Aug 23 06:01:44 AM UTC 24 |
Peak memory | 229404 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261078930 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3261078930 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1412294121 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 730579361 ps |
CPU time | 34.26 seconds |
Started | Aug 23 06:01:38 AM UTC 24 |
Finished | Aug 23 06:02:14 AM UTC 24 |
Peak memory | 224000 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412294121 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1412294121 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1201507907 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 135093035 ps |
CPU time | 4.63 seconds |
Started | Aug 23 06:01:55 AM UTC 24 |
Finished | Aug 23 06:02:00 AM UTC 24 |
Peak memory | 229304 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1201507907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rom_ctrl_csr_mem_rw_with_rand_reset.1201507907 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3365624146 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 499513160 ps |
CPU time | 4.38 seconds |
Started | Aug 23 06:01:50 AM UTC 24 |
Finished | Aug 23 06:01:56 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365624146 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3365624146 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1536810329 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 363407584 ps |
CPU time | 16.71 seconds |
Started | Aug 23 06:01:44 AM UTC 24 |
Finished | Aug 23 06:02:02 AM UTC 24 |
Peak memory | 221972 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536810329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1536810329 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3040609352 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 373174270 ps |
CPU time | 5.43 seconds |
Started | Aug 23 06:01:55 AM UTC 24 |
Finished | Aug 23 06:02:01 AM UTC 24 |
Peak memory | 229364 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040609352 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.3040609352 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3880785993 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 132395493 ps |
CPU time | 7.73 seconds |
Started | Aug 23 06:01:45 AM UTC 24 |
Finished | Aug 23 06:01:54 AM UTC 24 |
Peak memory | 228124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880785993 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3880785993 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.718763964 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 980575745 ps |
CPU time | 64.86 seconds |
Started | Aug 23 06:01:48 AM UTC 24 |
Finished | Aug 23 06:02:55 AM UTC 24 |
Peak memory | 223792 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718763964 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.718763964 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.447786995 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 121457023 ps |
CPU time | 4.77 seconds |
Started | Aug 23 06:02:03 AM UTC 24 |
Finished | Aug 23 06:02:09 AM UTC 24 |
Peak memory | 228024 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=447786995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.r om_ctrl_csr_mem_rw_with_rand_reset.447786995 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1694588773 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 132871784 ps |
CPU time | 4.32 seconds |
Started | Aug 23 06:02:01 AM UTC 24 |
Finished | Aug 23 06:02:06 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694588773 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1694588773 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2490567758 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 570034306 ps |
CPU time | 25.3 seconds |
Started | Aug 23 06:01:57 AM UTC 24 |
Finished | Aug 23 06:02:23 AM UTC 24 |
Peak memory | 221844 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490567758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.2490567758 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4039282367 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 363328862 ps |
CPU time | 5.4 seconds |
Started | Aug 23 06:02:02 AM UTC 24 |
Finished | Aug 23 06:02:08 AM UTC 24 |
Peak memory | 229136 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039282367 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.4039282367 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3528478347 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 1358472329 ps |
CPU time | 9.01 seconds |
Started | Aug 23 06:01:57 AM UTC 24 |
Finished | Aug 23 06:02:07 AM UTC 24 |
Peak memory | 229272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528478347 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3528478347 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1690978416 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 284322009 ps |
CPU time | 64.49 seconds |
Started | Aug 23 06:01:58 AM UTC 24 |
Finished | Aug 23 06:03:04 AM UTC 24 |
Peak memory | 223936 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690978416 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.1690978416 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3670875716 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 184867832 ps |
CPU time | 4.57 seconds |
Started | Aug 23 06:02:09 AM UTC 24 |
Finished | Aug 23 06:02:15 AM UTC 24 |
Peak memory | 229276 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3670875716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rom_ctrl_csr_mem_rw_with_rand_reset.3670875716 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1812535439 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 85413283 ps |
CPU time | 3.71 seconds |
Started | Aug 23 06:02:08 AM UTC 24 |
Finished | Aug 23 06:02:13 AM UTC 24 |
Peak memory | 221752 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812535439 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1812535439 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1590465401 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 1095464666 ps |
CPU time | 25.27 seconds |
Started | Aug 23 06:02:07 AM UTC 24 |
Finished | Aug 23 06:02:33 AM UTC 24 |
Peak memory | 221412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590465401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.1590465401 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.993301147 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 396457746 ps |
CPU time | 3.69 seconds |
Started | Aug 23 06:02:08 AM UTC 24 |
Finished | Aug 23 06:02:13 AM UTC 24 |
Peak memory | 221824 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993301147 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.993301147 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.587665290 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 216523989 ps |
CPU time | 34.59 seconds |
Started | Aug 23 06:02:07 AM UTC 24 |
Finished | Aug 23 06:02:43 AM UTC 24 |
Peak memory | 221748 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587665290 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.587665290 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1536729769 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 137731922 ps |
CPU time | 5 seconds |
Started | Aug 23 06:02:15 AM UTC 24 |
Finished | Aug 23 06:02:21 AM UTC 24 |
Peak memory | 229096 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1536729769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rom_ctrl_csr_mem_rw_with_rand_reset.1536729769 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1998074819 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 168028426 ps |
CPU time | 3.81 seconds |
Started | Aug 23 06:02:14 AM UTC 24 |
Finished | Aug 23 06:02:19 AM UTC 24 |
Peak memory | 221744 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998074819 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1998074819 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.620700916 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 526773437 ps |
CPU time | 19.7 seconds |
Started | Aug 23 06:02:09 AM UTC 24 |
Finished | Aug 23 06:02:30 AM UTC 24 |
Peak memory | 221844 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620700916 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.620700916 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3274026662 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 132198803 ps |
CPU time | 4.5 seconds |
Started | Aug 23 06:02:15 AM UTC 24 |
Finished | Aug 23 06:02:21 AM UTC 24 |
Peak memory | 228092 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274026662 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.3274026662 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1326512899 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 586578275 ps |
CPU time | 7.63 seconds |
Started | Aug 23 06:02:13 AM UTC 24 |
Finished | Aug 23 06:02:22 AM UTC 24 |
Peak memory | 225524 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326512899 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1326512899 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.835097835 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 372674894 ps |
CPU time | 34.11 seconds |
Started | Aug 23 06:02:13 AM UTC 24 |
Finished | Aug 23 06:02:49 AM UTC 24 |
Peak memory | 223364 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835097835 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.835097835 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2122607542 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 261208823 ps |
CPU time | 4.33 seconds |
Started | Aug 23 06:02:23 AM UTC 24 |
Finished | Aug 23 06:02:28 AM UTC 24 |
Peak memory | 229276 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2122607542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rom_ctrl_csr_mem_rw_with_rand_reset.2122607542 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2948850999 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 132203214 ps |
CPU time | 4.41 seconds |
Started | Aug 23 06:02:23 AM UTC 24 |
Finished | Aug 23 06:02:28 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948850999 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2948850999 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.225615138 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 2052764777 ps |
CPU time | 24.53 seconds |
Started | Aug 23 06:02:19 AM UTC 24 |
Finished | Aug 23 06:02:45 AM UTC 24 |
Peak memory | 221844 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225615138 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.225615138 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.137240092 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 350980325 ps |
CPU time | 3.78 seconds |
Started | Aug 23 06:02:23 AM UTC 24 |
Finished | Aug 23 06:02:27 AM UTC 24 |
Peak memory | 221828 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137240092 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.137240092 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4079417041 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 132330256 ps |
CPU time | 6.9 seconds |
Started | Aug 23 06:02:21 AM UTC 24 |
Finished | Aug 23 06:02:29 AM UTC 24 |
Peak memory | 225876 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079417041 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4079417041 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3176846225 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 189843519 ps |
CPU time | 34.83 seconds |
Started | Aug 23 06:02:22 AM UTC 24 |
Finished | Aug 23 06:02:59 AM UTC 24 |
Peak memory | 221824 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176846225 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.3176846225 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4231066961 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 262071803 ps |
CPU time | 4.57 seconds |
Started | Aug 23 06:02:31 AM UTC 24 |
Finished | Aug 23 06:02:37 AM UTC 24 |
Peak memory | 229212 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4231066961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rom_ctrl_csr_mem_rw_with_rand_reset.4231066961 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4074010077 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 86531822 ps |
CPU time | 3.79 seconds |
Started | Aug 23 06:02:29 AM UTC 24 |
Finished | Aug 23 06:02:34 AM UTC 24 |
Peak memory | 221744 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074010077 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4074010077 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3408659168 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 356962990 ps |
CPU time | 16.86 seconds |
Started | Aug 23 06:02:24 AM UTC 24 |
Finished | Aug 23 06:02:42 AM UTC 24 |
Peak memory | 221844 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408659168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.3408659168 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.527256492 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 517001218 ps |
CPU time | 4.36 seconds |
Started | Aug 23 06:02:30 AM UTC 24 |
Finished | Aug 23 06:02:35 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527256492 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.527256492 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.326127317 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 131682955 ps |
CPU time | 6.47 seconds |
Started | Aug 23 06:02:28 AM UTC 24 |
Finished | Aug 23 06:02:35 AM UTC 24 |
Peak memory | 226076 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326127317 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.326127317 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2219520545 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 631296616 ps |
CPU time | 65.13 seconds |
Started | Aug 23 06:02:29 AM UTC 24 |
Finished | Aug 23 06:03:35 AM UTC 24 |
Peak memory | 229348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219520545 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.2219520545 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3040778225 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 143356414 ps |
CPU time | 5.32 seconds |
Started | Aug 23 06:02:38 AM UTC 24 |
Finished | Aug 23 06:02:44 AM UTC 24 |
Peak memory | 229364 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3040778225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rom_ctrl_csr_mem_rw_with_rand_reset.3040778225 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.792182334 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 460415296 ps |
CPU time | 4.43 seconds |
Started | Aug 23 06:02:36 AM UTC 24 |
Finished | Aug 23 06:02:42 AM UTC 24 |
Peak memory | 221948 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792182334 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.792182334 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.733434736 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 12480479300 ps |
CPU time | 37.29 seconds |
Started | Aug 23 06:02:34 AM UTC 24 |
Finished | Aug 23 06:03:13 AM UTC 24 |
Peak memory | 224020 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733434736 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.733434736 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3441648127 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 501777812 ps |
CPU time | 4.52 seconds |
Started | Aug 23 06:02:36 AM UTC 24 |
Finished | Aug 23 06:02:42 AM UTC 24 |
Peak memory | 221812 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441648127 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.3441648127 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.530940415 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 519118542 ps |
CPU time | 6.39 seconds |
Started | Aug 23 06:02:34 AM UTC 24 |
Finished | Aug 23 06:02:42 AM UTC 24 |
Peak memory | 226076 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530940415 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.530940415 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1031878232 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 455907974 ps |
CPU time | 36.08 seconds |
Started | Aug 23 06:02:35 AM UTC 24 |
Finished | Aug 23 06:03:12 AM UTC 24 |
Peak memory | 229376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031878232 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.1031878232 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3467494775 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 148681885 ps |
CPU time | 4.75 seconds |
Started | Aug 23 06:02:45 AM UTC 24 |
Finished | Aug 23 06:02:51 AM UTC 24 |
Peak memory | 225976 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3467494775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rom_ctrl_csr_mem_rw_with_rand_reset.3467494775 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2403480970 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 498903519 ps |
CPU time | 4.38 seconds |
Started | Aug 23 06:02:42 AM UTC 24 |
Finished | Aug 23 06:02:48 AM UTC 24 |
Peak memory | 228068 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403480970 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2403480970 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2978325043 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 381160207 ps |
CPU time | 17.26 seconds |
Started | Aug 23 06:02:42 AM UTC 24 |
Finished | Aug 23 06:03:01 AM UTC 24 |
Peak memory | 221556 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978325043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.2978325043 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1556128544 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 130919156 ps |
CPU time | 4.42 seconds |
Started | Aug 23 06:02:43 AM UTC 24 |
Finished | Aug 23 06:02:49 AM UTC 24 |
Peak memory | 228592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556128544 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.1556128544 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1637236539 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 499095523 ps |
CPU time | 8 seconds |
Started | Aug 23 06:02:42 AM UTC 24 |
Finished | Aug 23 06:02:51 AM UTC 24 |
Peak memory | 227924 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637236539 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1637236539 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.140568222 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 468901664 ps |
CPU time | 35.36 seconds |
Started | Aug 23 06:02:42 AM UTC 24 |
Finished | Aug 23 06:03:19 AM UTC 24 |
Peak memory | 221812 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140568222 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.140568222 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1502923752 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 168608111 ps |
CPU time | 3.84 seconds |
Started | Aug 23 05:59:55 AM UTC 24 |
Finished | Aug 23 06:00:00 AM UTC 24 |
Peak memory | 228160 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502923752 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.1502923752 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3417921665 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 168049648 ps |
CPU time | 3.79 seconds |
Started | Aug 23 05:59:53 AM UTC 24 |
Finished | Aug 23 05:59:58 AM UTC 24 |
Peak memory | 227892 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417921665 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.3417921665 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1586955202 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 277494857 ps |
CPU time | 7.27 seconds |
Started | Aug 23 05:59:50 AM UTC 24 |
Finished | Aug 23 05:59:59 AM UTC 24 |
Peak memory | 221884 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586955202 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.1586955202 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4009185167 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 151425402 ps |
CPU time | 6.08 seconds |
Started | Aug 23 05:59:59 AM UTC 24 |
Finished | Aug 23 06:00:07 AM UTC 24 |
Peak memory | 229208 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4009185167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r om_ctrl_csr_mem_rw_with_rand_reset.4009185167 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1549718063 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 183296780 ps |
CPU time | 3.79 seconds |
Started | Aug 23 05:59:50 AM UTC 24 |
Finished | Aug 23 05:59:55 AM UTC 24 |
Peak memory | 229148 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549718063 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1549718063 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2282373601 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 516976106 ps |
CPU time | 4.21 seconds |
Started | Aug 23 05:59:47 AM UTC 24 |
Finished | Aug 23 05:59:52 AM UTC 24 |
Peak memory | 221620 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282373601 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.2282373601 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2845104883 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 351091245 ps |
CPU time | 3.66 seconds |
Started | Aug 23 05:59:45 AM UTC 24 |
Finished | Aug 23 05:59:50 AM UTC 24 |
Peak memory | 221816 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845104883 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.2845104883 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1488745518 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 531503517 ps |
CPU time | 19.15 seconds |
Started | Aug 23 05:59:41 AM UTC 24 |
Finished | Aug 23 06:00:01 AM UTC 24 |
Peak memory | 221788 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488745518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.1488745518 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2901656110 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 200255538 ps |
CPU time | 3.76 seconds |
Started | Aug 23 05:59:58 AM UTC 24 |
Finished | Aug 23 06:00:03 AM UTC 24 |
Peak memory | 221808 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901656110 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.2901656110 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1025887092 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 334498476 ps |
CPU time | 6.96 seconds |
Started | Aug 23 05:59:41 AM UTC 24 |
Finished | Aug 23 05:59:49 AM UTC 24 |
Peak memory | 229200 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025887092 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1025887092 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.795648894 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 296025292 ps |
CPU time | 34.71 seconds |
Started | Aug 23 05:59:43 AM UTC 24 |
Finished | Aug 23 06:00:19 AM UTC 24 |
Peak memory | 221820 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795648894 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.795648894 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.803366378 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 563957955 ps |
CPU time | 4.39 seconds |
Started | Aug 23 06:00:20 AM UTC 24 |
Finished | Aug 23 06:00:25 AM UTC 24 |
Peak memory | 221884 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803366378 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.803366378 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.918896141 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 1659726403 ps |
CPU time | 3.79 seconds |
Started | Aug 23 06:00:20 AM UTC 24 |
Finished | Aug 23 06:00:25 AM UTC 24 |
Peak memory | 229176 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918896141 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.918896141 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.996416988 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 163451609 ps |
CPU time | 5.72 seconds |
Started | Aug 23 06:00:15 AM UTC 24 |
Finished | Aug 23 06:00:22 AM UTC 24 |
Peak memory | 221884 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996416988 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.996416988 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.641051868 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 383982589 ps |
CPU time | 4.33 seconds |
Started | Aug 23 06:00:22 AM UTC 24 |
Finished | Aug 23 06:00:27 AM UTC 24 |
Peak memory | 229208 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=641051868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ro m_ctrl_csr_mem_rw_with_rand_reset.641051868 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2582607628 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 257213810 ps |
CPU time | 4.33 seconds |
Started | Aug 23 06:00:16 AM UTC 24 |
Finished | Aug 23 06:00:21 AM UTC 24 |
Peak memory | 229212 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582607628 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2582607628 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3289704655 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 251202095 ps |
CPU time | 4.25 seconds |
Started | Aug 23 06:00:14 AM UTC 24 |
Finished | Aug 23 06:00:19 AM UTC 24 |
Peak memory | 221620 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289704655 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.3289704655 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1312052192 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 174963404 ps |
CPU time | 3.66 seconds |
Started | Aug 23 06:00:08 AM UTC 24 |
Finished | Aug 23 06:00:12 AM UTC 24 |
Peak memory | 221620 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312052192 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.1312052192 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2616032400 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 129146894 ps |
CPU time | 4.36 seconds |
Started | Aug 23 06:00:22 AM UTC 24 |
Finished | Aug 23 06:00:27 AM UTC 24 |
Peak memory | 228276 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616032400 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.2616032400 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2905943665 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 334781628 ps |
CPU time | 7.54 seconds |
Started | Aug 23 06:00:02 AM UTC 24 |
Finished | Aug 23 06:00:15 AM UTC 24 |
Peak memory | 227996 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905943665 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2905943665 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.749889209 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 809009467 ps |
CPU time | 64.22 seconds |
Started | Aug 23 06:00:08 AM UTC 24 |
Finished | Aug 23 06:01:14 AM UTC 24 |
Peak memory | 224060 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749889209 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.749889209 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1753315558 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 129903539 ps |
CPU time | 4.41 seconds |
Started | Aug 23 06:00:34 AM UTC 24 |
Finished | Aug 23 06:00:40 AM UTC 24 |
Peak memory | 228028 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753315558 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.1753315558 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.462620137 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1656683216 ps |
CPU time | 3.99 seconds |
Started | Aug 23 06:00:33 AM UTC 24 |
Finished | Aug 23 06:00:38 AM UTC 24 |
Peak memory | 229344 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462620137 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.462620137 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1663540336 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 266919682 ps |
CPU time | 5.69 seconds |
Started | Aug 23 06:00:28 AM UTC 24 |
Finished | Aug 23 06:00:35 AM UTC 24 |
Peak memory | 229244 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663540336 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.1663540336 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3217890705 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 170489724 ps |
CPU time | 4.05 seconds |
Started | Aug 23 06:00:35 AM UTC 24 |
Finished | Aug 23 06:00:41 AM UTC 24 |
Peak memory | 226108 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3217890705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r om_ctrl_csr_mem_rw_with_rand_reset.3217890705 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3599765510 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 129153937 ps |
CPU time | 4.42 seconds |
Started | Aug 23 06:00:30 AM UTC 24 |
Finished | Aug 23 06:00:36 AM UTC 24 |
Peak memory | 221752 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599765510 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3599765510 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.864806306 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 335595596 ps |
CPU time | 3.61 seconds |
Started | Aug 23 06:00:28 AM UTC 24 |
Finished | Aug 23 06:00:33 AM UTC 24 |
Peak memory | 221748 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864806306 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.864806306 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2580059534 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 496658285 ps |
CPU time | 4.37 seconds |
Started | Aug 23 06:00:28 AM UTC 24 |
Finished | Aug 23 06:00:34 AM UTC 24 |
Peak memory | 221692 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580059534 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.2580059534 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1766685567 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 1491223329 ps |
CPU time | 16.68 seconds |
Started | Aug 23 06:00:25 AM UTC 24 |
Finished | Aug 23 06:00:43 AM UTC 24 |
Peak memory | 221856 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766685567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1766685567 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.926583004 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 129465256 ps |
CPU time | 4.48 seconds |
Started | Aug 23 06:00:35 AM UTC 24 |
Finished | Aug 23 06:00:41 AM UTC 24 |
Peak memory | 228952 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926583004 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.926583004 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3577220209 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 519596751 ps |
CPU time | 7.56 seconds |
Started | Aug 23 06:00:26 AM UTC 24 |
Finished | Aug 23 06:00:35 AM UTC 24 |
Peak memory | 229272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577220209 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3577220209 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1616801030 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 861230607 ps |
CPU time | 63.04 seconds |
Started | Aug 23 06:00:27 AM UTC 24 |
Finished | Aug 23 06:01:32 AM UTC 24 |
Peak memory | 229256 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616801030 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1616801030 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2102888216 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 427242262 ps |
CPU time | 4.19 seconds |
Started | Aug 23 06:00:44 AM UTC 24 |
Finished | Aug 23 06:00:49 AM UTC 24 |
Peak memory | 229300 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2102888216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r om_ctrl_csr_mem_rw_with_rand_reset.2102888216 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2166911728 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 132201578 ps |
CPU time | 4.52 seconds |
Started | Aug 23 06:00:42 AM UTC 24 |
Finished | Aug 23 06:00:48 AM UTC 24 |
Peak memory | 221752 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166911728 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2166911728 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2100967234 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 2016551190 ps |
CPU time | 19.02 seconds |
Started | Aug 23 06:00:36 AM UTC 24 |
Finished | Aug 23 06:00:57 AM UTC 24 |
Peak memory | 222048 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100967234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.2100967234 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3843459769 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 128611513 ps |
CPU time | 4.71 seconds |
Started | Aug 23 06:00:42 AM UTC 24 |
Finished | Aug 23 06:00:48 AM UTC 24 |
Peak memory | 221804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843459769 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.3843459769 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1552504825 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 260838019 ps |
CPU time | 6.85 seconds |
Started | Aug 23 06:00:40 AM UTC 24 |
Finished | Aug 23 06:00:47 AM UTC 24 |
Peak memory | 227996 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552504825 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1552504825 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.820918919 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 848464029 ps |
CPU time | 34.7 seconds |
Started | Aug 23 06:00:41 AM UTC 24 |
Finished | Aug 23 06:01:17 AM UTC 24 |
Peak memory | 221948 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820918919 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.820918919 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2313180571 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 102099832 ps |
CPU time | 4.53 seconds |
Started | Aug 23 06:00:56 AM UTC 24 |
Finished | Aug 23 06:01:02 AM UTC 24 |
Peak memory | 229280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2313180571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r om_ctrl_csr_mem_rw_with_rand_reset.2313180571 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1666002706 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 288668000 ps |
CPU time | 3.78 seconds |
Started | Aug 23 06:00:50 AM UTC 24 |
Finished | Aug 23 06:00:55 AM UTC 24 |
Peak memory | 221744 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666002706 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1666002706 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3815593566 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 1452379035 ps |
CPU time | 16.79 seconds |
Started | Aug 23 06:00:48 AM UTC 24 |
Finished | Aug 23 06:01:06 AM UTC 24 |
Peak memory | 221856 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815593566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.3815593566 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.341104088 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 262915803 ps |
CPU time | 4.4 seconds |
Started | Aug 23 06:00:53 AM UTC 24 |
Finished | Aug 23 06:00:58 AM UTC 24 |
Peak memory | 221820 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341104088 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.341104088 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3987903710 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 574690779 ps |
CPU time | 7.81 seconds |
Started | Aug 23 06:00:49 AM UTC 24 |
Finished | Aug 23 06:00:58 AM UTC 24 |
Peak memory | 229272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987903710 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3987903710 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3788431310 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1465500376 ps |
CPU time | 37.48 seconds |
Started | Aug 23 06:00:49 AM UTC 24 |
Finished | Aug 23 06:01:28 AM UTC 24 |
Peak memory | 223868 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788431310 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.3788431310 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2764514082 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 418653189 ps |
CPU time | 4.48 seconds |
Started | Aug 23 06:01:07 AM UTC 24 |
Finished | Aug 23 06:01:13 AM UTC 24 |
Peak memory | 229240 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2764514082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r om_ctrl_csr_mem_rw_with_rand_reset.2764514082 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3982223292 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 168368857 ps |
CPU time | 3.83 seconds |
Started | Aug 23 06:01:02 AM UTC 24 |
Finished | Aug 23 06:01:07 AM UTC 24 |
Peak memory | 228356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982223292 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3982223292 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1866372181 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 363488887 ps |
CPU time | 16.67 seconds |
Started | Aug 23 06:00:57 AM UTC 24 |
Finished | Aug 23 06:01:15 AM UTC 24 |
Peak memory | 221984 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866372181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.1866372181 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3878670227 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 966311852 ps |
CPU time | 6.15 seconds |
Started | Aug 23 06:01:07 AM UTC 24 |
Finished | Aug 23 06:01:14 AM UTC 24 |
Peak memory | 221808 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878670227 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.3878670227 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2087805750 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 659264967 ps |
CPU time | 8.32 seconds |
Started | Aug 23 06:00:59 AM UTC 24 |
Finished | Aug 23 06:01:08 AM UTC 24 |
Peak memory | 228060 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087805750 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2087805750 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1875071467 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 132687224 ps |
CPU time | 4.65 seconds |
Started | Aug 23 06:01:16 AM UTC 24 |
Finished | Aug 23 06:01:21 AM UTC 24 |
Peak memory | 226108 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1875071467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r om_ctrl_csr_mem_rw_with_rand_reset.1875071467 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.662099033 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 133911820 ps |
CPU time | 4.54 seconds |
Started | Aug 23 06:01:14 AM UTC 24 |
Finished | Aug 23 06:01:20 AM UTC 24 |
Peak memory | 228024 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662099033 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.662099033 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1237227167 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 1036057630 ps |
CPU time | 19.71 seconds |
Started | Aug 23 06:01:08 AM UTC 24 |
Finished | Aug 23 06:01:29 AM UTC 24 |
Peak memory | 221984 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237227167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1237227167 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3513529153 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 85600110 ps |
CPU time | 3.77 seconds |
Started | Aug 23 06:01:16 AM UTC 24 |
Finished | Aug 23 06:01:20 AM UTC 24 |
Peak memory | 221824 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513529153 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.3513529153 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.421213914 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 167733575 ps |
CPU time | 9.09 seconds |
Started | Aug 23 06:01:09 AM UTC 24 |
Finished | Aug 23 06:01:19 AM UTC 24 |
Peak memory | 229280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421213914 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.421213914 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4225527949 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 279315619 ps |
CPU time | 67.1 seconds |
Started | Aug 23 06:01:13 AM UTC 24 |
Finished | Aug 23 06:02:22 AM UTC 24 |
Peak memory | 221944 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225527949 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.4225527949 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.238520786 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 527628622 ps |
CPU time | 5.74 seconds |
Started | Aug 23 06:01:27 AM UTC 24 |
Finished | Aug 23 06:01:34 AM UTC 24 |
Peak memory | 229300 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=238520786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ro m_ctrl_csr_mem_rw_with_rand_reset.238520786 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.857424732 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 775071808 ps |
CPU time | 4.36 seconds |
Started | Aug 23 06:01:21 AM UTC 24 |
Finished | Aug 23 06:01:26 AM UTC 24 |
Peak memory | 221752 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857424732 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.857424732 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1578977266 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 1494165750 ps |
CPU time | 17 seconds |
Started | Aug 23 06:01:18 AM UTC 24 |
Finished | Aug 23 06:01:36 AM UTC 24 |
Peak memory | 221856 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578977266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.1578977266 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2933424717 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 168531630 ps |
CPU time | 3.83 seconds |
Started | Aug 23 06:01:22 AM UTC 24 |
Finished | Aug 23 06:01:27 AM UTC 24 |
Peak memory | 221808 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933424717 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.2933424717 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3429024659 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 126408497 ps |
CPU time | 6.94 seconds |
Started | Aug 23 06:01:20 AM UTC 24 |
Finished | Aug 23 06:01:28 AM UTC 24 |
Peak memory | 229200 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429024659 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3429024659 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3823126325 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 206094998 ps |
CPU time | 34.52 seconds |
Started | Aug 23 06:01:21 AM UTC 24 |
Finished | Aug 23 06:01:56 AM UTC 24 |
Peak memory | 229184 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823126325 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.3823126325 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2753112187 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 5101410313 ps |
CPU time | 104.56 seconds |
Started | Aug 23 06:05:55 AM UTC 24 |
Finished | Aug 23 06:07:42 AM UTC 24 |
Peak memory | 224788 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753112187 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.2753112187 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3110086939 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 144013511 ps |
CPU time | 5.88 seconds |
Started | Aug 23 06:05:55 AM UTC 24 |
Finished | Aug 23 06:06:02 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110086939 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3110086939 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2868975149 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 721182140 ps |
CPU time | 104.15 seconds |
Started | Aug 23 06:05:56 AM UTC 24 |
Finished | Aug 23 06:07:42 AM UTC 24 |
Peak memory | 256612 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868975149 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2868975149 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3262951933 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 523374999 ps |
CPU time | 3.75 seconds |
Started | Aug 23 06:06:00 AM UTC 24 |
Finished | Aug 23 06:06:04 AM UTC 24 |
Peak memory | 221512 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262951933 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3262951933 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2712687674 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1757594549 ps |
CPU time | 104.71 seconds |
Started | Aug 23 06:05:57 AM UTC 24 |
Finished | Aug 23 06:07:44 AM UTC 24 |
Peak memory | 256828 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712687674 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.2712687674 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1397373484 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 98901123 ps |
CPU time | 4.83 seconds |
Started | Aug 23 06:05:57 AM UTC 24 |
Finished | Aug 23 06:06:04 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397373484 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1397373484 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2208649974 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 566503909 ps |
CPU time | 48.68 seconds |
Started | Aug 23 06:05:58 AM UTC 24 |
Finished | Aug 23 06:06:49 AM UTC 24 |
Peak memory | 257484 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208649974 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2208649974 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2981031851 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 98950112 ps |
CPU time | 5.03 seconds |
Started | Aug 23 06:05:56 AM UTC 24 |
Finished | Aug 23 06:06:02 AM UTC 24 |
Peak memory | 223320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981031851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2981031851 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.324638223 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 1132886295 ps |
CPU time | 4.42 seconds |
Started | Aug 23 06:07:07 AM UTC 24 |
Finished | Aug 23 06:07:13 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324638223 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.324638223 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1408578653 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 2602361443 ps |
CPU time | 66.2 seconds |
Started | Aug 23 06:07:01 AM UTC 24 |
Finished | Aug 23 06:08:09 AM UTC 24 |
Peak memory | 221548 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408578653 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.1408578653 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.656129218 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 521330382 ps |
CPU time | 10.1 seconds |
Started | Aug 23 06:07:05 AM UTC 24 |
Finished | Aug 23 06:07:16 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656129218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.656129218 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1452417984 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 98433230 ps |
CPU time | 5.07 seconds |
Started | Aug 23 06:07:01 AM UTC 24 |
Finished | Aug 23 06:07:07 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452417984 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1452417984 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.846643496 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 303103258 ps |
CPU time | 14.79 seconds |
Started | Aug 23 06:06:59 AM UTC 24 |
Finished | Aug 23 06:07:15 AM UTC 24 |
Peak memory | 225372 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846643496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.846643496 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4231431806 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 5271433386 ps |
CPU time | 120.71 seconds |
Started | Aug 23 06:07:07 AM UTC 24 |
Finished | Aug 23 06:09:10 AM UTC 24 |
Peak memory | 245196 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4231431806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4231431806 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3823694010 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 1037780098 ps |
CPU time | 4.32 seconds |
Started | Aug 23 06:07:26 AM UTC 24 |
Finished | Aug 23 06:07:31 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823694010 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3823694010 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2231073779 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 3024277296 ps |
CPU time | 131.5 seconds |
Started | Aug 23 06:07:15 AM UTC 24 |
Finished | Aug 23 06:09:29 AM UTC 24 |
Peak memory | 253356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231073779 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.2231073779 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1347685607 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 261885349 ps |
CPU time | 10.7 seconds |
Started | Aug 23 06:07:17 AM UTC 24 |
Finished | Aug 23 06:07:29 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347685607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1347685607 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1196897697 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 486969185 ps |
CPU time | 5.69 seconds |
Started | Aug 23 06:07:13 AM UTC 24 |
Finished | Aug 23 06:07:20 AM UTC 24 |
Peak memory | 221216 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196897697 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1196897697 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3343760362 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 633600138 ps |
CPU time | 15.66 seconds |
Started | Aug 23 06:07:08 AM UTC 24 |
Finished | Aug 23 06:07:25 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334376036 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.3343760362 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1007681576 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 5061794113 ps |
CPU time | 98.8 seconds |
Started | Aug 23 06:07:21 AM UTC 24 |
Finished | Aug 23 06:09:01 AM UTC 24 |
Peak memory | 232916 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1007681576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1007681576 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.324205928 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 132693335 ps |
CPU time | 4.4 seconds |
Started | Aug 23 06:07:32 AM UTC 24 |
Finished | Aug 23 06:07:37 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324205928 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.324205928 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1952723666 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 9284549955 ps |
CPU time | 114.87 seconds |
Started | Aug 23 06:07:30 AM UTC 24 |
Finished | Aug 23 06:09:27 AM UTC 24 |
Peak memory | 254432 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952723666 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.1952723666 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.345013412 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 261687352 ps |
CPU time | 10.03 seconds |
Started | Aug 23 06:07:31 AM UTC 24 |
Finished | Aug 23 06:07:42 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345013412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.345013412 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.886606564 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 514697490 ps |
CPU time | 7.67 seconds |
Started | Aug 23 06:07:27 AM UTC 24 |
Finished | Aug 23 06:07:35 AM UTC 24 |
Peak memory | 221528 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886606564 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.886606564 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1113615942 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 5750104263 ps |
CPU time | 15.44 seconds |
Started | Aug 23 06:07:27 AM UTC 24 |
Finished | Aug 23 06:07:43 AM UTC 24 |
Peak memory | 227568 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111361594 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.1113615942 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2630861411 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 34763353175 ps |
CPU time | 46.15 seconds |
Started | Aug 23 06:07:32 AM UTC 24 |
Finished | Aug 23 06:08:19 AM UTC 24 |
Peak memory | 239052 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2630861411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2630861411 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1404041080 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 514658265 ps |
CPU time | 4.43 seconds |
Started | Aug 23 06:07:43 AM UTC 24 |
Finished | Aug 23 06:07:49 AM UTC 24 |
Peak memory | 221580 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404041080 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1404041080 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2466609843 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1356428993 ps |
CPU time | 52.56 seconds |
Started | Aug 23 06:07:38 AM UTC 24 |
Finished | Aug 23 06:08:32 AM UTC 24 |
Peak memory | 223528 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466609843 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.2466609843 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.4105828116 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1078491580 ps |
CPU time | 10.02 seconds |
Started | Aug 23 06:07:42 AM UTC 24 |
Finished | Aug 23 06:07:53 AM UTC 24 |
Peak memory | 221352 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105828116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4105828116 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2153820891 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 97158924 ps |
CPU time | 4.98 seconds |
Started | Aug 23 06:07:36 AM UTC 24 |
Finished | Aug 23 06:07:42 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153820891 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2153820891 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.79771835 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 512548451 ps |
CPU time | 10.55 seconds |
Started | Aug 23 06:07:33 AM UTC 24 |
Finished | Aug 23 06:07:44 AM UTC 24 |
Peak memory | 225444 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79771835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.79771835 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1254460155 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 334316980 ps |
CPU time | 3.78 seconds |
Started | Aug 23 06:07:51 AM UTC 24 |
Finished | Aug 23 06:07:56 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254460155 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1254460155 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3015356509 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 2811483347 ps |
CPU time | 125.5 seconds |
Started | Aug 23 06:07:45 AM UTC 24 |
Finished | Aug 23 06:09:53 AM UTC 24 |
Peak memory | 223668 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015356509 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3015356509 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2398930225 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 261222884 ps |
CPU time | 10.09 seconds |
Started | Aug 23 06:07:45 AM UTC 24 |
Finished | Aug 23 06:07:56 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398930225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2398930225 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.3844092281 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 141851415 ps |
CPU time | 5.71 seconds |
Started | Aug 23 06:07:44 AM UTC 24 |
Finished | Aug 23 06:07:51 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844092281 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3844092281 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.132064942 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 699748483 ps |
CPU time | 12.07 seconds |
Started | Aug 23 06:07:43 AM UTC 24 |
Finished | Aug 23 06:07:56 AM UTC 24 |
Peak memory | 223580 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132064942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.132064942 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2421046395 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 17307291025 ps |
CPU time | 257.58 seconds |
Started | Aug 23 06:07:49 AM UTC 24 |
Finished | Aug 23 06:12:10 AM UTC 24 |
Peak memory | 246252 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2421046395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2421046395 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3000788617 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 245638153 ps |
CPU time | 4.48 seconds |
Started | Aug 23 06:07:57 AM UTC 24 |
Finished | Aug 23 06:08:02 AM UTC 24 |
Peak memory | 221104 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000788617 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3000788617 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4075904548 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 2733177362 ps |
CPU time | 122.57 seconds |
Started | Aug 23 06:07:55 AM UTC 24 |
Finished | Aug 23 06:09:59 AM UTC 24 |
Peak memory | 257400 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075904548 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.4075904548 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.2039779064 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 519158188 ps |
CPU time | 9.97 seconds |
Started | Aug 23 06:07:57 AM UTC 24 |
Finished | Aug 23 06:08:08 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039779064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2039779064 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3046289318 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1697756671 ps |
CPU time | 5.85 seconds |
Started | Aug 23 06:07:54 AM UTC 24 |
Finished | Aug 23 06:08:00 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046289318 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3046289318 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3503361217 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 197646997 ps |
CPU time | 9.37 seconds |
Started | Aug 23 06:07:54 AM UTC 24 |
Finished | Aug 23 06:08:04 AM UTC 24 |
Peak memory | 223648 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350336121 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.3503361217 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2893328366 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 9697421068 ps |
CPU time | 119.2 seconds |
Started | Aug 23 06:07:57 AM UTC 24 |
Finished | Aug 23 06:09:58 AM UTC 24 |
Peak memory | 243148 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2893328366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2893328366 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.982094831 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 127486123 ps |
CPU time | 4.39 seconds |
Started | Aug 23 06:08:03 AM UTC 24 |
Finished | Aug 23 06:08:08 AM UTC 24 |
Peak memory | 221580 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982094831 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.982094831 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3773622856 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 4452637282 ps |
CPU time | 139.24 seconds |
Started | Aug 23 06:08:01 AM UTC 24 |
Finished | Aug 23 06:10:22 AM UTC 24 |
Peak memory | 252516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773622856 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.3773622856 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.712968500 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 350394467 ps |
CPU time | 5.66 seconds |
Started | Aug 23 06:08:00 AM UTC 24 |
Finished | Aug 23 06:08:06 AM UTC 24 |
Peak memory | 221464 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712968500 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.712968500 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1406373207 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1658679850 ps |
CPU time | 17.23 seconds |
Started | Aug 23 06:07:57 AM UTC 24 |
Finished | Aug 23 06:08:15 AM UTC 24 |
Peak memory | 225440 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140637320 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1406373207 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.89940171 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 10060981350 ps |
CPU time | 84.21 seconds |
Started | Aug 23 06:08:02 AM UTC 24 |
Finished | Aug 23 06:09:28 AM UTC 24 |
Peak memory | 243348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=89940171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.89940171 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.3730916305 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 891785124 ps |
CPU time | 4.38 seconds |
Started | Aug 23 06:08:10 AM UTC 24 |
Finished | Aug 23 06:08:16 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730916305 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3730916305 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.565987381 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 13705004392 ps |
CPU time | 94.32 seconds |
Started | Aug 23 06:08:07 AM UTC 24 |
Finished | Aug 23 06:09:44 AM UTC 24 |
Peak memory | 223592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565987381 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.565987381 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1084593181 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 520838912 ps |
CPU time | 10.01 seconds |
Started | Aug 23 06:08:08 AM UTC 24 |
Finished | Aug 23 06:08:20 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084593181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1084593181 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3611005902 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 269374518 ps |
CPU time | 5.68 seconds |
Started | Aug 23 06:08:05 AM UTC 24 |
Finished | Aug 23 06:08:12 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611005902 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3611005902 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3311908852 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 861903557 ps |
CPU time | 12.68 seconds |
Started | Aug 23 06:08:04 AM UTC 24 |
Finished | Aug 23 06:08:18 AM UTC 24 |
Peak memory | 223328 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331190885 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.3311908852 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1650572252 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 30818187290 ps |
CPU time | 257.38 seconds |
Started | Aug 23 06:08:09 AM UTC 24 |
Finished | Aug 23 06:12:31 AM UTC 24 |
Peak memory | 248368 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1650572252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1650572252 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.371302989 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 520259591 ps |
CPU time | 4.44 seconds |
Started | Aug 23 06:08:16 AM UTC 24 |
Finished | Aug 23 06:08:21 AM UTC 24 |
Peak memory | 221388 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371302989 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.371302989 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3415879252 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 9722101330 ps |
CPU time | 98.55 seconds |
Started | Aug 23 06:08:12 AM UTC 24 |
Finished | Aug 23 06:09:53 AM UTC 24 |
Peak memory | 257436 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415879252 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.3415879252 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3160518963 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 1185167979 ps |
CPU time | 8.57 seconds |
Started | Aug 23 06:08:12 AM UTC 24 |
Finished | Aug 23 06:08:22 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160518963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3160518963 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2588468278 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 138024525 ps |
CPU time | 5.53 seconds |
Started | Aug 23 06:08:11 AM UTC 24 |
Finished | Aug 23 06:08:18 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588468278 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2588468278 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1695923475 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 2017806469 ps |
CPU time | 10.54 seconds |
Started | Aug 23 06:08:10 AM UTC 24 |
Finished | Aug 23 06:08:22 AM UTC 24 |
Peak memory | 223520 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169592347 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.1695923475 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2215798773 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 3481294651 ps |
CPU time | 113.56 seconds |
Started | Aug 23 06:08:15 AM UTC 24 |
Finished | Aug 23 06:10:10 AM UTC 24 |
Peak memory | 243148 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2215798773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2215798773 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.2199473726 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 184972153 ps |
CPU time | 4.61 seconds |
Started | Aug 23 06:08:21 AM UTC 24 |
Finished | Aug 23 06:08:27 AM UTC 24 |
Peak memory | 221388 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199473726 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2199473726 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.147119545 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1668350446 ps |
CPU time | 91.71 seconds |
Started | Aug 23 06:08:19 AM UTC 24 |
Finished | Aug 23 06:09:52 AM UTC 24 |
Peak memory | 257208 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147119545 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.147119545 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2196767692 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 379192535 ps |
CPU time | 8.69 seconds |
Started | Aug 23 06:08:19 AM UTC 24 |
Finished | Aug 23 06:08:29 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196767692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2196767692 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.4001068814 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 384510616 ps |
CPU time | 4.9 seconds |
Started | Aug 23 06:08:19 AM UTC 24 |
Finished | Aug 23 06:08:25 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001068814 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4001068814 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1966388123 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1071212623 ps |
CPU time | 10.57 seconds |
Started | Aug 23 06:08:17 AM UTC 24 |
Finished | Aug 23 06:08:28 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196638812 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.1966388123 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4237189539 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 141694653 ps |
CPU time | 3.81 seconds |
Started | Aug 23 06:06:05 AM UTC 24 |
Finished | Aug 23 06:06:10 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237189539 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4237189539 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.72167307 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 392634783 ps |
CPU time | 5.19 seconds |
Started | Aug 23 06:06:02 AM UTC 24 |
Finished | Aug 23 06:06:08 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72167307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.72167307 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3173088288 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 98876367 ps |
CPU time | 5.02 seconds |
Started | Aug 23 06:06:01 AM UTC 24 |
Finished | Aug 23 06:06:07 AM UTC 24 |
Peak memory | 223512 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173088288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3173088288 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3846926467 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 11233438390 ps |
CPU time | 114.21 seconds |
Started | Aug 23 06:06:03 AM UTC 24 |
Finished | Aug 23 06:07:59 AM UTC 24 |
Peak memory | 243148 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3846926467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3846926467 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1400498941 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 126872717 ps |
CPU time | 4.45 seconds |
Started | Aug 23 06:08:27 AM UTC 24 |
Finished | Aug 23 06:08:33 AM UTC 24 |
Peak memory | 221388 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400498941 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1400498941 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3517082023 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 2475558787 ps |
CPU time | 97.29 seconds |
Started | Aug 23 06:08:23 AM UTC 24 |
Finished | Aug 23 06:10:02 AM UTC 24 |
Peak memory | 253424 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517082023 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.3517082023 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.872104887 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 273658232 ps |
CPU time | 10.02 seconds |
Started | Aug 23 06:08:26 AM UTC 24 |
Finished | Aug 23 06:08:37 AM UTC 24 |
Peak memory | 221352 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872104887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.872104887 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3715337795 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 533476505 ps |
CPU time | 5.55 seconds |
Started | Aug 23 06:08:23 AM UTC 24 |
Finished | Aug 23 06:08:30 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715337795 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3715337795 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3417525310 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2717579538 ps |
CPU time | 13.63 seconds |
Started | Aug 23 06:08:22 AM UTC 24 |
Finished | Aug 23 06:08:37 AM UTC 24 |
Peak memory | 225520 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341752531 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.3417525310 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2881852835 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 4198698239 ps |
CPU time | 84.66 seconds |
Started | Aug 23 06:08:26 AM UTC 24 |
Finished | Aug 23 06:09:53 AM UTC 24 |
Peak memory | 239052 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2881852835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2881852835 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2782548407 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 333534109 ps |
CPU time | 3.79 seconds |
Started | Aug 23 06:08:35 AM UTC 24 |
Finished | Aug 23 06:08:40 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782548407 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2782548407 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3066214252 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 5717405576 ps |
CPU time | 77.29 seconds |
Started | Aug 23 06:08:30 AM UTC 24 |
Finished | Aug 23 06:09:49 AM UTC 24 |
Peak memory | 257416 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066214252 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.3066214252 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1968303385 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 177433456 ps |
CPU time | 8.66 seconds |
Started | Aug 23 06:08:32 AM UTC 24 |
Finished | Aug 23 06:08:42 AM UTC 24 |
Peak memory | 221412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968303385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1968303385 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.4223501599 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 690365410 ps |
CPU time | 4.83 seconds |
Started | Aug 23 06:08:29 AM UTC 24 |
Finished | Aug 23 06:08:35 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223501599 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4223501599 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1886791577 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 649031108 ps |
CPU time | 15.78 seconds |
Started | Aug 23 06:08:29 AM UTC 24 |
Finished | Aug 23 06:08:46 AM UTC 24 |
Peak memory | 227504 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188679157 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.1886791577 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.868953186 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 9660084747 ps |
CPU time | 285.03 seconds |
Started | Aug 23 06:08:33 AM UTC 24 |
Finished | Aug 23 06:13:22 AM UTC 24 |
Peak memory | 236208 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=868953186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 21.rom_ctrl_stress_all_with_rand_reset.868953186 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1652732800 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 153033651 ps |
CPU time | 4.42 seconds |
Started | Aug 23 06:08:47 AM UTC 24 |
Finished | Aug 23 06:08:52 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652732800 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1652732800 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2694322840 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 2195335429 ps |
CPU time | 96.06 seconds |
Started | Aug 23 06:08:41 AM UTC 24 |
Finished | Aug 23 06:10:18 AM UTC 24 |
Peak memory | 244176 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694322840 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.2694322840 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2678428747 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 348145760 ps |
CPU time | 8.6 seconds |
Started | Aug 23 06:08:43 AM UTC 24 |
Finished | Aug 23 06:08:52 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678428747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2678428747 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.84620863 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 138950831 ps |
CPU time | 5.48 seconds |
Started | Aug 23 06:08:39 AM UTC 24 |
Finished | Aug 23 06:08:45 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84620863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.84620863 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.564504466 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 6082089060 ps |
CPU time | 23.68 seconds |
Started | Aug 23 06:08:37 AM UTC 24 |
Finished | Aug 23 06:09:02 AM UTC 24 |
Peak memory | 227756 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564504466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.564504466 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2701710556 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 8076675692 ps |
CPU time | 131.7 seconds |
Started | Aug 23 06:08:46 AM UTC 24 |
Finished | Aug 23 06:11:00 AM UTC 24 |
Peak memory | 232908 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2701710556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2701710556 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3573115497 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 350774079 ps |
CPU time | 3.78 seconds |
Started | Aug 23 06:09:03 AM UTC 24 |
Finished | Aug 23 06:09:08 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573115497 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3573115497 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.857840373 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 16261965526 ps |
CPU time | 96 seconds |
Started | Aug 23 06:08:56 AM UTC 24 |
Finished | Aug 23 06:10:34 AM UTC 24 |
Peak memory | 242056 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857840373 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.857840373 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1378745327 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 618567692 ps |
CPU time | 8.67 seconds |
Started | Aug 23 06:09:00 AM UTC 24 |
Finished | Aug 23 06:09:10 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378745327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1378745327 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.339374795 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 164223534 ps |
CPU time | 5.31 seconds |
Started | Aug 23 06:08:53 AM UTC 24 |
Finished | Aug 23 06:08:59 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339374795 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.339374795 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1340858842 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 405915123 ps |
CPU time | 11.41 seconds |
Started | Aug 23 06:08:53 AM UTC 24 |
Finished | Aug 23 06:09:05 AM UTC 24 |
Peak memory | 225456 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134085884 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.1340858842 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1968648022 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 5223993466 ps |
CPU time | 167.3 seconds |
Started | Aug 23 06:09:02 AM UTC 24 |
Finished | Aug 23 06:11:52 AM UTC 24 |
Peak memory | 232908 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1968648022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1968648022 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3814102460 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 266757780 ps |
CPU time | 4.41 seconds |
Started | Aug 23 06:09:14 AM UTC 24 |
Finished | Aug 23 06:09:20 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814102460 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3814102460 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3931377048 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 15210541614 ps |
CPU time | 120.66 seconds |
Started | Aug 23 06:09:08 AM UTC 24 |
Finished | Aug 23 06:11:11 AM UTC 24 |
Peak memory | 223724 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931377048 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.3931377048 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2763526496 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 171604078 ps |
CPU time | 9.01 seconds |
Started | Aug 23 06:09:10 AM UTC 24 |
Finished | Aug 23 06:09:20 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763526496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2763526496 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3971207407 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1356311481 ps |
CPU time | 5.92 seconds |
Started | Aug 23 06:09:07 AM UTC 24 |
Finished | Aug 23 06:09:14 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971207407 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3971207407 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3385402594 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 768609778 ps |
CPU time | 8.94 seconds |
Started | Aug 23 06:09:06 AM UTC 24 |
Finished | Aug 23 06:09:16 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338540259 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.3385402594 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2376153183 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1724216506 ps |
CPU time | 93.22 seconds |
Started | Aug 23 06:09:10 AM UTC 24 |
Finished | Aug 23 06:10:45 AM UTC 24 |
Peak memory | 230988 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2376153183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2376153183 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2321072494 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 87343487 ps |
CPU time | 3.8 seconds |
Started | Aug 23 06:09:28 AM UTC 24 |
Finished | Aug 23 06:09:33 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321072494 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2321072494 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2729580205 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 3999181392 ps |
CPU time | 116.12 seconds |
Started | Aug 23 06:09:22 AM UTC 24 |
Finished | Aug 23 06:11:20 AM UTC 24 |
Peak memory | 242080 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729580205 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.2729580205 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1539227672 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 170391124 ps |
CPU time | 8.57 seconds |
Started | Aug 23 06:09:26 AM UTC 24 |
Finished | Aug 23 06:09:35 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539227672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1539227672 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2877461107 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 99971006 ps |
CPU time | 5.22 seconds |
Started | Aug 23 06:09:20 AM UTC 24 |
Finished | Aug 23 06:09:27 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877461107 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2877461107 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1413413309 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 507810064 ps |
CPU time | 7.76 seconds |
Started | Aug 23 06:09:16 AM UTC 24 |
Finished | Aug 23 06:09:25 AM UTC 24 |
Peak memory | 221472 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141341330 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.1413413309 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1869067640 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 3984038831 ps |
CPU time | 124.94 seconds |
Started | Aug 23 06:09:28 AM UTC 24 |
Finished | Aug 23 06:11:35 AM UTC 24 |
Peak memory | 233100 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1869067640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1869067640 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3622244593 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 520853402 ps |
CPU time | 6.51 seconds |
Started | Aug 23 06:09:45 AM UTC 24 |
Finished | Aug 23 06:09:52 AM UTC 24 |
Peak memory | 221580 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622244593 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3622244593 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2430926084 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 6504042927 ps |
CPU time | 153.47 seconds |
Started | Aug 23 06:09:34 AM UTC 24 |
Finished | Aug 23 06:12:10 AM UTC 24 |
Peak memory | 256704 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430926084 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2430926084 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1565892447 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1026978859 ps |
CPU time | 13.75 seconds |
Started | Aug 23 06:09:36 AM UTC 24 |
Finished | Aug 23 06:09:51 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565892447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1565892447 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2428213967 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 137329952 ps |
CPU time | 5.71 seconds |
Started | Aug 23 06:09:30 AM UTC 24 |
Finished | Aug 23 06:09:37 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428213967 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2428213967 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.267180008 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 595091344 ps |
CPU time | 23.5 seconds |
Started | Aug 23 06:09:29 AM UTC 24 |
Finished | Aug 23 06:09:53 AM UTC 24 |
Peak memory | 228820 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267180008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.267180008 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3228278140 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 9692383756 ps |
CPU time | 29.45 seconds |
Started | Aug 23 06:09:37 AM UTC 24 |
Finished | Aug 23 06:10:08 AM UTC 24 |
Peak memory | 231052 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3228278140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3228278140 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.1386561244 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 129635321 ps |
CPU time | 4.4 seconds |
Started | Aug 23 06:09:53 AM UTC 24 |
Finished | Aug 23 06:09:59 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386561244 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1386561244 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2738144695 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 1776910944 ps |
CPU time | 82.45 seconds |
Started | Aug 23 06:09:51 AM UTC 24 |
Finished | Aug 23 06:11:15 AM UTC 24 |
Peak memory | 257280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738144695 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.2738144695 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1334746257 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 665969666 ps |
CPU time | 8.63 seconds |
Started | Aug 23 06:09:53 AM UTC 24 |
Finished | Aug 23 06:10:03 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334746257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1334746257 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.4214373123 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 533333194 ps |
CPU time | 5.65 seconds |
Started | Aug 23 06:09:50 AM UTC 24 |
Finished | Aug 23 06:09:57 AM UTC 24 |
Peak memory | 221476 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214373123 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4214373123 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1728775045 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 2028766410 ps |
CPU time | 13.54 seconds |
Started | Aug 23 06:09:47 AM UTC 24 |
Finished | Aug 23 06:10:02 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172877504 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.1728775045 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.775525666 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 4039888253 ps |
CPU time | 209.09 seconds |
Started | Aug 23 06:09:53 AM UTC 24 |
Finished | Aug 23 06:13:25 AM UTC 24 |
Peak memory | 246404 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=775525666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 27.rom_ctrl_stress_all_with_rand_reset.775525666 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.472197202 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 500302175 ps |
CPU time | 4.48 seconds |
Started | Aug 23 06:10:00 AM UTC 24 |
Finished | Aug 23 06:10:05 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472197202 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.472197202 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1343627392 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 5508361299 ps |
CPU time | 70.41 seconds |
Started | Aug 23 06:09:54 AM UTC 24 |
Finished | Aug 23 06:11:07 AM UTC 24 |
Peak memory | 253400 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343627392 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.1343627392 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3683990220 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 177701463 ps |
CPU time | 8.63 seconds |
Started | Aug 23 06:09:57 AM UTC 24 |
Finished | Aug 23 06:10:07 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683990220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3683990220 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2330497644 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 546418942 ps |
CPU time | 5.95 seconds |
Started | Aug 23 06:09:54 AM UTC 24 |
Finished | Aug 23 06:10:02 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330497644 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2330497644 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3252792092 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 555181197 ps |
CPU time | 12.11 seconds |
Started | Aug 23 06:09:53 AM UTC 24 |
Finished | Aug 23 06:10:07 AM UTC 24 |
Peak memory | 225456 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325279209 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3252792092 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1295612945 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 7652867003 ps |
CPU time | 110.48 seconds |
Started | Aug 23 06:09:58 AM UTC 24 |
Finished | Aug 23 06:11:51 AM UTC 24 |
Peak memory | 231052 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1295612945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1295612945 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.10731000 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 133272568 ps |
CPU time | 4.5 seconds |
Started | Aug 23 06:10:04 AM UTC 24 |
Finished | Aug 23 06:10:09 AM UTC 24 |
Peak memory | 221316 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10731000 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.10731000 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2587645262 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 2591885012 ps |
CPU time | 101.78 seconds |
Started | Aug 23 06:10:03 AM UTC 24 |
Finished | Aug 23 06:11:46 AM UTC 24 |
Peak memory | 244844 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587645262 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.2587645262 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.734765229 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 2080350751 ps |
CPU time | 10.01 seconds |
Started | Aug 23 06:10:03 AM UTC 24 |
Finished | Aug 23 06:10:14 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734765229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.734765229 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3635133950 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 187358684 ps |
CPU time | 5.05 seconds |
Started | Aug 23 06:10:01 AM UTC 24 |
Finished | Aug 23 06:10:07 AM UTC 24 |
Peak memory | 221476 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635133950 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3635133950 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.1543328119 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1539513543 ps |
CPU time | 14.97 seconds |
Started | Aug 23 06:10:00 AM UTC 24 |
Finished | Aug 23 06:10:16 AM UTC 24 |
Peak memory | 225456 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154332811 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.1543328119 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1806380194 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 4499936373 ps |
CPU time | 126.16 seconds |
Started | Aug 23 06:10:03 AM UTC 24 |
Finished | Aug 23 06:12:11 AM UTC 24 |
Peak memory | 230860 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1806380194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1806380194 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1631067075 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 152351794 ps |
CPU time | 4.48 seconds |
Started | Aug 23 06:06:09 AM UTC 24 |
Finished | Aug 23 06:06:15 AM UTC 24 |
Peak memory | 221512 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631067075 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1631067075 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3781395063 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 4326696957 ps |
CPU time | 112.74 seconds |
Started | Aug 23 06:06:08 AM UTC 24 |
Finished | Aug 23 06:08:03 AM UTC 24 |
Peak memory | 256412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781395063 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.3781395063 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1575366636 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 169995673 ps |
CPU time | 8.81 seconds |
Started | Aug 23 06:06:09 AM UTC 24 |
Finished | Aug 23 06:06:19 AM UTC 24 |
Peak memory | 221356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575366636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1575366636 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2097906611 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 525805856 ps |
CPU time | 7.45 seconds |
Started | Aug 23 06:06:08 AM UTC 24 |
Finished | Aug 23 06:06:17 AM UTC 24 |
Peak memory | 221464 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097906611 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2097906611 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.1990511355 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1949068195 ps |
CPU time | 55.57 seconds |
Started | Aug 23 06:06:09 AM UTC 24 |
Finished | Aug 23 06:07:07 AM UTC 24 |
Peak memory | 257464 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990511355 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1990511355 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3398421954 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 541538368 ps |
CPU time | 5.68 seconds |
Started | Aug 23 06:06:05 AM UTC 24 |
Finished | Aug 23 06:06:12 AM UTC 24 |
Peak memory | 221536 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398421954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3398421954 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1128820855 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 261809965 ps |
CPU time | 10.19 seconds |
Started | Aug 23 06:06:06 AM UTC 24 |
Finished | Aug 23 06:06:17 AM UTC 24 |
Peak memory | 221276 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112882085 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.1128820855 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3917463231 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 3456837921 ps |
CPU time | 48.94 seconds |
Started | Aug 23 06:06:09 AM UTC 24 |
Finished | Aug 23 06:07:00 AM UTC 24 |
Peak memory | 228812 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3917463231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3917463231 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.410518153 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 479014031 ps |
CPU time | 4.44 seconds |
Started | Aug 23 06:10:08 AM UTC 24 |
Finished | Aug 23 06:10:14 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410518153 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.410518153 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.649724939 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 1450450465 ps |
CPU time | 84.24 seconds |
Started | Aug 23 06:10:07 AM UTC 24 |
Finished | Aug 23 06:11:33 AM UTC 24 |
Peak memory | 244748 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649724939 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.649724939 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2799489027 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 3572045947 ps |
CPU time | 9.93 seconds |
Started | Aug 23 06:10:07 AM UTC 24 |
Finished | Aug 23 06:10:18 AM UTC 24 |
Peak memory | 221412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799489027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2799489027 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3005649271 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 563409999 ps |
CPU time | 5.66 seconds |
Started | Aug 23 06:10:06 AM UTC 24 |
Finished | Aug 23 06:10:13 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005649271 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3005649271 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1731872787 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 283989801 ps |
CPU time | 11.91 seconds |
Started | Aug 23 06:10:06 AM UTC 24 |
Finished | Aug 23 06:10:19 AM UTC 24 |
Peak memory | 223520 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173187278 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.1731872787 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2438852421 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 463780123 ps |
CPU time | 3.83 seconds |
Started | Aug 23 06:10:17 AM UTC 24 |
Finished | Aug 23 06:10:22 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438852421 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2438852421 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.179335091 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 10444623861 ps |
CPU time | 59.35 seconds |
Started | Aug 23 06:10:14 AM UTC 24 |
Finished | Aug 23 06:11:15 AM UTC 24 |
Peak memory | 253380 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179335091 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.179335091 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.916154018 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 1279367694 ps |
CPU time | 8.57 seconds |
Started | Aug 23 06:10:15 AM UTC 24 |
Finished | Aug 23 06:10:25 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916154018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.916154018 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1732766019 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 193303223 ps |
CPU time | 4.88 seconds |
Started | Aug 23 06:10:11 AM UTC 24 |
Finished | Aug 23 06:10:17 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732766019 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1732766019 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2675048163 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 943526350 ps |
CPU time | 11.04 seconds |
Started | Aug 23 06:10:11 AM UTC 24 |
Finished | Aug 23 06:10:23 AM UTC 24 |
Peak memory | 224896 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267504816 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.2675048163 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.763192292 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 9012025339 ps |
CPU time | 261.9 seconds |
Started | Aug 23 06:10:15 AM UTC 24 |
Finished | Aug 23 06:14:40 AM UTC 24 |
Peak memory | 242288 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=763192292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 31.rom_ctrl_stress_all_with_rand_reset.763192292 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.4239655249 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 127071911 ps |
CPU time | 4.42 seconds |
Started | Aug 23 06:10:24 AM UTC 24 |
Finished | Aug 23 06:10:29 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239655249 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4239655249 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1679729801 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2580295989 ps |
CPU time | 116.08 seconds |
Started | Aug 23 06:10:19 AM UTC 24 |
Finished | Aug 23 06:12:18 AM UTC 24 |
Peak memory | 253528 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679729801 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.1679729801 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3756890386 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 1660453258 ps |
CPU time | 9.9 seconds |
Started | Aug 23 06:10:20 AM UTC 24 |
Finished | Aug 23 06:10:31 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756890386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3756890386 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3206632864 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 138917141 ps |
CPU time | 5.97 seconds |
Started | Aug 23 06:10:19 AM UTC 24 |
Finished | Aug 23 06:10:26 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206632864 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3206632864 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3242926988 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 228935020 ps |
CPU time | 11.67 seconds |
Started | Aug 23 06:10:17 AM UTC 24 |
Finished | Aug 23 06:10:30 AM UTC 24 |
Peak memory | 223328 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324292698 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.3242926988 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3311072435 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1130520823 ps |
CPU time | 4.33 seconds |
Started | Aug 23 06:10:32 AM UTC 24 |
Finished | Aug 23 06:10:38 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311072435 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3311072435 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1941356819 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 4755056793 ps |
CPU time | 57.68 seconds |
Started | Aug 23 06:10:27 AM UTC 24 |
Finished | Aug 23 06:11:26 AM UTC 24 |
Peak memory | 242056 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941356819 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.1941356819 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2978346372 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 305282590 ps |
CPU time | 8.8 seconds |
Started | Aug 23 06:10:30 AM UTC 24 |
Finished | Aug 23 06:10:40 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978346372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2978346372 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.980812350 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 386002104 ps |
CPU time | 4.91 seconds |
Started | Aug 23 06:10:26 AM UTC 24 |
Finished | Aug 23 06:10:32 AM UTC 24 |
Peak memory | 221464 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980812350 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.980812350 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3603953516 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 424221230 ps |
CPU time | 12.23 seconds |
Started | Aug 23 06:10:24 AM UTC 24 |
Finished | Aug 23 06:10:37 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360395351 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.3603953516 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3010538488 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2142708291 ps |
CPU time | 40.25 seconds |
Started | Aug 23 06:10:31 AM UTC 24 |
Finished | Aug 23 06:11:13 AM UTC 24 |
Peak memory | 230796 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3010538488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3010538488 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2216797909 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 131825808 ps |
CPU time | 4.38 seconds |
Started | Aug 23 06:10:41 AM UTC 24 |
Finished | Aug 23 06:10:46 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216797909 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2216797909 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1685724921 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 8362117338 ps |
CPU time | 123.08 seconds |
Started | Aug 23 06:10:38 AM UTC 24 |
Finished | Aug 23 06:12:43 AM UTC 24 |
Peak memory | 245152 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685724921 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.1685724921 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.242438150 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 762097007 ps |
CPU time | 8.6 seconds |
Started | Aug 23 06:10:39 AM UTC 24 |
Finished | Aug 23 06:10:48 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242438150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.242438150 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3881276582 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 96540550 ps |
CPU time | 5.18 seconds |
Started | Aug 23 06:10:34 AM UTC 24 |
Finished | Aug 23 06:10:41 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881276582 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3881276582 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1183700537 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 351598820 ps |
CPU time | 6.07 seconds |
Started | Aug 23 06:10:32 AM UTC 24 |
Finished | Aug 23 06:10:39 AM UTC 24 |
Peak memory | 221212 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118370053 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1183700537 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2096031436 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2906542568 ps |
CPU time | 154.2 seconds |
Started | Aug 23 06:10:40 AM UTC 24 |
Finished | Aug 23 06:13:16 AM UTC 24 |
Peak memory | 241292 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2096031436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2096031436 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.42379360 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 520030716 ps |
CPU time | 4.37 seconds |
Started | Aug 23 06:10:55 AM UTC 24 |
Finished | Aug 23 06:11:00 AM UTC 24 |
Peak memory | 221316 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42379360 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.42379360 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2080519993 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 6592446161 ps |
CPU time | 100.07 seconds |
Started | Aug 23 06:10:47 AM UTC 24 |
Finished | Aug 23 06:12:29 AM UTC 24 |
Peak memory | 223592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080519993 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.2080519993 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.84017153 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1041542280 ps |
CPU time | 10.08 seconds |
Started | Aug 23 06:10:49 AM UTC 24 |
Finished | Aug 23 06:11:00 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84017153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.84017153 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.315089573 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 98511922 ps |
CPU time | 5.2 seconds |
Started | Aug 23 06:10:46 AM UTC 24 |
Finished | Aug 23 06:10:52 AM UTC 24 |
Peak memory | 221528 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315089573 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.315089573 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.143307773 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 832138953 ps |
CPU time | 11.26 seconds |
Started | Aug 23 06:10:41 AM UTC 24 |
Finished | Aug 23 06:10:53 AM UTC 24 |
Peak memory | 225564 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143307773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.143307773 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.426436896 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 90322154837 ps |
CPU time | 157.27 seconds |
Started | Aug 23 06:10:53 AM UTC 24 |
Finished | Aug 23 06:13:33 AM UTC 24 |
Peak memory | 238140 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=426436896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 35.rom_ctrl_stress_all_with_rand_reset.426436896 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3825094468 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 89085915 ps |
CPU time | 3.84 seconds |
Started | Aug 23 06:11:12 AM UTC 24 |
Finished | Aug 23 06:11:17 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825094468 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3825094468 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2295857842 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 3477363081 ps |
CPU time | 149.45 seconds |
Started | Aug 23 06:11:01 AM UTC 24 |
Finished | Aug 23 06:13:33 AM UTC 24 |
Peak memory | 253416 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295857842 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.2295857842 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1893295385 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 3331916239 ps |
CPU time | 9.33 seconds |
Started | Aug 23 06:11:08 AM UTC 24 |
Finished | Aug 23 06:11:19 AM UTC 24 |
Peak memory | 221412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893295385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1893295385 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2338238665 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 369841005 ps |
CPU time | 4.92 seconds |
Started | Aug 23 06:11:01 AM UTC 24 |
Finished | Aug 23 06:11:07 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338238665 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2338238665 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2006358805 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 224678759 ps |
CPU time | 10.31 seconds |
Started | Aug 23 06:11:01 AM UTC 24 |
Finished | Aug 23 06:11:12 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200635880 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.2006358805 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3220318823 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 17567410392 ps |
CPU time | 216.17 seconds |
Started | Aug 23 06:11:08 AM UTC 24 |
Finished | Aug 23 06:14:47 AM UTC 24 |
Peak memory | 236164 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3220318823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3220318823 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3561085091 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 88993734 ps |
CPU time | 3.82 seconds |
Started | Aug 23 06:11:20 AM UTC 24 |
Finished | Aug 23 06:11:24 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561085091 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3561085091 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1796217764 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 13176314503 ps |
CPU time | 95.96 seconds |
Started | Aug 23 06:11:15 AM UTC 24 |
Finished | Aug 23 06:12:53 AM UTC 24 |
Peak memory | 223592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796217764 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.1796217764 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3163543507 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 581400561 ps |
CPU time | 8.61 seconds |
Started | Aug 23 06:11:16 AM UTC 24 |
Finished | Aug 23 06:11:26 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163543507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3163543507 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1193372559 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 384459906 ps |
CPU time | 5.43 seconds |
Started | Aug 23 06:11:13 AM UTC 24 |
Finished | Aug 23 06:11:20 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193372559 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1193372559 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2095704893 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 866296369 ps |
CPU time | 12.83 seconds |
Started | Aug 23 06:11:13 AM UTC 24 |
Finished | Aug 23 06:11:27 AM UTC 24 |
Peak memory | 225456 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209570489 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.2095704893 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.169612099 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 8093144689 ps |
CPU time | 131.95 seconds |
Started | Aug 23 06:11:18 AM UTC 24 |
Finished | Aug 23 06:13:32 AM UTC 24 |
Peak memory | 239244 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=169612099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.rom_ctrl_stress_all_with_rand_reset.169612099 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2915279565 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 129931904 ps |
CPU time | 4.53 seconds |
Started | Aug 23 06:11:27 AM UTC 24 |
Finished | Aug 23 06:11:33 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915279565 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2915279565 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1386006343 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 3469595637 ps |
CPU time | 101.22 seconds |
Started | Aug 23 06:11:25 AM UTC 24 |
Finished | Aug 23 06:13:08 AM UTC 24 |
Peak memory | 223596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386006343 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.1386006343 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.956719956 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 260630297 ps |
CPU time | 9.92 seconds |
Started | Aug 23 06:11:25 AM UTC 24 |
Finished | Aug 23 06:11:36 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956719956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.956719956 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1669516025 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 266411319 ps |
CPU time | 5.48 seconds |
Started | Aug 23 06:11:21 AM UTC 24 |
Finished | Aug 23 06:11:27 AM UTC 24 |
Peak memory | 221016 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669516025 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1669516025 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.395507820 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 132768970 ps |
CPU time | 7.41 seconds |
Started | Aug 23 06:11:21 AM UTC 24 |
Finished | Aug 23 06:11:29 AM UTC 24 |
Peak memory | 221020 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395507820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.395507820 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2243232534 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 2929055731 ps |
CPU time | 92.14 seconds |
Started | Aug 23 06:11:27 AM UTC 24 |
Finished | Aug 23 06:13:01 AM UTC 24 |
Peak memory | 241084 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2243232534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2243232534 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2743551487 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 127779049 ps |
CPU time | 4.42 seconds |
Started | Aug 23 06:11:36 AM UTC 24 |
Finished | Aug 23 06:11:41 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743551487 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2743551487 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2721074405 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 9294039357 ps |
CPU time | 125.09 seconds |
Started | Aug 23 06:11:31 AM UTC 24 |
Finished | Aug 23 06:13:38 AM UTC 24 |
Peak memory | 257492 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721074405 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.2721074405 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2295213085 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 3546575746 ps |
CPU time | 10.06 seconds |
Started | Aug 23 06:11:34 AM UTC 24 |
Finished | Aug 23 06:11:45 AM UTC 24 |
Peak memory | 221412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295213085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2295213085 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3867892632 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 143011333 ps |
CPU time | 5.46 seconds |
Started | Aug 23 06:11:28 AM UTC 24 |
Finished | Aug 23 06:11:35 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867892632 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3867892632 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3070659167 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1226178765 ps |
CPU time | 16.93 seconds |
Started | Aug 23 06:11:28 AM UTC 24 |
Finished | Aug 23 06:11:46 AM UTC 24 |
Peak memory | 225776 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307065916 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.3070659167 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2652746702 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 8625124632 ps |
CPU time | 79.39 seconds |
Started | Aug 23 06:11:34 AM UTC 24 |
Finished | Aug 23 06:12:55 AM UTC 24 |
Peak memory | 243148 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2652746702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2652746702 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1632165986 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 168490772 ps |
CPU time | 3.78 seconds |
Started | Aug 23 06:06:18 AM UTC 24 |
Finished | Aug 23 06:06:23 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632165986 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1632165986 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.883470146 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3033864749 ps |
CPU time | 123.61 seconds |
Started | Aug 23 06:06:12 AM UTC 24 |
Finished | Aug 23 06:08:18 AM UTC 24 |
Peak memory | 223592 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883470146 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.883470146 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1008519198 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 593253923 ps |
CPU time | 9.77 seconds |
Started | Aug 23 06:06:14 AM UTC 24 |
Finished | Aug 23 06:06:25 AM UTC 24 |
Peak memory | 221548 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008519198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1008519198 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.219252730 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 195635995 ps |
CPU time | 5.17 seconds |
Started | Aug 23 06:06:12 AM UTC 24 |
Finished | Aug 23 06:06:19 AM UTC 24 |
Peak memory | 221276 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219252730 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.219252730 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.741383451 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 574827611 ps |
CPU time | 95.16 seconds |
Started | Aug 23 06:06:17 AM UTC 24 |
Finished | Aug 23 06:07:54 AM UTC 24 |
Peak memory | 257532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741383451 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.741383451 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3675819768 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1228329580 ps |
CPU time | 5.56 seconds |
Started | Aug 23 06:06:10 AM UTC 24 |
Finished | Aug 23 06:06:17 AM UTC 24 |
Peak memory | 221464 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675819768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3675819768 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.272918316 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 285249473 ps |
CPU time | 10.87 seconds |
Started | Aug 23 06:06:10 AM UTC 24 |
Finished | Aug 23 06:06:23 AM UTC 24 |
Peak memory | 225452 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272918316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.272918316 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4017345117 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 2282554745 ps |
CPU time | 14.16 seconds |
Started | Aug 23 06:06:15 AM UTC 24 |
Finished | Aug 23 06:06:31 AM UTC 24 |
Peak memory | 228808 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4017345117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.4017345117 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.4054801324 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 2472223447 ps |
CPU time | 4.52 seconds |
Started | Aug 23 06:11:47 AM UTC 24 |
Finished | Aug 23 06:11:53 AM UTC 24 |
Peak memory | 221388 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054801324 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4054801324 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2514093075 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 7124363530 ps |
CPU time | 90.52 seconds |
Started | Aug 23 06:11:42 AM UTC 24 |
Finished | Aug 23 06:13:14 AM UTC 24 |
Peak memory | 252448 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514093075 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.2514093075 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3032923307 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 171778834 ps |
CPU time | 8.66 seconds |
Started | Aug 23 06:11:43 AM UTC 24 |
Finished | Aug 23 06:11:53 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032923307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3032923307 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3741604296 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 96842497 ps |
CPU time | 4.88 seconds |
Started | Aug 23 06:11:37 AM UTC 24 |
Finished | Aug 23 06:11:43 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741604296 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3741604296 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.4048662255 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 309427389 ps |
CPU time | 15.5 seconds |
Started | Aug 23 06:11:36 AM UTC 24 |
Finished | Aug 23 06:11:52 AM UTC 24 |
Peak memory | 225456 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404866225 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.4048662255 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1187856476 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 2288996447 ps |
CPU time | 104.13 seconds |
Started | Aug 23 06:11:45 AM UTC 24 |
Finished | Aug 23 06:13:31 AM UTC 24 |
Peak memory | 231116 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1187856476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1187856476 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3293079604 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 248057866 ps |
CPU time | 3.72 seconds |
Started | Aug 23 06:11:54 AM UTC 24 |
Finished | Aug 23 06:11:59 AM UTC 24 |
Peak memory | 221024 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293079604 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3293079604 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4243029004 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1879710017 ps |
CPU time | 81.37 seconds |
Started | Aug 23 06:11:53 AM UTC 24 |
Finished | Aug 23 06:13:16 AM UTC 24 |
Peak memory | 257020 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243029004 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.4243029004 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3987148315 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 348798783 ps |
CPU time | 8.54 seconds |
Started | Aug 23 06:11:53 AM UTC 24 |
Finished | Aug 23 06:12:02 AM UTC 24 |
Peak memory | 221604 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987148315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3987148315 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1100711829 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 272648700 ps |
CPU time | 5.93 seconds |
Started | Aug 23 06:11:52 AM UTC 24 |
Finished | Aug 23 06:11:59 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100711829 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1100711829 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1255748316 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 319652407 ps |
CPU time | 13 seconds |
Started | Aug 23 06:11:47 AM UTC 24 |
Finished | Aug 23 06:12:01 AM UTC 24 |
Peak memory | 223520 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125574831 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.1255748316 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.234442457 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 2819700281 ps |
CPU time | 87.44 seconds |
Started | Aug 23 06:11:54 AM UTC 24 |
Finished | Aug 23 06:13:23 AM UTC 24 |
Peak memory | 230468 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=234442457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 41.rom_ctrl_stress_all_with_rand_reset.234442457 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3426200515 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 1392650288 ps |
CPU time | 4.35 seconds |
Started | Aug 23 06:12:04 AM UTC 24 |
Finished | Aug 23 06:12:09 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426200515 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3426200515 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1304860407 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 3470406847 ps |
CPU time | 156.61 seconds |
Started | Aug 23 06:11:59 AM UTC 24 |
Finished | Aug 23 06:14:38 AM UTC 24 |
Peak memory | 257500 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304860407 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.1304860407 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3975938792 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 309800203 ps |
CPU time | 8.69 seconds |
Started | Aug 23 06:12:02 AM UTC 24 |
Finished | Aug 23 06:12:12 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975938792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3975938792 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.102727788 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 165339662 ps |
CPU time | 5.08 seconds |
Started | Aug 23 06:11:59 AM UTC 24 |
Finished | Aug 23 06:12:05 AM UTC 24 |
Peak memory | 221464 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102727788 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.102727788 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.797565037 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 471282174 ps |
CPU time | 5.43 seconds |
Started | Aug 23 06:11:55 AM UTC 24 |
Finished | Aug 23 06:12:01 AM UTC 24 |
Peak memory | 221356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797565037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.797565037 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3858066762 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 7707290289 ps |
CPU time | 101.78 seconds |
Started | Aug 23 06:12:02 AM UTC 24 |
Finished | Aug 23 06:13:46 AM UTC 24 |
Peak memory | 230920 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3858066762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3858066762 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1863897218 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 250313683 ps |
CPU time | 4.58 seconds |
Started | Aug 23 06:12:13 AM UTC 24 |
Finished | Aug 23 06:12:19 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863897218 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1863897218 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3187019779 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 32408111329 ps |
CPU time | 130.01 seconds |
Started | Aug 23 06:12:11 AM UTC 24 |
Finished | Aug 23 06:14:23 AM UTC 24 |
Peak memory | 257504 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187019779 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.3187019779 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3189267089 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 168625898 ps |
CPU time | 8.66 seconds |
Started | Aug 23 06:12:11 AM UTC 24 |
Finished | Aug 23 06:12:21 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189267089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3189267089 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1452713341 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 500195601 ps |
CPU time | 7.43 seconds |
Started | Aug 23 06:12:10 AM UTC 24 |
Finished | Aug 23 06:12:18 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452713341 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1452713341 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.4013864345 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 584173904 ps |
CPU time | 10.64 seconds |
Started | Aug 23 06:12:06 AM UTC 24 |
Finished | Aug 23 06:12:17 AM UTC 24 |
Peak memory | 223456 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401386434 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.4013864345 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3290151761 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 29920644972 ps |
CPU time | 73.19 seconds |
Started | Aug 23 06:12:12 AM UTC 24 |
Finished | Aug 23 06:13:27 AM UTC 24 |
Peak memory | 232908 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3290151761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3290151761 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2056991892 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 257050547 ps |
CPU time | 4.44 seconds |
Started | Aug 23 06:12:26 AM UTC 24 |
Finished | Aug 23 06:12:32 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056991892 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2056991892 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2181873348 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 7077771084 ps |
CPU time | 120.29 seconds |
Started | Aug 23 06:12:20 AM UTC 24 |
Finished | Aug 23 06:14:22 AM UTC 24 |
Peak memory | 257540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181873348 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.2181873348 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2677422878 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 301612466 ps |
CPU time | 9.88 seconds |
Started | Aug 23 06:12:20 AM UTC 24 |
Finished | Aug 23 06:12:31 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677422878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2677422878 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2073010420 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 548719445 ps |
CPU time | 5.94 seconds |
Started | Aug 23 06:12:18 AM UTC 24 |
Finished | Aug 23 06:12:25 AM UTC 24 |
Peak memory | 221236 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073010420 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2073010420 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3268686338 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 799084351 ps |
CPU time | 9.35 seconds |
Started | Aug 23 06:12:18 AM UTC 24 |
Finished | Aug 23 06:12:29 AM UTC 24 |
Peak memory | 225416 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326868633 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.3268686338 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1175268150 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 1322113909 ps |
CPU time | 48.91 seconds |
Started | Aug 23 06:12:22 AM UTC 24 |
Finished | Aug 23 06:13:12 AM UTC 24 |
Peak memory | 230860 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1175268150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1175268150 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.896966318 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 546230286 ps |
CPU time | 6.3 seconds |
Started | Aug 23 06:12:37 AM UTC 24 |
Finished | Aug 23 06:12:45 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896966318 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.896966318 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3249277340 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 13726861709 ps |
CPU time | 153.89 seconds |
Started | Aug 23 06:12:31 AM UTC 24 |
Finished | Aug 23 06:15:08 AM UTC 24 |
Peak memory | 253536 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249277340 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.3249277340 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.821091747 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1916381374 ps |
CPU time | 9.84 seconds |
Started | Aug 23 06:12:32 AM UTC 24 |
Finished | Aug 23 06:12:43 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821091747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.821091747 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.388971199 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 100021737 ps |
CPU time | 4.97 seconds |
Started | Aug 23 06:12:30 AM UTC 24 |
Finished | Aug 23 06:12:36 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388971199 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.388971199 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1384427299 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 1106723133 ps |
CPU time | 13.41 seconds |
Started | Aug 23 06:12:30 AM UTC 24 |
Finished | Aug 23 06:12:45 AM UTC 24 |
Peak memory | 225376 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138442729 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.1384427299 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3637442493 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 3468997063 ps |
CPU time | 193.64 seconds |
Started | Aug 23 06:12:32 AM UTC 24 |
Finished | Aug 23 06:15:49 AM UTC 24 |
Peak memory | 234116 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3637442493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3637442493 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2156044787 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 250833371 ps |
CPU time | 4.49 seconds |
Started | Aug 23 06:12:54 AM UTC 24 |
Finished | Aug 23 06:13:00 AM UTC 24 |
Peak memory | 221580 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156044787 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2156044787 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1303811065 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 3101483739 ps |
CPU time | 133.58 seconds |
Started | Aug 23 06:12:46 AM UTC 24 |
Finished | Aug 23 06:15:02 AM UTC 24 |
Peak memory | 257540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303811065 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.1303811065 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3534905834 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 5481706227 ps |
CPU time | 13.8 seconds |
Started | Aug 23 06:12:46 AM UTC 24 |
Finished | Aug 23 06:13:01 AM UTC 24 |
Peak memory | 221412 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534905834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3534905834 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2643451421 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 373668451 ps |
CPU time | 4.99 seconds |
Started | Aug 23 06:12:45 AM UTC 24 |
Finished | Aug 23 06:12:51 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643451421 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2643451421 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2889228052 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 149463085 ps |
CPU time | 7.64 seconds |
Started | Aug 23 06:12:44 AM UTC 24 |
Finished | Aug 23 06:12:53 AM UTC 24 |
Peak memory | 223328 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288922805 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.2889228052 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1070068505 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 8003778442 ps |
CPU time | 134.14 seconds |
Started | Aug 23 06:12:52 AM UTC 24 |
Finished | Aug 23 06:15:08 AM UTC 24 |
Peak memory | 233100 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1070068505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1070068505 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3580225553 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 127859358 ps |
CPU time | 4.38 seconds |
Started | Aug 23 06:13:03 AM UTC 24 |
Finished | Aug 23 06:13:08 AM UTC 24 |
Peak memory | 221516 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580225553 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3580225553 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1010131001 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 50309116262 ps |
CPU time | 168.65 seconds |
Started | Aug 23 06:13:01 AM UTC 24 |
Finished | Aug 23 06:15:52 AM UTC 24 |
Peak memory | 221720 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010131001 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.1010131001 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.87561854 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 1466670116 ps |
CPU time | 9.97 seconds |
Started | Aug 23 06:13:02 AM UTC 24 |
Finished | Aug 23 06:13:13 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87561854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.87561854 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2850869466 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 197757668 ps |
CPU time | 5.71 seconds |
Started | Aug 23 06:12:55 AM UTC 24 |
Finished | Aug 23 06:13:02 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850869466 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2850869466 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2237768388 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 171028351 ps |
CPU time | 9.54 seconds |
Started | Aug 23 06:12:54 AM UTC 24 |
Finished | Aug 23 06:13:05 AM UTC 24 |
Peak memory | 223328 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223776838 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.2237768388 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1930883218 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 2094162839 ps |
CPU time | 67.46 seconds |
Started | Aug 23 06:13:02 AM UTC 24 |
Finished | Aug 23 06:14:11 AM UTC 24 |
Peak memory | 238988 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1930883218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1930883218 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1847454204 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 88080337 ps |
CPU time | 3.82 seconds |
Started | Aug 23 06:13:16 AM UTC 24 |
Finished | Aug 23 06:13:20 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847454204 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1847454204 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2170389249 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 17989239626 ps |
CPU time | 75.89 seconds |
Started | Aug 23 06:13:09 AM UTC 24 |
Finished | Aug 23 06:14:27 AM UTC 24 |
Peak memory | 257500 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170389249 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.2170389249 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1473304341 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1838775868 ps |
CPU time | 8.67 seconds |
Started | Aug 23 06:13:13 AM UTC 24 |
Finished | Aug 23 06:13:23 AM UTC 24 |
Peak memory | 221348 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473304341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1473304341 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4191473469 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 408480946 ps |
CPU time | 4.75 seconds |
Started | Aug 23 06:13:09 AM UTC 24 |
Finished | Aug 23 06:13:15 AM UTC 24 |
Peak memory | 221280 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191473469 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4191473469 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1783572102 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 592882728 ps |
CPU time | 8.85 seconds |
Started | Aug 23 06:13:06 AM UTC 24 |
Finished | Aug 23 06:13:16 AM UTC 24 |
Peak memory | 223328 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178357210 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1783572102 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4220275745 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 9141815741 ps |
CPU time | 124.77 seconds |
Started | Aug 23 06:13:13 AM UTC 24 |
Finished | Aug 23 06:15:20 AM UTC 24 |
Peak memory | 241292 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4220275745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4220275745 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2967422767 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 89097471 ps |
CPU time | 3.81 seconds |
Started | Aug 23 06:13:23 AM UTC 24 |
Finished | Aug 23 06:13:28 AM UTC 24 |
Peak memory | 221324 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967422767 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2967422767 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2797012633 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 1192965363 ps |
CPU time | 49.54 seconds |
Started | Aug 23 06:13:17 AM UTC 24 |
Finished | Aug 23 06:14:08 AM UTC 24 |
Peak memory | 253340 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797012633 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.2797012633 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3223748025 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 259587307 ps |
CPU time | 9.88 seconds |
Started | Aug 23 06:13:17 AM UTC 24 |
Finished | Aug 23 06:13:28 AM UTC 24 |
Peak memory | 221160 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223748025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3223748025 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3205890510 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 102480351 ps |
CPU time | 4.98 seconds |
Started | Aug 23 06:13:17 AM UTC 24 |
Finished | Aug 23 06:13:23 AM UTC 24 |
Peak memory | 221340 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205890510 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3205890510 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3369093548 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1087831812 ps |
CPU time | 13.22 seconds |
Started | Aug 23 06:13:16 AM UTC 24 |
Finished | Aug 23 06:13:30 AM UTC 24 |
Peak memory | 223600 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336909354 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.3369093548 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4204300943 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 1576667222 ps |
CPU time | 71.62 seconds |
Started | Aug 23 06:13:21 AM UTC 24 |
Finished | Aug 23 06:14:34 AM UTC 24 |
Peak memory | 230796 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4204300943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.4204300943 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1350616550 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 308692384 ps |
CPU time | 3.75 seconds |
Started | Aug 23 06:06:23 AM UTC 24 |
Finished | Aug 23 06:06:28 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350616550 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1350616550 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2719926007 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1584837146 ps |
CPU time | 99.68 seconds |
Started | Aug 23 06:06:20 AM UTC 24 |
Finished | Aug 23 06:08:01 AM UTC 24 |
Peak memory | 244676 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719926007 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.2719926007 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1492166645 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 1085873346 ps |
CPU time | 9.98 seconds |
Started | Aug 23 06:06:20 AM UTC 24 |
Finished | Aug 23 06:06:31 AM UTC 24 |
Peak memory | 221356 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492166645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1492166645 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2634359150 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 638439493 ps |
CPU time | 5.89 seconds |
Started | Aug 23 06:06:19 AM UTC 24 |
Finished | Aug 23 06:06:26 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634359150 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2634359150 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1286315295 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 667513333 ps |
CPU time | 5.65 seconds |
Started | Aug 23 06:06:19 AM UTC 24 |
Finished | Aug 23 06:06:25 AM UTC 24 |
Peak memory | 221352 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286315295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1286315295 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.651442656 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 664693616 ps |
CPU time | 8.43 seconds |
Started | Aug 23 06:06:19 AM UTC 24 |
Finished | Aug 23 06:06:28 AM UTC 24 |
Peak memory | 221548 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651442656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.651442656 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3150256827 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 5284286094 ps |
CPU time | 65.81 seconds |
Started | Aug 23 06:06:23 AM UTC 24 |
Finished | Aug 23 06:07:30 AM UTC 24 |
Peak memory | 230860 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3150256827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3150256827 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1851436707 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 828454453 ps |
CPU time | 3.83 seconds |
Started | Aug 23 06:06:29 AM UTC 24 |
Finished | Aug 23 06:06:34 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851436707 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1851436707 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1775180360 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 447619469 ps |
CPU time | 9.91 seconds |
Started | Aug 23 06:06:26 AM UTC 24 |
Finished | Aug 23 06:06:37 AM UTC 24 |
Peak memory | 221284 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775180360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1775180360 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2434441935 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 152846673 ps |
CPU time | 5.22 seconds |
Started | Aug 23 06:06:26 AM UTC 24 |
Finished | Aug 23 06:06:32 AM UTC 24 |
Peak memory | 221540 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434441935 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2434441935 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1693750502 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 123016664 ps |
CPU time | 5.35 seconds |
Started | Aug 23 06:06:24 AM UTC 24 |
Finished | Aug 23 06:06:30 AM UTC 24 |
Peak memory | 221044 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693750502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1693750502 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1501620393 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1110800473 ps |
CPU time | 9.06 seconds |
Started | Aug 23 06:06:24 AM UTC 24 |
Finished | Aug 23 06:06:34 AM UTC 24 |
Peak memory | 220952 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150162039 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1501620393 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.663647943 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 519405354 ps |
CPU time | 4.45 seconds |
Started | Aug 23 06:06:37 AM UTC 24 |
Finished | Aug 23 06:06:43 AM UTC 24 |
Peak memory | 221316 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663647943 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.663647943 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3819972255 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 7628571060 ps |
CPU time | 77.17 seconds |
Started | Aug 23 06:06:33 AM UTC 24 |
Finished | Aug 23 06:07:52 AM UTC 24 |
Peak memory | 253424 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819972255 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.3819972255 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3152675731 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 3321825905 ps |
CPU time | 8.65 seconds |
Started | Aug 23 06:06:34 AM UTC 24 |
Finished | Aug 23 06:06:44 AM UTC 24 |
Peak memory | 221420 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152675731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3152675731 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3832764125 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 388662579 ps |
CPU time | 5.28 seconds |
Started | Aug 23 06:06:31 AM UTC 24 |
Finished | Aug 23 06:06:37 AM UTC 24 |
Peak memory | 221528 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832764125 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3832764125 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.706666285 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 141735721 ps |
CPU time | 5.89 seconds |
Started | Aug 23 06:06:31 AM UTC 24 |
Finished | Aug 23 06:06:38 AM UTC 24 |
Peak memory | 221288 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706666285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.706666285 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2060984404 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 3067368235 ps |
CPU time | 15.19 seconds |
Started | Aug 23 06:06:31 AM UTC 24 |
Finished | Aug 23 06:06:48 AM UTC 24 |
Peak memory | 225692 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206098440 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.2060984404 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2964938498 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 1785937719 ps |
CPU time | 109.29 seconds |
Started | Aug 23 06:06:34 AM UTC 24 |
Finished | Aug 23 06:08:26 AM UTC 24 |
Peak memory | 228728 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2964938498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2964938498 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4293839722 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 517316602 ps |
CPU time | 4.53 seconds |
Started | Aug 23 06:06:49 AM UTC 24 |
Finished | Aug 23 06:06:54 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293839722 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4293839722 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3185584859 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 22649001751 ps |
CPU time | 199.1 seconds |
Started | Aug 23 06:06:44 AM UTC 24 |
Finished | Aug 23 06:10:05 AM UTC 24 |
Peak memory | 259588 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185584859 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.3185584859 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2262312053 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 340846696 ps |
CPU time | 8.59 seconds |
Started | Aug 23 06:06:45 AM UTC 24 |
Finished | Aug 23 06:06:54 AM UTC 24 |
Peak memory | 221548 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262312053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2262312053 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3708515267 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 380446968 ps |
CPU time | 5.07 seconds |
Started | Aug 23 06:06:42 AM UTC 24 |
Finished | Aug 23 06:06:49 AM UTC 24 |
Peak memory | 221528 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708515267 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3708515267 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3828741589 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 383046132 ps |
CPU time | 4.79 seconds |
Started | Aug 23 06:06:38 AM UTC 24 |
Finished | Aug 23 06:06:44 AM UTC 24 |
Peak memory | 221060 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828741589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3828741589 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.674412773 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 183197558 ps |
CPU time | 11.95 seconds |
Started | Aug 23 06:06:38 AM UTC 24 |
Finished | Aug 23 06:06:51 AM UTC 24 |
Peak memory | 225316 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674412773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.674412773 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3375217588 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 6661595670 ps |
CPU time | 178.79 seconds |
Started | Aug 23 06:06:45 AM UTC 24 |
Finished | Aug 23 06:09:46 AM UTC 24 |
Peak memory | 232908 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3375217588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3375217588 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1109542479 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 161741391 ps |
CPU time | 3.77 seconds |
Started | Aug 23 06:06:56 AM UTC 24 |
Finished | Aug 23 06:07:01 AM UTC 24 |
Peak memory | 221320 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109542479 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1109542479 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1516968408 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 979282153 ps |
CPU time | 63.43 seconds |
Started | Aug 23 06:06:55 AM UTC 24 |
Finished | Aug 23 06:08:00 AM UTC 24 |
Peak memory | 252532 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516968408 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.1516968408 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1936036530 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 542831009 ps |
CPU time | 5.76 seconds |
Started | Aug 23 06:06:52 AM UTC 24 |
Finished | Aug 23 06:06:59 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936036530 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1936036530 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1513030880 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 384919183 ps |
CPU time | 4.85 seconds |
Started | Aug 23 06:06:50 AM UTC 24 |
Finished | Aug 23 06:06:56 AM UTC 24 |
Peak memory | 221272 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513030880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1513030880 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4218898776 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 283882501 ps |
CPU time | 13.53 seconds |
Started | Aug 23 06:06:50 AM UTC 24 |
Finished | Aug 23 06:07:04 AM UTC 24 |
Peak memory | 225372 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421889877 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.4218898776 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4254017323 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2154573666 ps |
CPU time | 129.37 seconds |
Started | Aug 23 06:06:55 AM UTC 24 |
Finished | Aug 23 06:09:07 AM UTC 24 |
Peak memory | 241100 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4254017323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.rom_ctrl_stress_all_with_rand_reset.4254017323 |
Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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