| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.49 | 96.89 | 92.13 | 97.67 | 100.00 | 98.62 | 98.05 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 63.08 | 63.08 | 92.58 | 92.58 | 71.35 | 71.35 | 41.77 | 41.77 | 40.00 | 40.00 | 90.00 | 90.00 | 93.70 | 93.70 | 12.18 | 12.18 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3486436971 |
| 82.54 | 19.46 | 96.29 | 3.71 | 80.76 | 9.41 | 70.75 | 28.98 | 53.33 | 13.33 | 93.79 | 3.79 | 95.50 | 1.80 | 87.35 | 75.18 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1643035083 |
| 90.82 | 8.28 | 96.41 | 0.12 | 83.15 | 2.39 | 84.88 | 14.12 | 93.33 | 40.00 | 94.48 | 0.69 | 95.65 | 0.15 | 87.82 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1493994095 |
| 93.03 | 2.21 | 96.41 | 0.00 | 88.62 | 5.48 | 93.40 | 8.53 | 93.33 | 0.00 | 95.17 | 0.69 | 95.95 | 0.30 | 88.29 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3899267724 |
| 94.23 | 1.21 | 96.65 | 0.24 | 89.47 | 0.84 | 93.40 | 0.00 | 93.33 | 0.00 | 96.21 | 1.03 | 95.95 | 0.00 | 94.61 | 6.32 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.21066749 |
| 95.33 | 1.09 | 96.65 | 0.00 | 89.89 | 0.42 | 93.50 | 0.10 | 100.00 | 6.67 | 96.21 | 0.00 | 95.95 | 0.00 | 95.08 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1162025002 |
| 96.18 | 0.85 | 96.89 | 0.24 | 90.59 | 0.70 | 95.58 | 2.08 | 100.00 | 0.00 | 97.93 | 1.72 | 96.25 | 0.30 | 96.02 | 0.94 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1071977672 |
| 96.45 | 0.27 | 96.89 | 0.00 | 91.29 | 0.70 | 95.78 | 0.20 | 100.00 | 0.00 | 97.93 | 0.00 | 96.55 | 0.30 | 96.72 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2842889937 |
| 96.66 | 0.20 | 96.89 | 0.00 | 91.29 | 0.00 | 95.78 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.75 | 1.20 | 96.96 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3491164257 |
| 96.84 | 0.18 | 96.89 | 0.00 | 91.29 | 0.00 | 96.67 | 0.90 | 100.00 | 0.00 | 97.93 | 0.00 | 97.90 | 0.15 | 97.19 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.355584403 |
| 97.01 | 0.17 | 96.89 | 0.00 | 91.29 | 0.00 | 96.67 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.90 | 0.00 | 98.36 | 1.17 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2143147469 |
| 97.13 | 0.13 | 96.89 | 0.00 | 91.43 | 0.14 | 97.08 | 0.40 | 100.00 | 0.00 | 98.28 | 0.34 | 97.90 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1043144202 |
| 97.23 | 0.09 | 96.89 | 0.00 | 91.57 | 0.14 | 97.25 | 0.17 | 100.00 | 0.00 | 98.62 | 0.34 | 97.90 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1937060142 |
| 97.32 | 0.09 | 96.89 | 0.00 | 92.13 | 0.56 | 97.33 | 0.07 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3211316517 |
| 97.37 | 0.05 | 96.89 | 0.00 | 92.13 | 0.00 | 97.33 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.15 | 98.59 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.26416040 |
| 97.43 | 0.05 | 96.89 | 0.00 | 92.13 | 0.00 | 97.45 | 0.12 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3467905036 |
| 97.46 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.45 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1770673711 |
| 97.47 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.55 | 0.10 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2808581746 |
| 97.49 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.65 | 0.10 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2497123991 |
| 97.49 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.67 | 0.03 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2878106327 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2754269737 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3224096884 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1939800155 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2254866626 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3596080244 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1690920501 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.901124824 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3811217192 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1133474205 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.102404934 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1302036686 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2460150129 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3200551159 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.219186668 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2083452475 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2241306385 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.938779908 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2481318410 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2460107004 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.202425579 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2008740408 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.824677441 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2777926813 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1660784069 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2581255167 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2474702998 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.161143895 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1102377557 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2299283260 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3261078930 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1412294121 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1201507907 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3365624146 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1536810329 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3040609352 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3880785993 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.718763964 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.447786995 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1694588773 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2490567758 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4039282367 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3528478347 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1690978416 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3670875716 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1812535439 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1590465401 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.993301147 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.587665290 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1536729769 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1998074819 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.620700916 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3274026662 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1326512899 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.835097835 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2122607542 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2948850999 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.225615138 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.137240092 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4079417041 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3176846225 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4231066961 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4074010077 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3408659168 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.527256492 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.326127317 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2219520545 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3040778225 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.792182334 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.733434736 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3441648127 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.530940415 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1031878232 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3467494775 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2403480970 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2978325043 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1556128544 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1637236539 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.140568222 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1502923752 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3417921665 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1586955202 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4009185167 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1549718063 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2282373601 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2845104883 |
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| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1100711829 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1255748316 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.234442457 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3426200515 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1304860407 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3975938792 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.102727788 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.797565037 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3858066762 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1863897218 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3187019779 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3189267089 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1452713341 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.4013864345 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3290151761 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2056991892 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2181873348 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2677422878 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2073010420 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3268686338 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1175268150 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.896966318 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3249277340 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.821091747 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.388971199 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1384427299 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3637442493 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2156044787 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1303811065 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3534905834 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2643451421 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2889228052 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1070068505 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3580225553 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1010131001 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.87561854 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2850869466 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2237768388 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1930883218 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1847454204 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2170389249 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1473304341 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4191473469 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1783572102 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4220275745 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2967422767 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2797012633 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3223748025 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3205890510 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3369093548 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4204300943 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1350616550 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2719926007 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1492166645 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2634359150 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1286315295 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.651442656 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3150256827 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1851436707 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1775180360 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2434441935 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1693750502 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1501620393 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.663647943 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3819972255 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3152675731 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3832764125 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.706666285 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2060984404 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2964938498 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4293839722 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3185584859 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2262312053 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3708515267 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3828741589 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.674412773 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3375217588 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1109542479 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1516968408 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1936036530 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1513030880 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4218898776 |
| /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4254017323 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3211316517 | Aug 23 06:05:56 AM UTC 24 | Aug 23 06:06:01 AM UTC 24 | 1185020274 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3110086939 | Aug 23 06:05:55 AM UTC 24 | Aug 23 06:06:02 AM UTC 24 | 144013511 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2981031851 | Aug 23 06:05:56 AM UTC 24 | Aug 23 06:06:02 AM UTC 24 | 98950112 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1397373484 | Aug 23 06:05:57 AM UTC 24 | Aug 23 06:06:04 AM UTC 24 | 98901123 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3486436971 | Aug 23 06:05:55 AM UTC 24 | Aug 23 06:06:04 AM UTC 24 | 1021832131 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3262951933 | Aug 23 06:06:00 AM UTC 24 | Aug 23 06:06:04 AM UTC 24 | 523374999 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2808581746 | Aug 23 06:05:55 AM UTC 24 | Aug 23 06:06:05 AM UTC 24 | 596900638 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3173088288 | Aug 23 06:06:01 AM UTC 24 | Aug 23 06:06:07 AM UTC 24 | 98876367 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.72167307 | Aug 23 06:06:02 AM UTC 24 | Aug 23 06:06:08 AM UTC 24 | 392634783 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1071977672 | Aug 23 06:05:57 AM UTC 24 | Aug 23 06:06:09 AM UTC 24 | 1037944649 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4237189539 | Aug 23 06:06:05 AM UTC 24 | Aug 23 06:06:10 AM UTC 24 | 141694653 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3398421954 | Aug 23 06:06:05 AM UTC 24 | Aug 23 06:06:12 AM UTC 24 | 541538368 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2878106327 | Aug 23 06:05:55 AM UTC 24 | Aug 23 06:06:12 AM UTC 24 | 1251730901 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3899267724 | Aug 23 06:05:57 AM UTC 24 | Aug 23 06:06:14 AM UTC 24 | 461455043 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1631067075 | Aug 23 06:06:09 AM UTC 24 | Aug 23 06:06:15 AM UTC 24 | 152351794 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.355584403 | Aug 23 06:06:02 AM UTC 24 | Aug 23 06:06:16 AM UTC 24 | 779973128 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2097906611 | Aug 23 06:06:08 AM UTC 24 | Aug 23 06:06:17 AM UTC 24 | 525805856 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3675819768 | Aug 23 06:06:10 AM UTC 24 | Aug 23 06:06:17 AM UTC 24 | 1228329580 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1128820855 | Aug 23 06:06:06 AM UTC 24 | Aug 23 06:06:17 AM UTC 24 | 261809965 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1043144202 | Aug 23 06:06:03 AM UTC 24 | Aug 23 06:06:17 AM UTC 24 | 1970739223 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.219252730 | Aug 23 06:06:12 AM UTC 24 | Aug 23 06:06:19 AM UTC 24 | 195635995 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1575366636 | Aug 23 06:06:09 AM UTC 24 | Aug 23 06:06:19 AM UTC 24 | 169995673 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.272918316 | Aug 23 06:06:10 AM UTC 24 | Aug 23 06:06:23 AM UTC 24 | 285249473 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1632165986 | Aug 23 06:06:18 AM UTC 24 | Aug 23 06:06:23 AM UTC 24 | 168490772 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1286315295 | Aug 23 06:06:19 AM UTC 24 | Aug 23 06:06:25 AM UTC 24 | 667513333 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1008519198 | Aug 23 06:06:14 AM UTC 24 | Aug 23 06:06:25 AM UTC 24 | 593253923 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2634359150 | Aug 23 06:06:19 AM UTC 24 | Aug 23 06:06:26 AM UTC 24 | 638439493 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1350616550 | Aug 23 06:06:23 AM UTC 24 | Aug 23 06:06:28 AM UTC 24 | 308692384 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.651442656 | Aug 23 06:06:19 AM UTC 24 | Aug 23 06:06:28 AM UTC 24 | 664693616 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1693750502 | Aug 23 06:06:24 AM UTC 24 | Aug 23 06:06:30 AM UTC 24 | 123016664 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4017345117 | Aug 23 06:06:15 AM UTC 24 | Aug 23 06:06:31 AM UTC 24 | 2282554745 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1492166645 | Aug 23 06:06:20 AM UTC 24 | Aug 23 06:06:31 AM UTC 24 | 1085873346 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2434441935 | Aug 23 06:06:26 AM UTC 24 | Aug 23 06:06:32 AM UTC 24 | 152846673 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1501620393 | Aug 23 06:06:24 AM UTC 24 | Aug 23 06:06:34 AM UTC 24 | 1110800473 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1851436707 | Aug 23 06:06:29 AM UTC 24 | Aug 23 06:06:34 AM UTC 24 | 828454453 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1775180360 | Aug 23 06:06:26 AM UTC 24 | Aug 23 06:06:37 AM UTC 24 | 447619469 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3832764125 | Aug 23 06:06:31 AM UTC 24 | Aug 23 06:06:37 AM UTC 24 | 388662579 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.706666285 | Aug 23 06:06:31 AM UTC 24 | Aug 23 06:06:38 AM UTC 24 | 141735721 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1643035083 | Aug 23 06:05:55 AM UTC 24 | Aug 23 06:06:42 AM UTC 24 | 5240793084 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.663647943 | Aug 23 06:06:37 AM UTC 24 | Aug 23 06:06:43 AM UTC 24 | 519405354 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3152675731 | Aug 23 06:06:34 AM UTC 24 | Aug 23 06:06:44 AM UTC 24 | 3321825905 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3828741589 | Aug 23 06:06:38 AM UTC 24 | Aug 23 06:06:44 AM UTC 24 | 383046132 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2060984404 | Aug 23 06:06:31 AM UTC 24 | Aug 23 06:06:48 AM UTC 24 | 3067368235 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3708515267 | Aug 23 06:06:42 AM UTC 24 | Aug 23 06:06:49 AM UTC 24 | 380446968 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2208649974 | Aug 23 06:05:58 AM UTC 24 | Aug 23 06:06:49 AM UTC 24 | 566503909 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.674412773 | Aug 23 06:06:38 AM UTC 24 | Aug 23 06:06:51 AM UTC 24 | 183197558 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2842889937 | Aug 23 06:06:04 AM UTC 24 | Aug 23 06:06:54 AM UTC 24 | 137920573 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4293839722 | Aug 23 06:06:49 AM UTC 24 | Aug 23 06:06:54 AM UTC 24 | 517316602 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2262312053 | Aug 23 06:06:45 AM UTC 24 | Aug 23 06:06:54 AM UTC 24 | 340846696 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1513030880 | Aug 23 06:06:50 AM UTC 24 | Aug 23 06:06:56 AM UTC 24 | 384919183 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.1936036530 | Aug 23 06:06:52 AM UTC 24 | Aug 23 06:06:59 AM UTC 24 | 542831009 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3917463231 | Aug 23 06:06:09 AM UTC 24 | Aug 23 06:07:00 AM UTC 24 | 3456837921 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1109542479 | Aug 23 06:06:56 AM UTC 24 | Aug 23 06:07:01 AM UTC 24 | 161741391 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4218898776 | Aug 23 06:06:50 AM UTC 24 | Aug 23 06:07:04 AM UTC 24 | 283882501 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1937060142 | Aug 23 06:06:55 AM UTC 24 | Aug 23 06:07:06 AM UTC 24 | 1036146407 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.1990511355 | Aug 23 06:06:09 AM UTC 24 | Aug 23 06:07:07 AM UTC 24 | 1949068195 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1452417984 | Aug 23 06:07:01 AM UTC 24 | Aug 23 06:07:07 AM UTC 24 | 98433230 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.324638223 | Aug 23 06:07:07 AM UTC 24 | Aug 23 06:07:13 AM UTC 24 | 1132886295 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.846643496 | Aug 23 06:06:59 AM UTC 24 | Aug 23 06:07:15 AM UTC 24 | 303103258 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.656129218 | Aug 23 06:07:05 AM UTC 24 | Aug 23 06:07:16 AM UTC 24 | 521330382 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1196897697 | Aug 23 06:07:13 AM UTC 24 | Aug 23 06:07:20 AM UTC 24 | 486969185 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3343760362 | Aug 23 06:07:08 AM UTC 24 | Aug 23 06:07:25 AM UTC 24 | 633600138 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1347685607 | Aug 23 06:07:17 AM UTC 24 | Aug 23 06:07:29 AM UTC 24 | 261885349 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3150256827 | Aug 23 06:06:23 AM UTC 24 | Aug 23 06:07:30 AM UTC 24 | 5284286094 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3823694010 | Aug 23 06:07:26 AM UTC 24 | Aug 23 06:07:31 AM UTC 24 | 1037780098 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3467905036 | Aug 23 06:06:28 AM UTC 24 | Aug 23 06:07:31 AM UTC 24 | 1947741849 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1493994095 | Aug 23 06:06:03 AM UTC 24 | Aug 23 06:07:32 AM UTC 24 | 7525648285 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.886606564 | Aug 23 06:07:27 AM UTC 24 | Aug 23 06:07:35 AM UTC 24 | 514697490 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.324205928 | Aug 23 06:07:32 AM UTC 24 | Aug 23 06:07:37 AM UTC 24 | 132693335 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2753112187 | Aug 23 06:05:55 AM UTC 24 | Aug 23 06:07:42 AM UTC 24 | 5101410313 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.345013412 | Aug 23 06:07:31 AM UTC 24 | Aug 23 06:07:42 AM UTC 24 | 261687352 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2153820891 | Aug 23 06:07:36 AM UTC 24 | Aug 23 06:07:42 AM UTC 24 | 97158924 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2868975149 | Aug 23 06:05:56 AM UTC 24 | Aug 23 06:07:42 AM UTC 24 | 721182140 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1113615942 | Aug 23 06:07:27 AM UTC 24 | Aug 23 06:07:43 AM UTC 24 | 5750104263 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2712687674 | Aug 23 06:05:57 AM UTC 24 | Aug 23 06:07:44 AM UTC 24 | 1757594549 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.79771835 | Aug 23 06:07:33 AM UTC 24 | Aug 23 06:07:44 AM UTC 24 | 512548451 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1404041080 | Aug 23 06:07:43 AM UTC 24 | Aug 23 06:07:49 AM UTC 24 | 514658265 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.3844092281 | Aug 23 06:07:44 AM UTC 24 | Aug 23 06:07:51 AM UTC 24 | 141851415 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3819972255 | Aug 23 06:06:33 AM UTC 24 | Aug 23 06:07:52 AM UTC 24 | 7628571060 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.4105828116 | Aug 23 06:07:42 AM UTC 24 | Aug 23 06:07:53 AM UTC 24 | 1078491580 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.741383451 | Aug 23 06:06:17 AM UTC 24 | Aug 23 06:07:54 AM UTC 24 | 574827611 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.4214373123 | Aug 23 06:09:50 AM UTC 24 | Aug 23 06:09:57 AM UTC 24 | 533333194 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1254460155 | Aug 23 06:07:51 AM UTC 24 | Aug 23 06:07:56 AM UTC 24 | 334316980 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.132064942 | Aug 23 06:07:43 AM UTC 24 | Aug 23 06:07:56 AM UTC 24 | 699748483 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2398930225 | Aug 23 06:07:45 AM UTC 24 | Aug 23 06:07:56 AM UTC 24 | 261222884 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3846926467 | Aug 23 06:06:03 AM UTC 24 | Aug 23 06:07:59 AM UTC 24 | 11233438390 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1516968408 | Aug 23 06:06:55 AM UTC 24 | Aug 23 06:08:00 AM UTC 24 | 979282153 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3046289318 | Aug 23 06:07:54 AM UTC 24 | Aug 23 06:08:00 AM UTC 24 | 1697756671 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2719926007 | Aug 23 06:06:20 AM UTC 24 | Aug 23 06:08:01 AM UTC 24 | 1584837146 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3000788617 | Aug 23 06:07:57 AM UTC 24 | Aug 23 06:08:02 AM UTC 24 | 245638153 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3781395063 | Aug 23 06:06:08 AM UTC 24 | Aug 23 06:08:03 AM UTC 24 | 4326696957 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3503361217 | Aug 23 06:07:54 AM UTC 24 | Aug 23 06:08:04 AM UTC 24 | 197646997 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.712968500 | Aug 23 06:08:00 AM UTC 24 | Aug 23 06:08:06 AM UTC 24 | 350394467 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.2039779064 | Aug 23 06:07:57 AM UTC 24 | Aug 23 06:08:08 AM UTC 24 | 519158188 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.982094831 | Aug 23 06:08:03 AM UTC 24 | Aug 23 06:08:08 AM UTC 24 | 127486123 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1408578653 | Aug 23 06:07:01 AM UTC 24 | Aug 23 06:08:09 AM UTC 24 | 2602361443 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1162025002 | Aug 23 06:06:26 AM UTC 24 | Aug 23 06:08:09 AM UTC 24 | 6829053431 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3611005902 | Aug 23 06:08:05 AM UTC 24 | Aug 23 06:08:12 AM UTC 24 | 269374518 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1406373207 | Aug 23 06:07:57 AM UTC 24 | Aug 23 06:08:15 AM UTC 24 | 1658679850 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.3730916305 | Aug 23 06:08:10 AM UTC 24 | Aug 23 06:08:16 AM UTC 24 | 891785124 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2588468278 | Aug 23 06:08:11 AM UTC 24 | Aug 23 06:08:18 AM UTC 24 | 138024525 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.883470146 | Aug 23 06:06:12 AM UTC 24 | Aug 23 06:08:18 AM UTC 24 | 3033864749 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3311908852 | Aug 23 06:08:04 AM UTC 24 | Aug 23 06:08:18 AM UTC 24 | 861903557 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2630861411 | Aug 23 06:07:32 AM UTC 24 | Aug 23 06:08:19 AM UTC 24 | 34763353175 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1084593181 | Aug 23 06:08:08 AM UTC 24 | Aug 23 06:08:20 AM UTC 24 | 520838912 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.371302989 | Aug 23 06:08:16 AM UTC 24 | Aug 23 06:08:21 AM UTC 24 | 520259591 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1695923475 | Aug 23 06:08:10 AM UTC 24 | Aug 23 06:08:22 AM UTC 24 | 2017806469 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3160518963 | Aug 23 06:08:12 AM UTC 24 | Aug 23 06:08:22 AM UTC 24 | 1185167979 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.4001068814 | Aug 23 06:08:19 AM UTC 24 | Aug 23 06:08:25 AM UTC 24 | 384510616 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2964938498 | Aug 23 06:06:34 AM UTC 24 | Aug 23 06:08:26 AM UTC 24 | 1785937719 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.2199473726 | Aug 23 06:08:21 AM UTC 24 | Aug 23 06:08:27 AM UTC 24 | 184972153 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1966388123 | Aug 23 06:08:17 AM UTC 24 | Aug 23 06:08:28 AM UTC 24 | 1071212623 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2196767692 | Aug 23 06:08:19 AM UTC 24 | Aug 23 06:08:29 AM UTC 24 | 379192535 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3715337795 | Aug 23 06:08:23 AM UTC 24 | Aug 23 06:08:30 AM UTC 24 | 533476505 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2466609843 | Aug 23 06:07:38 AM UTC 24 | Aug 23 06:08:32 AM UTC 24 | 1356428993 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1400498941 | Aug 23 06:08:27 AM UTC 24 | Aug 23 06:08:33 AM UTC 24 | 126872717 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.4223501599 | Aug 23 06:08:29 AM UTC 24 | Aug 23 06:08:35 AM UTC 24 | 690365410 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3417525310 | Aug 23 06:08:22 AM UTC 24 | Aug 23 06:08:37 AM UTC 24 | 2717579538 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.872104887 | Aug 23 06:08:26 AM UTC 24 | Aug 23 06:08:37 AM UTC 24 | 273658232 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2782548407 | Aug 23 06:08:35 AM UTC 24 | Aug 23 06:08:40 AM UTC 24 | 333534109 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1968303385 | Aug 23 06:08:32 AM UTC 24 | Aug 23 06:08:42 AM UTC 24 | 177433456 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.84620863 | Aug 23 06:08:39 AM UTC 24 | Aug 23 06:08:45 AM UTC 24 | 138950831 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1886791577 | Aug 23 06:08:29 AM UTC 24 | Aug 23 06:08:46 AM UTC 24 | 649031108 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1652732800 | Aug 23 06:08:47 AM UTC 24 | Aug 23 06:08:52 AM UTC 24 | 153033651 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2678428747 | Aug 23 06:08:43 AM UTC 24 | Aug 23 06:08:52 AM UTC 24 | 348145760 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.339374795 | Aug 23 06:08:53 AM UTC 24 | Aug 23 06:08:59 AM UTC 24 | 164223534 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1007681576 | Aug 23 06:07:21 AM UTC 24 | Aug 23 06:09:01 AM UTC 24 | 5061794113 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.564504466 | Aug 23 06:08:37 AM UTC 24 | Aug 23 06:09:02 AM UTC 24 | 6082089060 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1340858842 | Aug 23 06:08:53 AM UTC 24 | Aug 23 06:09:05 AM UTC 24 | 405915123 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4254017323 | Aug 23 06:06:55 AM UTC 24 | Aug 23 06:09:07 AM UTC 24 | 2154573666 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3573115497 | Aug 23 06:09:03 AM UTC 24 | Aug 23 06:09:08 AM UTC 24 | 350774079 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1378745327 | Aug 23 06:09:00 AM UTC 24 | Aug 23 06:09:10 AM UTC 24 | 618567692 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4231431806 | Aug 23 06:07:07 AM UTC 24 | Aug 23 06:09:10 AM UTC 24 | 5271433386 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3971207407 | Aug 23 06:09:07 AM UTC 24 | Aug 23 06:09:14 AM UTC 24 | 1356311481 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3385402594 | Aug 23 06:09:06 AM UTC 24 | Aug 23 06:09:16 AM UTC 24 | 768609778 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3814102460 | Aug 23 06:09:14 AM UTC 24 | Aug 23 06:09:20 AM UTC 24 | 266757780 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2763526496 | Aug 23 06:09:10 AM UTC 24 | Aug 23 06:09:20 AM UTC 24 | 171604078 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1413413309 | Aug 23 06:09:16 AM UTC 24 | Aug 23 06:09:25 AM UTC 24 | 507810064 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1952723666 | Aug 23 06:07:30 AM UTC 24 | Aug 23 06:09:27 AM UTC 24 | 9284549955 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2877461107 | Aug 23 06:09:20 AM UTC 24 | Aug 23 06:09:27 AM UTC 24 | 99971006 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.89940171 | Aug 23 06:08:02 AM UTC 24 | Aug 23 06:09:28 AM UTC 24 | 10060981350 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2231073779 | Aug 23 06:07:15 AM UTC 24 | Aug 23 06:09:29 AM UTC 24 | 3024277296 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2321072494 | Aug 23 06:09:28 AM UTC 24 | Aug 23 06:09:33 AM UTC 24 | 87343487 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.1386561244 | Aug 23 06:09:53 AM UTC 24 | Aug 23 06:09:59 AM UTC 24 | 129635321 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1539227672 | Aug 23 06:09:26 AM UTC 24 | Aug 23 06:09:35 AM UTC 24 | 170391124 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2428213967 | Aug 23 06:09:30 AM UTC 24 | Aug 23 06:09:37 AM UTC 24 | 137329952 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.565987381 | Aug 23 06:08:07 AM UTC 24 | Aug 23 06:09:44 AM UTC 24 | 13705004392 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3375217588 | Aug 23 06:06:45 AM UTC 24 | Aug 23 06:09:46 AM UTC 24 | 6661595670 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3066214252 | Aug 23 06:08:30 AM UTC 24 | Aug 23 06:09:49 AM UTC 24 | 5717405576 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1565892447 | Aug 23 06:09:36 AM UTC 24 | Aug 23 06:09:51 AM UTC 24 | 1026978859 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.147119545 | Aug 23 06:08:19 AM UTC 24 | Aug 23 06:09:52 AM UTC 24 | 1668350446 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3622244593 | Aug 23 06:09:45 AM UTC 24 | Aug 23 06:09:52 AM UTC 24 | 520853402 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2881852835 | Aug 23 06:08:26 AM UTC 24 | Aug 23 06:09:53 AM UTC 24 | 4198698239 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3015356509 | Aug 23 06:07:45 AM UTC 24 | Aug 23 06:09:53 AM UTC 24 | 2811483347 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3415879252 | Aug 23 06:08:12 AM UTC 24 | Aug 23 06:09:53 AM UTC 24 | 9722101330 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.267180008 | Aug 23 06:09:29 AM UTC 24 | Aug 23 06:09:53 AM UTC 24 | 595091344 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4075904548 | Aug 23 06:07:55 AM UTC 24 | Aug 23 06:09:59 AM UTC 24 | 2733177362 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2893328366 | Aug 23 06:07:57 AM UTC 24 | Aug 23 06:09:58 AM UTC 24 | 9697421068 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2497123991 | Aug 23 06:05:57 AM UTC 24 | Aug 23 06:10:00 AM UTC 24 | 16828500055 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1728775045 | Aug 23 06:09:47 AM UTC 24 | Aug 23 06:10:02 AM UTC 24 | 2028766410 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2330497644 | Aug 23 06:09:54 AM UTC 24 | Aug 23 06:10:02 AM UTC 24 | 546418942 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3517082023 | Aug 23 06:08:23 AM UTC 24 | Aug 23 06:10:02 AM UTC 24 | 2475558787 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1334746257 | Aug 23 06:09:53 AM UTC 24 | Aug 23 06:10:03 AM UTC 24 | 665969666 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.472197202 | Aug 23 06:10:00 AM UTC 24 | Aug 23 06:10:05 AM UTC 24 | 500302175 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3185584859 | Aug 23 06:06:44 AM UTC 24 | Aug 23 06:10:05 AM UTC 24 | 22649001751 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3252792092 | Aug 23 06:09:53 AM UTC 24 | Aug 23 06:10:07 AM UTC 24 | 555181197 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3635133950 | Aug 23 06:10:01 AM UTC 24 | Aug 23 06:10:07 AM UTC 24 | 187358684 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3683990220 | Aug 23 06:09:57 AM UTC 24 | Aug 23 06:10:07 AM UTC 24 | 177701463 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3228278140 | Aug 23 06:09:37 AM UTC 24 | Aug 23 06:10:08 AM UTC 24 | 9692383756 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.10731000 | Aug 23 06:10:04 AM UTC 24 | Aug 23 06:10:09 AM UTC 24 | 133272568 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2215798773 | Aug 23 06:08:15 AM UTC 24 | Aug 23 06:10:10 AM UTC 24 | 3481294651 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3005649271 | Aug 23 06:10:06 AM UTC 24 | Aug 23 06:10:13 AM UTC 24 | 563409999 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.734765229 | Aug 23 06:10:03 AM UTC 24 | Aug 23 06:10:14 AM UTC 24 | 2080350751 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.410518153 | Aug 23 06:10:08 AM UTC 24 | Aug 23 06:10:14 AM UTC 24 | 479014031 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.1543328119 | Aug 23 06:10:00 AM UTC 24 | Aug 23 06:10:16 AM UTC 24 | 1539513543 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1732766019 | Aug 23 06:10:11 AM UTC 24 | Aug 23 06:10:17 AM UTC 24 | 193303223 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2799489027 | Aug 23 06:10:07 AM UTC 24 | Aug 23 06:10:18 AM UTC 24 | 3572045947 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2694322840 | Aug 23 06:08:41 AM UTC 24 | Aug 23 06:10:18 AM UTC 24 | 2195335429 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1731872787 | Aug 23 06:10:06 AM UTC 24 | Aug 23 06:10:19 AM UTC 24 | 283989801 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2438852421 | Aug 23 06:10:17 AM UTC 24 | Aug 23 06:10:22 AM UTC 24 | 463780123 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3773622856 | Aug 23 06:08:01 AM UTC 24 | Aug 23 06:10:22 AM UTC 24 | 4452637282 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2675048163 | Aug 23 06:10:11 AM UTC 24 | Aug 23 06:10:23 AM UTC 24 | 943526350 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.916154018 | Aug 23 06:10:15 AM UTC 24 | Aug 23 06:10:25 AM UTC 24 | 1279367694 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3206632864 | Aug 23 06:10:19 AM UTC 24 | Aug 23 06:10:26 AM UTC 24 | 138917141 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.4239655249 | Aug 23 06:10:24 AM UTC 24 | Aug 23 06:10:29 AM UTC 24 | 127071911 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3242926988 | Aug 23 06:10:17 AM UTC 24 | Aug 23 06:10:30 AM UTC 24 | 228935020 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3756890386 | Aug 23 06:10:20 AM UTC 24 | Aug 23 06:10:31 AM UTC 24 | 1660453258 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.980812350 | Aug 23 06:10:26 AM UTC 24 | Aug 23 06:10:32 AM UTC 24 | 386002104 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.857840373 | Aug 23 06:08:56 AM UTC 24 | Aug 23 06:10:34 AM UTC 24 | 16261965526 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3603953516 | Aug 23 06:10:24 AM UTC 24 | Aug 23 06:10:37 AM UTC 24 | 424221230 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3311072435 | Aug 23 06:10:32 AM UTC 24 | Aug 23 06:10:38 AM UTC 24 | 1130520823 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1183700537 | Aug 23 06:10:32 AM UTC 24 | Aug 23 06:10:39 AM UTC 24 | 351598820 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2978346372 | Aug 23 06:10:30 AM UTC 24 | Aug 23 06:10:40 AM UTC 24 | 305282590 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3881276582 | Aug 23 06:10:34 AM UTC 24 | Aug 23 06:10:41 AM UTC 24 | 96540550 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2376153183 | Aug 23 06:09:10 AM UTC 24 | Aug 23 06:10:45 AM UTC 24 | 1724216506 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2216797909 | Aug 23 06:10:41 AM UTC 24 | Aug 23 06:10:46 AM UTC 24 | 131825808 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.242438150 | Aug 23 06:10:39 AM UTC 24 | Aug 23 06:10:48 AM UTC 24 | 762097007 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.315089573 | Aug 23 06:10:46 AM UTC 24 | Aug 23 06:10:52 AM UTC 24 | 98511922 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.143307773 | Aug 23 06:10:41 AM UTC 24 | Aug 23 06:10:53 AM UTC 24 | 832138953 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2701710556 | Aug 23 06:08:46 AM UTC 24 | Aug 23 06:11:00 AM UTC 24 | 8076675692 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.42379360 | Aug 23 06:10:55 AM UTC 24 | Aug 23 06:11:00 AM UTC 24 | 520030716 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.84017153 | Aug 23 06:10:49 AM UTC 24 | Aug 23 06:11:00 AM UTC 24 | 1041542280 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2338238665 | Aug 23 06:11:01 AM UTC 24 | Aug 23 06:11:07 AM UTC 24 | 369841005 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1343627392 | Aug 23 06:09:54 AM UTC 24 | Aug 23 06:11:07 AM UTC 24 | 5508361299 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3931377048 | Aug 23 06:09:08 AM UTC 24 | Aug 23 06:11:11 AM UTC 24 | 15210541614 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2006358805 | Aug 23 06:11:01 AM UTC 24 | Aug 23 06:11:12 AM UTC 24 | 224678759 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3010538488 | Aug 23 06:10:31 AM UTC 24 | Aug 23 06:11:13 AM UTC 24 | 2142708291 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.179335091 | Aug 23 06:10:14 AM UTC 24 | Aug 23 06:11:15 AM UTC 24 | 10444623861 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2738144695 | Aug 23 06:09:51 AM UTC 24 | Aug 23 06:11:15 AM UTC 24 | 1776910944 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3825094468 | Aug 23 06:11:12 AM UTC 24 | Aug 23 06:11:17 AM UTC 24 | 89085915 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1893295385 | Aug 23 06:11:08 AM UTC 24 | Aug 23 06:11:19 AM UTC 24 | 3331916239 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2729580205 | Aug 23 06:09:22 AM UTC 24 | Aug 23 06:11:20 AM UTC 24 | 3999181392 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1193372559 | Aug 23 06:11:13 AM UTC 24 | Aug 23 06:11:20 AM UTC 24 | 384459906 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3561085091 | Aug 23 06:11:20 AM UTC 24 | Aug 23 06:11:24 AM UTC 24 | 88993734 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3163543507 | Aug 23 06:11:16 AM UTC 24 | Aug 23 06:11:26 AM UTC 24 | 581400561 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1941356819 | Aug 23 06:10:27 AM UTC 24 | Aug 23 06:11:26 AM UTC 24 | 4755056793 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2095704893 | Aug 23 06:11:13 AM UTC 24 | Aug 23 06:11:27 AM UTC 24 | 866296369 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1669516025 | Aug 23 06:11:21 AM UTC 24 | Aug 23 06:11:27 AM UTC 24 | 266411319 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.395507820 | Aug 23 06:11:21 AM UTC 24 | Aug 23 06:11:29 AM UTC 24 | 132768970 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2915279565 | Aug 23 06:11:27 AM UTC 24 | Aug 23 06:11:33 AM UTC 24 | 129931904 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.649724939 | Aug 23 06:10:07 AM UTC 24 | Aug 23 06:11:33 AM UTC 24 | 1450450465 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1869067640 | Aug 23 06:09:28 AM UTC 24 | Aug 23 06:11:35 AM UTC 24 | 3984038831 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3867892632 | Aug 23 06:11:28 AM UTC 24 | Aug 23 06:11:35 AM UTC 24 | 143011333 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.956719956 | Aug 23 06:11:25 AM UTC 24 | Aug 23 06:11:36 AM UTC 24 | 260630297 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2743551487 | Aug 23 06:11:36 AM UTC 24 | Aug 23 06:11:41 AM UTC 24 | 127779049 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3741604296 | Aug 23 06:11:37 AM UTC 24 | Aug 23 06:11:43 AM UTC 24 | 96842497 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2295213085 | Aug 23 06:11:34 AM UTC 24 | Aug 23 06:11:45 AM UTC 24 | 3546575746 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3070659167 | Aug 23 06:11:28 AM UTC 24 | Aug 23 06:11:46 AM UTC 24 | 1226178765 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2587645262 | Aug 23 06:10:03 AM UTC 24 | Aug 23 06:11:46 AM UTC 24 | 2591885012 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1295612945 | Aug 23 06:09:58 AM UTC 24 | Aug 23 06:11:51 AM UTC 24 | 7652867003 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1968648022 | Aug 23 06:09:02 AM UTC 24 | Aug 23 06:11:52 AM UTC 24 | 5223993466 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.4048662255 | Aug 23 06:11:36 AM UTC 24 | Aug 23 06:11:52 AM UTC 24 | 309427389 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3032923307 | Aug 23 06:11:43 AM UTC 24 | Aug 23 06:11:53 AM UTC 24 | 171778834 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.4054801324 | Aug 23 06:11:47 AM UTC 24 | Aug 23 06:11:53 AM UTC 24 | 2472223447 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1100711829 | Aug 23 06:11:52 AM UTC 24 | Aug 23 06:11:59 AM UTC 24 | 272648700 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3293079604 | Aug 23 06:11:54 AM UTC 24 | Aug 23 06:11:59 AM UTC 24 | 248057866 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1255748316 | Aug 23 06:11:47 AM UTC 24 | Aug 23 06:12:01 AM UTC 24 | 319652407 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.797565037 | Aug 23 06:11:55 AM UTC 24 | Aug 23 06:12:01 AM UTC 24 | 471282174 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3987148315 | Aug 23 06:11:53 AM UTC 24 | Aug 23 06:12:02 AM UTC 24 | 348798783 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.102727788 | Aug 23 06:11:59 AM UTC 24 | Aug 23 06:12:05 AM UTC 24 | 165339662 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3426200515 | Aug 23 06:12:04 AM UTC 24 | Aug 23 06:12:09 AM UTC 24 | 1392650288 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2430926084 | Aug 23 06:09:34 AM UTC 24 | Aug 23 06:12:10 AM UTC 24 | 6504042927 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2421046395 | Aug 23 06:07:49 AM UTC 24 | Aug 23 06:12:10 AM UTC 24 | 17307291025 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1806380194 | Aug 23 06:10:03 AM UTC 24 | Aug 23 06:12:11 AM UTC 24 | 4499936373 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3975938792 | Aug 23 06:12:02 AM UTC 24 | Aug 23 06:12:12 AM UTC 24 | 309800203 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.4013864345 | Aug 23 06:12:06 AM UTC 24 | Aug 23 06:12:17 AM UTC 24 | 584173904 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1679729801 | Aug 23 06:10:19 AM UTC 24 | Aug 23 06:12:18 AM UTC 24 | 2580295989 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1452713341 | Aug 23 06:12:10 AM UTC 24 | Aug 23 06:12:18 AM UTC 24 | 500195601 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1863897218 | Aug 23 06:12:13 AM UTC 24 | Aug 23 06:12:19 AM UTC 24 | 250313683 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3189267089 | Aug 23 06:12:11 AM UTC 24 | Aug 23 06:12:21 AM UTC 24 | 168625898 ps |
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