|  |  |  |  |  |  |  |     
    
tb  | 
 97.23 | 
 96.89 | 
 92.13 | 
 97.67 | 
100.00 | 
 98.62 | 
 98.05 | 
    
    
| dut | 
 97.23 | 
 96.89 | 
 92.13 | 
 97.67 | 
100.00 | 
 98.62 | 
 98.05 | 
    
    
| gen_alert_tx[0].u_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_fsm_scramble_enabled.u_checker_fsm | 
 98.02 | 
100.00 | 
 98.15 | 
 90.00 | 
100.00 | 
100.00 | 
100.00 | 
    
    
| u_compare | 
 97.95 | 
100.00 | 
 97.67 | 
 90.00 | 
100.00 | 
100.00 | 
100.00 | 
    
    
| u_done_sender | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_flops.u_prim_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prim_count_addr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_counter | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_rom_scramble_enabled.u_rom | 
 97.06 | 
 88.24 | 
 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| u_prince | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_rom | 
 94.44 | 
 83.33 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_prim_rom | 
 88.89 | 
 66.67 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_generic.u_impl_generic | 
 88.89 | 
 66.67 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_seed_anchor | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_sp_addr | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| regs_tlul_assert_device | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| rom_ctrl_regs_csr_assert | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| rom_tlul_assert_device | 
 99.30 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 97.90 | 
    
    
| u_mux | 
 95.24 | 
100.00 | 
 85.71 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sel_bus_q_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sel_bus_qq_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_reg_regs | 
 99.72 | 
 99.41 | 
 99.21 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| u_alert_test | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_chk | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
100.00 | 
    
    
| u_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_dec | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_digest_0 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_1 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_2 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_3 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_4 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_5 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_6 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_digest_7 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_0 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_1 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_2 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_3 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_4 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_5 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_6 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exp_digest_7 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_fatal_alert_cause_checker_error | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_fatal_alert_cause_integrity_error | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_reg_we_check | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_onehot_check | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_reg_if | 
 98.67 | 
 97.14 | 
 97.53 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_rsp_intg_gen | 
 83.33 | 
 66.67 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_rsp_intg_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_data_intg.u_tlul_data_integ_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rsp_intg.u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tl_adapter_rom | 
 93.03 | 
 90.70 | 
 82.58 | 
 97.66 | 
 | 
 94.20 | 
100.00 | 
    
    
| gen_cmd_intg_check.u_cmd_intg_chk | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
100.00 | 
    
    
| u_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_dec | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_reqfifo | 
 94.41 | 
100.00 | 
 82.05 | 
 90.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 95.33 | 
100.00 | 
 91.30 | 
 90.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_rsp_intg.u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_rspfifo | 
 95.02 | 
100.00 | 
 85.11 | 
 90.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 95.33 | 
100.00 | 
 91.30 | 
 90.00 | 
 | 
100.00 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| u_sram_byte | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_sramreqfifo | 
 90.36 | 
100.00 | 
 71.79 | 
 90.00 | 
 | 
 90.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 84.82 | 
100.00 | 
 82.61 | 
 90.00 | 
 | 
 66.67 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
 90.00 | 
 | 
 | 
 90.00 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_data | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_instr | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tl_rom_h2d_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 |