Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

551288

1

T2

43

T3

82

T4

38

full_word

343019

1

T2

6

T3

8

T4

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	894027	1			T2	49		T3	90		T4	47
auto[TlIntgErrCmd]	106	1			T63	4		T64	6		T65	3
auto[TlIntgErrData]	87	1			T63	3		T64	4		T65	5
auto[TlIntgErrBoth]	87	1			T63	3		T65	2		T123	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164243

1

T2

49

T3

90

T4

47

auto[1]

730064

1

T11

5728

T12

7765

T13

4189

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	80690	1			T2	43		T3	82		T4	38
auto[TlIntgErrNone]	partial	auto[1]	470344	1			T11	3898		T12	5136		T13	2655
auto[TlIntgErrNone]	full_word	auto[0]	83428	1			T2	6		T3	8		T4	9
auto[TlIntgErrNone]	full_word	auto[1]	259565	1			T11	1830		T12	2629		T13	1534
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T64	5		T123	1		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T63	4		T64	1		T65	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T126	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T127	1		T121	2		T128	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T64	2		T65	2		T123	2
auto[TlIntgErrData]	partial	auto[1]	37	1			T63	2		T64	2		T65	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T63	1		T127	1		T129	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T65	1		T120	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T123	3		T125	1		T119	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T63	3		T65	2		T123	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T125	1		T131	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T123	1		T119	1		T127	1