Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

615358

1

T1

38

T2

22

T3

300

full_word

389248

1

T1

2

T2

2

T3

36

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1004306	1			T1	40		T2	24		T3	336
auto[TlIntgErrCmd]	93	1			T55	5		T56	2		T57	1
auto[TlIntgErrData]	117	1			T55	3		T56	4		T57	4
auto[TlIntgErrBoth]	90	1			T55	2		T56	4		T57	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179213

1

T1

40

T2

24

T3

336

auto[1]

825393

1

T11

5884

T12

7674

T13

2290

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	85338	1			T1	38		T2	22		T3	300
auto[TlIntgErrNone]	partial	auto[1]	529747	1			T11	3419		T12	4665		T13	1277
auto[TlIntgErrNone]	full_word	auto[0]	93739	1			T1	2		T2	2		T3	36
auto[TlIntgErrNone]	full_word	auto[1]	295482	1			T11	2465		T12	3009		T13	1013
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T55	1		T56	1		T103	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T55	3		T57	1		T104	2
auto[TlIntgErrCmd]	full_word	auto[1]	12	1			T55	1		T56	1		T103	3
auto[TlIntgErrData]	partial	auto[0]	50	1			T55	1		T56	2		T57	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T55	2		T56	2		T57	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T105	1		T106	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T108	2		T105	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T55	1		T56	2		T57	3
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T55	1		T56	2		T57	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T57	1		T109	1		T110	2