Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

623789

1

T1

19

T2

161

T3

49

full_word

384546

1

T1

2

T2

25

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1008045	1			T1	21		T2	186		T3	56
auto[TlIntgErrCmd]	107	1			T58	2		T59	6		T60	6
auto[TlIntgErrData]	87	1			T58	1		T59	2		T60	1
auto[TlIntgErrBoth]	96	1			T58	7		T59	2		T60	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181404

1

T1

21

T2

186

T3

56

auto[1]

826931

1

T15

8495

T16

14325

T17

1827

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	88316	1			T1	19		T2	161		T3	49
auto[TlIntgErrNone]	partial	auto[1]	535208	1			T15	5094		T16	9801		T17	1340
auto[TlIntgErrNone]	full_word	auto[0]	92969	1			T1	2		T2	25		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	291552	1			T15	3401		T16	4524		T17	487
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T59	1		T60	1		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T58	2		T59	4		T60	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T59	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T120	1		T121	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T59	1		T60	1		T120	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T58	1		T59	1		T118	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T111	1		T119	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T114	1		T119	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T58	3		T60	2		T120	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T58	3		T59	2		T120	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T58	1		T119	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T60	1		T111	1		T121	1