Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

554304

1

T1

46

T2

180

T3

62

full_word

345156

1

T1

1

T2

20

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	899130	1			T1	47		T2	200		T3	64
auto[TlIntgErrCmd]	102	1			T72	3		T73	3		T74	1
auto[TlIntgErrData]	123	1			T72	3		T73	2		T74	4
auto[TlIntgErrBoth]	105	1			T72	4		T73	5		T74	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160682

1

T1

47

T2

200

T3

64

auto[1]

738778

1

T14

5567

T15

8895

T16

8984

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	77379	1			T1	46		T2	180		T3	62
auto[TlIntgErrNone]	partial	auto[1]	476625	1			T14	3528		T15	5474		T16	5695
auto[TlIntgErrNone]	full_word	auto[0]	83162	1			T1	1		T2	20		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	261964	1			T14	2039		T15	3421		T16	3289
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T72	1		T73	3		T120	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T72	2		T74	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T127	1		T125	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T119	1		T129	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T72	2		T118	2		T123	2
auto[TlIntgErrData]	partial	auto[1]	58	1			T73	2		T74	4		T120	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T72	1		T120	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T121	2		T130	3		T131	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T72	3		T74	2		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T72	1		T73	5		T74	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T124	1		T129	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T74	1		T123	1		T121	1