Line Coverage for Module :
tlul_adapter_reg
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 38 | 38 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| ALWAYS | 95 | 6 | 6 | 100.00 |
| ALWAYS | 101 | 8 | 8 | 100.00 |
| ALWAYS | 141 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 208 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
| ALWAYS | 218 | 3 | 3 | 100.00 |
76
77 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready;
Tests: T1 T2 T3
78 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready;
Tests: T1 T2 T3
79 // Request signal
80 1/1 assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData));
Tests: T1 T3 T4
81 1/1 assign rd_req = a_ack & (tl_i.a_opcode == Get);
Tests: T1 T3 T4
82
83 1/1 assign we_o = wr_req & ~err_internal;
Tests: T1 T3 T4
84 1/1 assign re_o = rd_req & ~err_internal;
Tests: T1 T3 T4
85 1/1 assign wdata_o = tl_i.a_data;
Tests: T1 T3 T4
86 1/1 assign be_o = tl_i.a_mask;
Tests: T1 T3 T4
87
88 if (RegAw <= 2) begin : gen_only_one_reg
89 assign addr_o = '0;
90 end else begin : gen_more_regs
91 1/1 assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align
Tests: T1 T3 T4
92 end
93
94 always_ff @(posedge clk_i or negedge rst_ni) begin
95 2/2 if (!rst_ni) outstanding_q <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
96 2/2 else if (a_ack) outstanding_q <= 1'b1;
Tests: T1 T2 T3 | T1 T3 T4
97 2/2 else if (d_ack) outstanding_q <= 1'b0;
Tests: T1 T2 T3 | T1 T3 T4
MISSING_ELSE
98 end
99
100 always_ff @(posedge clk_i or negedge rst_ni) begin
101 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
102 1/1 reqid_q <= '0;
Tests: T1 T2 T3
103 1/1 reqsz_q <= '0;
Tests: T1 T2 T3
104 1/1 rspop_q <= AccessAck;
Tests: T1 T2 T3
105 1/1 end else if (a_ack) begin
Tests: T1 T2 T3
106 1/1 reqid_q <= tl_i.a_source;
Tests: T1 T3 T4
107 1/1 reqsz_q <= tl_i.a_size;
Tests: T1 T3 T4
108 // Return AccessAckData regardless of error
109 1/1 rspop_q <= (rd_req) ? AccessAckData : AccessAck ;
Tests: T1 T3 T4
110 end
MISSING_ELSE
111 end
112
113 if (AccessLatency == 1) begin : gen_access_latency1
114 logic wr_req_q, rd_req_q;
115 always_ff @(posedge clk_i or negedge rst_ni) begin
116 if (!rst_ni) begin
117 rdata_q <= '0;
118 error_q <= 1'b0;
119 wr_req_q <= 1'b0;
120 rd_req_q <= 1'b0;
121 end else begin
122 rd_req_q <= rd_req;
123 wr_req_q <= wr_req;
124 // Addressing phase
125 if (a_ack) begin
126 error_q <= err_internal;
127 // Response phase
128 end else begin
129 error_q <= error;
130 rdata_q <= rdata;
131 end
132 end
133 end
134 assign rdata = (error_i || error_q || wr_req_q) ? '1 :
135 (rd_req_q) ? rdata_i :
136 rdata_q; // backpressure case
137 assign error = (rd_req_q || wr_req_q) ? (error_q || error_i) :
138 error_q; // backpressure case
139 end else begin : gen_access_latency0
140 always_ff @(posedge clk_i or negedge rst_ni) begin
141 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
142 1/1 rdata_q <= '0;
Tests: T1 T2 T3
143 1/1 error_q <= 1'b0;
Tests: T1 T2 T3
144 1/1 end else if (a_ack) begin
Tests: T1 T2 T3
145 1/1 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i;
Tests: T1 T3 T4
146 1/1 error_q <= error_i || err_internal;
Tests: T1 T3 T4
147 end
MISSING_ELSE
148 end
149 1/1 assign rdata = rdata_q;
Tests: T1 T2 T3
150 1/1 assign error = error_q;
Tests: T1 T2 T3
151 end
152
153 tlul_pkg::tl_d2h_t tl_o_pre;
154 1/1 assign tl_o_pre = '{
Tests: T1 T2 T3
155 // busy is selected based on address
156 // thus if there is no valid transaction, we should ignore busy
157 a_ready: ~(outstanding_q | tl_i.a_valid & busy_i),
158 d_valid: outstanding_q,
159 d_opcode: rspop_q,
160 d_param: '0,
161 d_size: reqsz_q,
162 d_source: reqid_q,
163 d_sink: '0,
164 d_data: rdata,
165 d_user: '0,
166 d_error: error
167 };
168
169 // outgoing integrity generation
170 tlul_rsp_intg_gen #(
171 .EnableRspIntgGen(EnableRspIntgGen),
172 .EnableDataIntgGen(EnableDataIntgGen)
173 ) u_rsp_intg_gen (
174 .tl_i(tl_o_pre),
175 .tl_o(tl_o)
176 );
177
178 if (CmdIntgCheck) begin : gen_cmd_intg_check
179 logic intg_error_q;
180 tlul_cmd_intg_chk u_cmd_intg_chk (
181 .tl_i(tl_i),
182 .err_o(intg_error)
183 );
184 // permanently latch integrity error until reset
185 always_ff @(posedge clk_i or negedge rst_ni) begin
186 if (!rst_ni) begin
187 intg_error_q <= 1'b0;
188 end else if (intg_error) begin
189 intg_error_q <= 1'b1;
190 end
191 end
192 assign intg_error_o = intg_error_q;
193 end else begin : gen_no_cmd_intg_check
194 assign intg_error = 1'b0;
195 assign intg_error_o = 1'b0;
196 end
197
198 ////////////////////
199 // Error Handling //
200 ////////////////////
201
202 // An instruction type transaction is only valid if en_ifetch is enabled
203 // If the instruction type is completely invalid, also considered an instruction error
204 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) |
Tests: T1 T3 T4
205 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
206 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i));
207
208 1/1 assign err_internal = addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error;
Tests: T1 T3 T4
209
210 // Don't allow unsupported values.
211 1/1 assign malformed_meta_err = tl_a_user_chk(tl_i.a_user);
Tests: T1 T3 T4
212
213 // addr_align_err
214 // Raised if addr isn't aligned with the size
215 // Read size error is checked in tlul_assert.sv
216 // Here is it added due to the limitation of register interface.
217 always_comb begin
218 1/1 if (wr_req) begin
Tests: T1 T3 T4
219 // Only word-align is accepted based on comportability spec
220 1/1 addr_align_err = |tl_i.a_address[1:0];
Tests: T4 T9 T17
221 end else begin
222 // No request
223 1/1 addr_align_err = 1'b0;
Tests: T1 T3 T4
Cond Coverage for Module :
tlul_adapter_reg
| Total | Covered | Percent |
|---|
| Conditions | 46 | 44 | 95.65 |
| Logical | 46 | 44 | 95.65 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 77
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 78
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 80
EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
--1-- ----------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T7,T9 |
| 1 | 0 | Covered | T1,T3,T5 |
| 1 | 1 | Covered | T4,T9,T17 |
LINE 80
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T3,T5 |
| 0 | 1 | Covered | T4,T7,T9 |
| 1 | 0 | Covered | T4,T7,T9 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T9 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T9 |
LINE 81
EXPRESSION (a_ack & (tl_i.a_opcode == Get))
--1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T5 |
| 1 | 0 | Covered | T4,T9,T17 |
| 1 | 1 | Covered | T1,T3,T5 |
LINE 81
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T5 |
LINE 83
EXPRESSION (wr_req & ((~err_internal)))
---1-- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T4,T9,T17 |
LINE 84
EXPRESSION (rd_req & ((~err_internal)))
---1-- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T1,T3,T5 |
LINE 109
EXPRESSION (rd_req ? AccessAckData : AccessAck)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T9,T17 |
| 1 | Covered | T1,T3,T5 |
LINE 145
EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T3,T5 |
| 1 | Covered | T4,T9,T17 |
LINE 145
SUB-EXPRESSION (error_i || err_internal || wr_req)
---1--- ------2----- ---3--
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T3,T5 |
| 0 | 0 | 1 | Covered | T4,T9,T17 |
| 0 | 1 | 0 | Covered | T14,T15,T16 |
| 1 | 0 | 0 | Covered | T14,T15,T16 |
LINE 146
EXPRESSION (error_i || err_internal)
---1--- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T3,T4 |
| 0 | 1 | Covered | T14,T15,T16 |
| 1 | 0 | Covered | T14,T15,T16 |
LINE 154
SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T3,T4 |
LINE 154
SUB-EXPRESSION (tl_i.a_valid & busy_i)
------1----- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Unreachable | |
LINE 208
EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
-------1------ ---------2-------- ---3-- -----4----- -----5----
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T4 |
| 0 | 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 0 | 1 | 0 | Not Covered | |
| 0 | 0 | 1 | 0 | 0 | Covered | T7,T12,T33 |
| 0 | 1 | 0 | 0 | 0 | Not Covered | |
| 1 | 0 | 0 | 0 | 0 | Covered | T14,T15,T16 |
Branch Coverage for Module :
tlul_adapter_reg
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| IF |
95 |
4 |
4 |
100.00 |
| IF |
101 |
4 |
4 |
100.00 |
| IF |
218 |
2 |
2 |
100.00 |
| IF |
141 |
4 |
4 |
100.00 |
95 if (!rst_ni) outstanding_q <= 1'b0;
-1-
==>
96 else if (a_ack) outstanding_q <= 1'b1;
-2-
==>
97 else if (d_ack) outstanding_q <= 1'b0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T3,T4 |
| 0 |
0 |
1 |
Covered |
T1,T3,T4 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
101 if (!rst_ni) begin
-1-
102 reqid_q <= '0;
==>
103 reqsz_q <= '0;
104 rspop_q <= AccessAck;
105 end else if (a_ack) begin
-2-
106 reqid_q <= tl_i.a_source;
107 reqsz_q <= tl_i.a_size;
108 // Return AccessAckData regardless of error
109 rspop_q <= (rd_req) ? AccessAckData : AccessAck ;
-3-
==>
==>
110 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
Covered |
T1,T3,T5 |
| 0 |
1 |
0 |
Covered |
T4,T9,T17 |
| 0 |
0 |
- |
Covered |
T1,T2,T3 |
218 if (wr_req) begin
-1-
219 // Only word-align is accepted based on comportability spec
220 addr_align_err = |tl_i.a_address[1:0];
==>
221 end else begin
222 // No request
223 addr_align_err = 1'b0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T9,T17 |
| 0 |
Covered |
T1,T3,T4 |
141 if (!rst_ni) begin
-1-
142 rdata_q <= '0;
==>
143 error_q <= 1'b0;
144 end else if (a_ack) begin
-2-
145 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i;
-3-
==>
==>
146 error_q <= error_i || err_internal;
147 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
Covered |
T4,T9,T17 |
| 0 |
1 |
0 |
Covered |
T1,T3,T5 |
| 0 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_reg
Assertion Details
AllowedLatency_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
456 |
456 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
MatchedWidthAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
456 |
456 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |