Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

646619

1

T1

41

T2

330

T3

68

full_word

407129

1

T1

4

T2

34

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1053468	1			T1	45		T2	364		T3	70
auto[TlIntgErrCmd]	87	1			T50	3		T51	3		T52	3
auto[TlIntgErrData]	110	1			T50	4		T51	11		T52	5
auto[TlIntgErrBoth]	83	1			T50	3		T51	6		T52	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

186971

1

T1

45

T2

364

T3

70

auto[1]

866777

1

T11

4584

T12

16592

T13

3317

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	88514	1			T1	41		T2	330		T3	68
auto[TlIntgErrNone]	partial	auto[1]	557848	1			T11	2889		T12	10463		T13	2290
auto[TlIntgErrNone]	full_word	auto[0]	98332	1			T1	4		T2	34		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	308774	1			T11	1695		T12	6129		T13	1027
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T107	2		T103	2		T111	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T50	3		T51	2		T52	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T51	1		T111	1		T106	3
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T107	1		T113	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T50	4		T51	5		T52	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T51	6		T52	2		T107	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T111	1		T114	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T52	1		T112	1		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T50	2		T103	3		T111	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T50	1		T51	6		T52	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T109	1		T106	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T115	1		T116	1		-	-